From patchwork Tue Jun 27 20:14:17 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Marijn Suijten X-Patchwork-Id: 696959 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id B66D0C0015E for ; Tue, 27 Jun 2023 20:14:33 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230449AbjF0UOb (ORCPT ); Tue, 27 Jun 2023 16:14:31 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:35782 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230253AbjF0UOa (ORCPT ); Tue, 27 Jun 2023 16:14:30 -0400 Received: from relay05.th.seeweb.it (relay05.th.seeweb.it [5.144.164.166]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 945251BC5 for ; Tue, 27 Jun 2023 13:14:26 -0700 (PDT) Received: from Marijn-Arch-PC.localdomain (94-211-6-86.cable.dynamic.v4.ziggo.nl [94.211.6.86]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (2048 bits) server-digest SHA256) (No client certificate requested) by m-r2.th.seeweb.it (Postfix) with ESMTPSA id D26F53F73D; Tue, 27 Jun 2023 22:14:23 +0200 (CEST) From: Marijn Suijten Date: Tue, 27 Jun 2023 22:14:17 +0200 Subject: [PATCH v2 02/15] arm64: dts: qcom: sm6125: Sort spmi_bus node numerically by reg MIME-Version: 1.0 Message-Id: <20230627-sm6125-dpu-v2-2-03e430a2078c@somainline.org> References: <20230627-sm6125-dpu-v2-0-03e430a2078c@somainline.org> In-Reply-To: <20230627-sm6125-dpu-v2-0-03e430a2078c@somainline.org> To: Andy Gross , Bjorn Andersson , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Michael Turquette , Stephen Boyd , Rob Clark , Abhinav Kumar , Dmitry Baryshkov , Sean Paul , David Airlie , Daniel Vetter , Krishna Manikandan , Marijn Suijten , Loic Poulain , Konrad Dybcio Cc: ~postmarketos/upstreaming@lists.sr.ht, AngeloGioacchino Del Regno , Konrad Dybcio , Martin Botka , Jami Kettunen , linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Krzysztof Kozlowski , linux-clk@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, Lux Aliaga X-Mailer: b4 0.12.3 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org This node has always resided in the wrong spot, making it somewhat harder to contribute new node entries while maintaining proper sorting around it. Move the node up to sit after hsusb_phy1 where it maintains proper numerical sorting on the (first of its many) reg address property. Fixes: cff4bbaf2a2d ("arm64: dts: qcom: Add support for SM6125") Reviewed-by: Konrad Dybcio Signed-off-by: Marijn Suijten --- arch/arm64/boot/dts/qcom/sm6125.dtsi | 38 ++++++++++++++++++------------------ 1 file changed, 19 insertions(+), 19 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sm6125.dtsi b/arch/arm64/boot/dts/qcom/sm6125.dtsi index a596baa6ce3e..722dde560bec 100644 --- a/arch/arm64/boot/dts/qcom/sm6125.dtsi +++ b/arch/arm64/boot/dts/qcom/sm6125.dtsi @@ -679,6 +679,24 @@ hsusb_phy1: phy@1613000 { status = "disabled"; }; + spmi_bus: spmi@1c40000 { + compatible = "qcom,spmi-pmic-arb"; + reg = <0x01c40000 0x1100>, + <0x01e00000 0x2000000>, + <0x03e00000 0x100000>, + <0x03f00000 0xa0000>, + <0x01c0a000 0x26000>; + reg-names = "core", "chnls", "obsrvr", "intr", "cnfg"; + interrupt-names = "periph_irq"; + interrupts = ; + qcom,ee = <0>; + qcom,channel = <0>; + #address-cells = <2>; + #size-cells = <0>; + interrupt-controller; + #interrupt-cells = <4>; + }; + rpm_msg_ram: sram@45f0000 { compatible = "qcom,rpm-msg-ram"; reg = <0x045f0000 0x7000>; @@ -1184,27 +1202,9 @@ sram@4690000 { reg = <0x04690000 0x10000>; }; - spmi_bus: spmi@1c40000 { - compatible = "qcom,spmi-pmic-arb"; - reg = <0x01c40000 0x1100>, - <0x01e00000 0x2000000>, - <0x03e00000 0x100000>, - <0x03f00000 0xa0000>, - <0x01c0a000 0x26000>; - reg-names = "core", "chnls", "obsrvr", "intr", "cnfg"; - interrupt-names = "periph_irq"; - interrupts = ; - qcom,ee = <0>; - qcom,channel = <0>; - #address-cells = <2>; - #size-cells = <0>; - interrupt-controller; - #interrupt-cells = <4>; - }; - apps_smmu: iommu@c600000 { compatible = "qcom,sm6125-smmu-500", "qcom,smmu-500", "arm,mmu-500"; - reg = <0xc600000 0x80000>; + reg = <0x0c600000 0x80000>; interrupts = , , ,