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[178.235.187.166]) by smtp.gmail.com with ESMTPSA id o11-20020a1709061d4b00b009faca59cf38sm8160232ejh.182.2023.11.29.10.59.29 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 29 Nov 2023 10:59:30 -0800 (PST) From: Konrad Dybcio Date: Wed, 29 Nov 2023 19:59:20 +0100 Subject: [PATCH v2 01/15] clk: qcom: branch: Add a helper for setting the enable bit Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20230717-topic-branch_aon_cleanup-v2-1-2a583460ef26@linaro.org> References: <20230717-topic-branch_aon_cleanup-v2-0-2a583460ef26@linaro.org> In-Reply-To: <20230717-topic-branch_aon_cleanup-v2-0-2a583460ef26@linaro.org> To: Bjorn Andersson , Andy Gross , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: Marijn Suijten , linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, Konrad Dybcio , Johan Hovold X-Mailer: b4 0.12.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1701284367; l=1349; i=konrad.dybcio@linaro.org; s=20230215; h=from:subject:message-id; bh=e6Fwd/o/2qWMn5DgIB1LfGYNT4yrpvovsVT/9DIkQR4=; b=+eEk+TghBsnLCZCKRQBNiCy3J6n0y4kWQbmKrrzMtwEQaCMfUHZIhn/PXAAtWGh1WSlPcpZLZ AYyrU1b4m2KAB/2TLILjlEznLF0x+to14cnRrP7UPF/6jqVKtktGyiV X-Developer-Key: i=konrad.dybcio@linaro.org; a=ed25519; pk=iclgkYvtl2w05SSXO5EjjSYlhFKsJ+5OSZBjOkQuEms= We hardcode some clocks to be always-on, as they're essential to the functioning of the SoC / some peripherals. Add a helper to do so to make the writes less magic. Reviewed-by: Johan Hovold Signed-off-by: Konrad Dybcio Reviewed-by: Bryan O'Donoghue --- drivers/clk/qcom/clk-branch.h | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/drivers/clk/qcom/clk-branch.h b/drivers/clk/qcom/clk-branch.h index 0cf800b9d08d..155818cc8d49 100644 --- a/drivers/clk/qcom/clk-branch.h +++ b/drivers/clk/qcom/clk-branch.h @@ -47,6 +47,7 @@ struct clk_branch { #define CBCR_FORCE_MEM_PERIPH_OFF BIT(12) #define CBCR_WAKEUP GENMASK(11, 8) #define CBCR_SLEEP GENMASK(7, 4) +#define CBCR_CLOCK_ENABLE BIT(0) static inline void qcom_branch_set_force_mem_core(struct regmap *regmap, struct clk_branch clk, bool on) @@ -81,6 +82,12 @@ static inline void qcom_branch_set_sleep(struct regmap *regmap, struct clk_branc FIELD_PREP(CBCR_SLEEP, val)); } +static inline void qcom_branch_set_clk_en(struct regmap *regmap, u32 cbcr) +{ + regmap_update_bits(regmap, cbcr, CBCR_CLOCK_ENABLE, + CBCR_CLOCK_ENABLE); +} + extern const struct clk_ops clk_branch_ops; extern const struct clk_ops clk_branch2_ops; extern const struct clk_ops clk_branch_simple_ops;