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[212.182.62.129]) by smtp.gmail.com with ESMTPSA id v6-20020a2e2f06000000b002c9f939598csm2184518ljv.70.2023.12.14.16.01.15 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 14 Dec 2023 16:01:16 -0800 (PST) From: Konrad Dybcio Date: Fri, 15 Dec 2023 01:01:09 +0100 Subject: [PATCH 2/3] arm64: dts: qcom: msm8996: Hook up MPM Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20231215-topic-mpm_dt-v1-2-c6636fc75ce3@linaro.org> References: <20231215-topic-mpm_dt-v1-0-c6636fc75ce3@linaro.org> In-Reply-To: <20231215-topic-mpm_dt-v1-0-c6636fc75ce3@linaro.org> To: Andy Gross , Bjorn Andersson , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: Konrad Dybcio , linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Konrad Dybcio X-Mailer: b4 0.13-dev-0438c Wire up MPM and the interrupts it provides. Signed-off-by: Konrad Dybcio --- arch/arm64/boot/dts/qcom/msm8996.dtsi | 39 +++++++++++++++++++++++++++++------ 1 file changed, 33 insertions(+), 6 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/msm8996.dtsi b/arch/arm64/boot/dts/qcom/msm8996.dtsi index 35a0d2a69711..11e3fe4f342f 100644 --- a/arch/arm64/boot/dts/qcom/msm8996.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8996.dtsi @@ -444,6 +444,25 @@ memory@80000000 { reg = <0x0 0x80000000 0x0 0x0>; }; + mpm: interrupt-controller { + compatible = "qcom,mpm"; + qcom,rpm-msg-ram = <&apss_mpm>; + interrupts = ; + mboxes = <&apcs_glb 1>; + interrupt-controller; + #interrupt-cells = <2>; + #power-domain-cells = <0>; + interrupt-parent = <&intc>; + qcom,mpm-pin-count = <96>; + qcom,mpm-pin-map = <2 184>, /* TSENS1 upper_lower_int */ + <52 243>, /* DWC3_PRI ss_phy_irq */ + <79 347>, /* DWC3_PRI hs_phy_irq */ + <80 352>, /* DWC3_SEC hs_phy_irq */ + <81 347>, /* QUSB2_PHY_PRI DP+DM */ + <82 352>, /* QUSB2_PHY_SEC DP+DM */ + <87 326>; /* SPMI */ + }; + psci { compatible = "arm,psci-1.0"; method = "smc"; @@ -733,8 +752,15 @@ pciephy_2: phy@3000 { }; rpm_msg_ram: sram@68000 { - compatible = "qcom,rpm-msg-ram"; + compatible = "qcom,rpm-msg-ram", "mmio-sram"; reg = <0x00068000 0x6000>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x00068000 0x7000>; + + apss_mpm: sram@1b8 { + reg = <0x1b8 0x48>; + }; }; qfprom@74000 { @@ -820,8 +846,8 @@ tsens1: thermal-sensor@4ad000 { reg = <0x004ad000 0x1000>, /* TM */ <0x004ac000 0x1000>; /* SROT */ #qcom,sensors = <8>; - interrupts = , - ; + interrupts-extended = <&mpm 2 IRQ_TYPE_LEVEL_HIGH>, + <&intc GIC_SPI 430 IRQ_TYPE_LEVEL_HIGH>; interrupt-names = "uplow", "critical"; #thermal-sensor-cells = <1>; }; @@ -1343,6 +1369,7 @@ tlmm: pinctrl@1010000 { interrupts = ; gpio-controller; gpio-ranges = <&tlmm 0 0 150>; + wakeup-parent = <&mpm>; #gpio-cells = <2>; interrupt-controller; #interrupt-cells = <2>; @@ -1870,7 +1897,7 @@ spmi_bus: spmi@400f000 { <0x0400a000 0x002100>; reg-names = "core", "chnls", "obsrvr", "intr", "cnfg"; interrupt-names = "periph_irq"; - interrupts = ; + interrupts-extended = <&mpm 87 IRQ_TYPE_LEVEL_HIGH>; qcom,ee = <0>; qcom,channel = <0>; #address-cells = <2>; @@ -3026,8 +3053,8 @@ usb3: usb@6af8800 { #size-cells = <1>; ranges; - interrupts = , - ; + interrupts-extended = <&mpm 79 IRQ_TYPE_LEVEL_HIGH>, + <&mpm 52 IRQ_TYPE_LEVEL_HIGH>; interrupt-names = "hs_phy_irq", "ss_phy_irq"; clocks = <&gcc GCC_SYS_NOC_USB3_AXI_CLK>,