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[178.235.179.206]) by smtp.gmail.com with ESMTPSA id i11-20020a170906250b00b00a233a4c4a30sm3782036ejb.90.2023.12.19.10.55.36 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 19 Dec 2023 10:55:37 -0800 (PST) From: Konrad Dybcio Date: Tue, 19 Dec 2023 19:55:32 +0100 Subject: [PATCH 1/2] clk: qcom: gpucc-sm8650: Add test_ctl parameters to PLL config Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20231219-topic-8650_clks-v1-1-5672bfa0eb05@linaro.org> References: <20231219-topic-8650_clks-v1-0-5672bfa0eb05@linaro.org> In-Reply-To: <20231219-topic-8650_clks-v1-0-5672bfa0eb05@linaro.org> To: Bjorn Andersson , Michael Turquette , Stephen Boyd , Neil Armstrong Cc: Marijn Suijten , linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, Konrad Dybcio X-Mailer: b4 0.12.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1703012135; l=1040; i=konrad.dybcio@linaro.org; s=20230215; h=from:subject:message-id; bh=zp+MxlirxZfTXZcMa6Fu/HzTuCmSGvfkPNhTYEzcqFg=; b=1/rs3+CvYSQP7zIJMC0zR6ci2MufS9LgIUcL1e1f3xNZDzrxA0LPTn1a4zmcsUWutvEs/L3K1 KJ2sH1dhTKfCIr4za4tsO8OmnQRy8mNy5xlxti0Iy8E9wYRuZQHUXdT X-Developer-Key: i=konrad.dybcio@linaro.org; a=ed25519; pk=iclgkYvtl2w05SSXO5EjjSYlhFKsJ+5OSZBjOkQuEms= These values were missing. Add them. Fixes: 8676fd4f3874 ("clk: qcom: add the SM8650 GPU Clock Controller driver") Signed-off-by: Konrad Dybcio --- drivers/clk/qcom/gpucc-sm8650.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/clk/qcom/gpucc-sm8650.c b/drivers/clk/qcom/gpucc-sm8650.c index 5ae494e17ee4..03307e482aca 100644 --- a/drivers/clk/qcom/gpucc-sm8650.c +++ b/drivers/clk/qcom/gpucc-sm8650.c @@ -50,6 +50,7 @@ static const struct alpha_pll_config gpu_cc_pll0_config = { .test_ctl_val = 0x00000000, .test_ctl_hi_val = 0x00000003, .test_ctl_hi1_val = 0x00009000, + .test_ctl_hi2_val = 0x00000034, .user_ctl_val = 0x00000000, .user_ctl_hi_val = 0x00000005, }; @@ -80,6 +81,7 @@ static const struct alpha_pll_config gpu_cc_pll1_config = { .test_ctl_val = 0x00000000, .test_ctl_hi_val = 0x00000003, .test_ctl_hi1_val = 0x00009000, + .test_ctl_hi2_val = 0x00000034, .user_ctl_val = 0x00000000, .user_ctl_hi_val = 0x00000005, };