From patchwork Tue Mar 19 10:44:29 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Neil Armstrong X-Patchwork-Id: 781188 Received: from mail-wr1-f47.google.com (mail-wr1-f47.google.com [209.85.221.47]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id DA1C37D410 for ; Tue, 19 Mar 2024 10:44:44 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.221.47 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1710845086; cv=none; b=C0Y2QxZwy3MYBVLdZiYw5Tj9AnQ2gYyMgpkTUlo4EU7DqRTkQqjYixTlHgyO2xIhxaxu1LOxUTJ2rweTgiLbZusjJ7a9TWpE/aAArwhc+Ot8R/WGY+vJ45bjQ23I8quSjySI5+ZA9UBKPEbnCWAfc0suvajZB6MZhhP+r0OmJ+M= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1710845086; c=relaxed/simple; bh=WsGgAE39xLO1WpNxrXfF0aN/WkAyS4SNo1d7Voxy384=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=GTIT6pEF0qOjoGsJWwuVsp/c3ds5OQeZ0qomRSqbbOCfgv1TssfcF04Hg1UJ7YR4Ri89G3XnvZTJSHPfhgiHOe8pFPH3njBm1/cvnruDh8eH3SkgW7snwZP3M/k+W3uq6AEwk2aaB0fMlvND0BRk0Gx4KFmaDOSuhmHB3yDu0y8= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org; spf=pass smtp.mailfrom=linaro.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b=efau+ci0; arc=none smtp.client-ip=209.85.221.47 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linaro.org Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="efau+ci0" Received: by mail-wr1-f47.google.com with SMTP id ffacd0b85a97d-3417a3151c4so1357202f8f.3 for ; Tue, 19 Mar 2024 03:44:44 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1710845083; x=1711449883; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=vaUDxu1aSxyRZXnYFOND1HceBfA/6o9Fk2GBTMCjqhg=; b=efau+ci0WufP7mMygXekY6fy7NIRO4WNproaFaPgGndVeWOSMij8hPDEA+WhjMAP+F sXqCQ5V4E0seGy7JkOO/D/TH9XOaoLgTu32PfGgIoDTN/2Ut1wSbFJOFXCZX1ikPzcVk RrQV9AWA2Ih64zTfvNZrIN56GYQll/vrlfd4pKK+Asu2XJ7CiYlIkxwS9277zqNfnw5m horJ31L+AJbRfSHFtNAyizEgfG4i5ngO3cyxLvO3eLQ64Cc01whjJ+tK8oeYhzJ3eyBN UyEG1G0VqOXKIY9FLB1UUWzZSAUJW9CISUKclKJxK1NRgQdJblGpkR5syjbSrA1U+8Vl HX0Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1710845083; x=1711449883; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=vaUDxu1aSxyRZXnYFOND1HceBfA/6o9Fk2GBTMCjqhg=; b=uY95b8HfgMhTEncvZ33mDlXPjkFDb2aZEh62KW3NntSwvH+xZcX/eusXxYNWomPxro K2WMd7syU3hHaYd7UPlt7rCX8IrJxqwX3+OhfxAnUpmXLu4Dk1mpYrys8icfSr4BPu7H zwt6+/CY0Q3l4JKTLe4guKStTu46XQkKJdjNzCwv1wxpIVJyYaGXC738PO+k1Sf+hcA4 7aGFVZYy3GHpVfsC+7NbH46YFhjlBZ8HYVVFvRDmfwz67tkNGnKML/ZU3/5hgTpzDgeL jZpYd6DmjnRxSHkIlmIu2RxX8+3u264VyQS/s2E1TEPU/LTu4fFfhp8SBYt3dSpdG1xN BrNw== X-Gm-Message-State: AOJu0YxP/pE5Ln9qnyDzlm15KR5NN0BXrFNHgjSjyHtiYQB95/1QcyPC deWlnCVooh7nen9Tz6X59j0K6gbul7fuykmrXz9xXCtPe9wim14NxXtVsbxpnxs= X-Google-Smtp-Source: AGHT+IEI8FAubESL+OiWqRmez4YrJyHkp0zhMaROfLEYoQuQYkJSDscEjausMNnTYtuORRoHxflksw== X-Received: by 2002:a5d:420e:0:b0:33f:6ec1:56dd with SMTP id n14-20020a5d420e000000b0033f6ec156ddmr7618246wrq.45.1710845083167; Tue, 19 Mar 2024 03:44:43 -0700 (PDT) Received: from arrakeen.starnux.net ([2a01:e0a:982:cbb0:52eb:f6ff:feb3:451a]) by smtp.gmail.com with ESMTPSA id a5-20020a5d4d45000000b0033e03a6b1ecsm12029459wru.18.2024.03.19.03.44.42 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 19 Mar 2024 03:44:42 -0700 (PDT) From: Neil Armstrong Date: Tue, 19 Mar 2024 11:44:29 +0100 Subject: [PATCH 3/7] phy: qcom: qmp-pcie: register second optional PHY AUX clock Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20240319-topic-sm8x50-upstream-pcie-1-phy-aux-clk-v1-3-926d7a4ccd80@linaro.org> References: <20240319-topic-sm8x50-upstream-pcie-1-phy-aux-clk-v1-0-926d7a4ccd80@linaro.org> In-Reply-To: <20240319-topic-sm8x50-upstream-pcie-1-phy-aux-clk-v1-0-926d7a4ccd80@linaro.org> To: Bjorn Andersson , Konrad Dybcio , Vinod Koul , Kishon Vijay Abraham I , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: linux-arm-msm@vger.kernel.org, linux-phy@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Neil Armstrong X-Mailer: b4 0.12.4 X-Developer-Signature: v=1; a=openpgp-sha256; l=3998; i=neil.armstrong@linaro.org; h=from:subject:message-id; bh=WsGgAE39xLO1WpNxrXfF0aN/WkAyS4SNo1d7Voxy384=; b=owEBbQKS/ZANAwAKAXfc29rIyEnRAcsmYgBl+WyVxmma2DSKw3/90m56VEW2t4wrDj06AsVmW6xr jurjn3aJAjMEAAEKAB0WIQQ9U8YmyFYF/h30LIt33NvayMhJ0QUCZflslQAKCRB33NvayMhJ0eJ7EA Ci49/QyBonFj6tTlibAF/GecKy1f4werx+qj80VTNMHp4lnZqaFjmcd5Mf36y+mo8ejHbBNVJk448Q TXtX8ILRoQzCPl4EhvAJIKLQdqoS9jynPhkVnN/BfMvt4Z3KGwIQGjNCcBjJZJdo2LVBs6qlWGsivm Lwru5OgO1kRvo0JYWs9INIqH2Pkua4sen+yy4repsxhxS1+pnY3Cbt+ijHz7Meq/BmJKjQ51iPoR1o uoB0Mk9xEPgAHTZZKA214XRQL2UsvUsf3V//3wuHX5Qu5GrEZ2XVNxwDw3hD1gyYFXNNac12iGWVYu Xi5pT5vu0HkqR9bGSepW2fKD+rAvqUpWqRJ2MDzSjrtX2i0K/7mQP79ZtZiJ1UQhraZyJkiWmwH44m 8TAaLzuQhsPoAQtcfCmYnkXI4uU+INxioz23jM1kFZ2tsqevV5Top4womKXrL0xt0FfSDFnerrGWNr eqUD1iQ7PYDRYg0qh7O6WpkJHEEOiioIFSmTMBPgAF8/N475ppBZJ8n3HZcTiAOpUdtmFeC9WxHJli v1lo+blY9rjF7fmF3Bdf3VOLa7kZ6/esa1aZNHKOlls8R38Bdv6m2Xhr87ZvQZ6tbLSeJTmLkNLMid x8sC12HuRi8gFf9hB8eUEj6p813xjDgMr0BoYTnxpBxOP8CvB+bGmMtvTM4A== X-Developer-Key: i=neil.armstrong@linaro.org; a=openpgp; fpr=89EC3D058446217450F22848169AB7B1A4CFF8AE The PCIe Gen4x2 PHY found in the SM8[456]50 SoCs have a second clock, add the code to register it for PHYs configs that sets a aux_clock_rate. In order to get the right clock, add qmp_pcie_clk_hw_get() which uses the newly introduced QMP_PCIE_PIPE_CLK & QMP_PCIE_PHY_AUX_CLK clock IDs and also supports the legacy bindings by returning the PIPE clock. Signed-off-by: Neil Armstrong --- drivers/phy/qualcomm/phy-qcom-qmp-pcie.c | 70 ++++++++++++++++++++++++++++++++ 1 file changed, 70 insertions(+) diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c b/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c index 079b3e306489..2d05226ae200 100644 --- a/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c +++ b/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c @@ -22,6 +22,8 @@ #include #include +#include + #include "phy-qcom-qmp-common.h" #include "phy-qcom-qmp.h" @@ -2389,6 +2391,9 @@ struct qmp_phy_cfg { /* QMP PHY pipe clock interface rate */ unsigned long pipe_clock_rate; + + /* QMP PHY AUX clock interface rate */ + unsigned long aux_clock_rate; }; struct qmp_pcie { @@ -2420,6 +2425,7 @@ struct qmp_pcie { int mode; struct clk_fixed_rate pipe_clk_fixed; + struct clk_fixed_rate aux_clk_fixed; }; static inline void qphy_setbits(void __iomem *base, u32 offset, u32 val) @@ -3681,6 +3687,62 @@ static int phy_pipe_clk_register(struct qmp_pcie *qmp, struct device_node *np) return devm_clk_hw_register(qmp->dev, &fixed->hw); } +/* + * Register a fixed rate PHY aux clock. + * + * The _phy_aux_clksrc generated by PHY goes to the GCC that gate + * controls it. The _phy_aux_clk coming out of the GCC is requested + * by the PHY driver for its operations. + * We register the _phy_aux_clksrc here. The gcc driver takes care + * of assigning this _phy_aux_clksrc as parent to _phy_aux_clk. + * Below picture shows this relationship. + * + * +---------------+ + * | PHY block |<<---------------------------------------------+ + * | | | + * | +-------+ | +-----+ | + * I/P---^-->| PLL |---^--->phy_aux_clksrc--->| GCC |--->phy_aux_clk---+ + * clk | +-------+ | +-----+ + * +---------------+ + */ +static int phy_aux_clk_register(struct qmp_pcie *qmp, struct device_node *np) +{ + struct clk_fixed_rate *fixed = &qmp->aux_clk_fixed; + struct clk_init_data init = { }; + int ret; + + ret = of_property_read_string_index(np, "clock-output-names", 1, &init.name); + if (ret) { + dev_err(qmp->dev, "%pOFn: No clock-output-names index 1\n", np); + return ret; + } + + init.ops = &clk_fixed_rate_ops; + + fixed->fixed_rate = qmp->cfg->aux_clock_rate; + fixed->hw.init = &init; + + return devm_clk_hw_register(qmp->dev, &fixed->hw); +} + +static struct clk_hw *qmp_pcie_clk_hw_get(struct of_phandle_args *clkspec, void *data) +{ + struct qmp_pcie *qmp = data; + + /* Support legacy bindings */ + if (!clkspec->args_count) + return &qmp->pipe_clk_fixed.hw; + + switch (clkspec->args[0]) { + case QMP_PCIE_PIPE_CLK: + return &qmp->pipe_clk_fixed.hw; + case QMP_PCIE_PHY_AUX_CLK: + return &qmp->aux_clk_fixed.hw; + } + + return ERR_PTR(-EINVAL); +} + static int qmp_pcie_register_clocks(struct qmp_pcie *qmp, struct device_node *np) { int ret; @@ -3689,6 +3751,14 @@ static int qmp_pcie_register_clocks(struct qmp_pcie *qmp, struct device_node *np if (ret) return ret; + if (qmp->cfg->aux_clock_rate) { + ret = phy_aux_clk_register(qmp, np); + if (ret) + return ret; + + return devm_of_clk_add_hw_provider(qmp->dev, qmp_pcie_clk_hw_get, qmp); + } + return devm_of_clk_add_hw_provider(qmp->dev, of_clk_hw_simple_get, &qmp->pipe_clk_fixed.hw); }