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Thu, 21 Mar 2024 04:16:54 -0700 (PDT) Received: from [127.0.1.1] ([2409:40f4:102b:a64b:d832:a82a:837c:6d3]) by smtp.gmail.com with ESMTPSA id ka6-20020a056a00938600b006e7324d32bbsm5531120pfb.122.2024.03.21.04.16.49 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 21 Mar 2024 04:16:53 -0700 (PDT) From: Manivannan Sadhasivam Date: Thu, 21 Mar 2024 16:46:24 +0530 Subject: [PATCH v2 04/21] arm64: dts: qcom: sm8350: Add PCIe bridge node Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20240321-pcie-qcom-bridge-dts-v2-4-1eb790c53e43@linaro.org> References: <20240321-pcie-qcom-bridge-dts-v2-0-1eb790c53e43@linaro.org> In-Reply-To: <20240321-pcie-qcom-bridge-dts-v2-0-1eb790c53e43@linaro.org> To: Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Conor Dooley , cros-qcom-dts-watchers@chromium.org, Rob Herring Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Manivannan Sadhasivam X-Mailer: b4 0.12.4 X-Developer-Signature: v=1; a=openpgp-sha256; l=1223; i=manivannan.sadhasivam@linaro.org; h=from:subject:message-id; bh=IUhajlMiebMRXpZMv8IJ+rUpDu9cL/zwabR+phBMHXo=; b=owEBbQGS/pANAwAKAVWfEeb+kc71AcsmYgBl/BcJkQBTU7cHMjQHCmaE8rE5vqzECiSajk6OF 58uXgQKlRaJATMEAAEKAB0WIQRnpUMqgUjL2KRYJ5dVnxHm/pHO9QUCZfwXCQAKCRBVnxHm/pHO 9ar9B/4lkmGZ9w867Lq+7Ob1yb3R8dwMvftktOgUQSmPnhqRIvQc8Xs10jR1g9dEEhft8UfUTg0 BUUTD3UDVxPZE5jGB+Q/Hy5It4wqPlfcVeadsi3W6AUk6eRWlTzAlZArG9g2ASEbJENOhl/kprZ IvU2axd9wH9oy2j2rPO3dTRgIcrKYYWRmrfL5PCz1gr2ztQI4jzHZ3T501tNMl85XikHvKvvntV 3zYGzO3PN0ipEdoeLKrzL74DDNImbXnQjoHwycHXH4LvPNuVBY7SPDcFPoj84CJoT1Sx3k65LvN MiEHka6VZz7y7a/Y0WiekYEuFnOTbG4akpP5xzeTj6QgCAWT X-Developer-Key: i=manivannan.sadhasivam@linaro.org; a=openpgp; fpr=C668AEC3C3188E4C611465E7488550E901166008 On Qcom SoCs, the PCIe host bridge is connected to a single PCIe bridge for each controller instance. Hence, add a node to represent the bridge. Signed-off-by: Manivannan Sadhasivam --- arch/arm64/boot/dts/qcom/sm8350.dtsi | 20 ++++++++++++++++++++ 1 file changed, 20 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm8350.dtsi b/arch/arm64/boot/dts/qcom/sm8350.dtsi index a5e7dbbd8c6c..a7346b817400 100644 --- a/arch/arm64/boot/dts/qcom/sm8350.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8350.dtsi @@ -1572,6 +1572,16 @@ pcie0: pcie@1c00000 { phy-names = "pciephy"; status = "disabled"; + + pcie@0 { + device_type = "pci"; + reg = <0x0 0x0 0x0 0x0 0x0>; + bus-range = <0x01 0xff>; + + #address-cells = <3>; + #size-cells = <2>; + ranges; + }; }; pcie0_phy: phy@1c06000 { @@ -1669,6 +1679,16 @@ pcie1: pcie@1c08000 { phy-names = "pciephy"; status = "disabled"; + + pcie@0 { + device_type = "pci"; + reg = <0x0 0x0 0x0 0x0 0x0>; + bus-range = <0x01 0xff>; + + #address-cells = <3>; + #size-cells = <2>; + ranges; + }; }; pcie1_phy: phy@1c0e000 {