[v2,05/21] arm64: dts: qcom: sm8450: Add PCIe bridge node

Message ID	20240321-pcie-qcom-bridge-dts-v2-5-1eb790c53e43@linaro.org
State	Accepted
Commit	4261fd53582df00dc7d3a384a552c35d76ab0ace
Headers	show Received: from mail-oa1-f48.google.com (mail-oa1-f48.google.com [209.85.160.48]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id AC24E58ACC for <linux-arm-msm@vger.kernel.org>; Thu, 21 Mar 2024 11:16:59 +0000 (UTC) From: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Date: Thu, 21 Mar 2024 16:46:25 +0530 Subject: [PATCH v2 05/21] arm64: dts: qcom: sm8450: Add PCIe bridge node Precedence: bulk MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 7bit Message-Id: <20240321-pcie-qcom-bridge-dts-v2-5-1eb790c53e43@linaro.org> References: <20240321-pcie-qcom-bridge-dts-v2-0-1eb790c53e43@linaro.org> In-Reply-To: <20240321-pcie-qcom-bridge-dts-v2-0-1eb790c53e43@linaro.org> To: Bjorn Andersson <andersson@kernel.org>, Konrad Dybcio <konrad.dybcio@linaro.org>, Rob Herring <robh+dt@kernel.org>, Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>, Conor Dooley <conor+dt@kernel.org>, cros-qcom-dts-watchers@chromium.org, Rob Herring <robh@kernel.org> Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>, Neil Armstrong <neil.armstrong@linaro.org>
Series	Add PCIe bridge node in DT for Qcom SoCs \| expand [v2,00/21] Add PCIe bridge node in DT for Qcom SoCs [v2,01/21] arm64: dts: qcom: sm8250: Add PCIe bridge node [v2,02/21] arm64: dts: qcom: sdm845: Add PCIe bridge node [v2,03/21] arm64: dts: qcom: sm8150: Add PCIe bridge node [v2,04/21] arm64: dts: qcom: sm8350: Add PCIe bridge node [v2,05/21] arm64: dts: qcom: sm8450: Add PCIe bridge node [v2,06/21] arm64: dts: qcom: sm8550: Add PCIe bridge node [v2,07/21] arm64: dts: qcom: sm8650: Add PCIe bridge node [v2,08/21] arm64: dts: qcom: sa8775p: Add PCIe bridge node [v2,09/21] arm64: dts: qcom: sc8280xp: Add PCIe bridge node [v2,10/21] arm64: dts: qcom: msm8998: Add PCIe bridge node [v2,11/21] arm64: dts: qcom: sc7280: Add PCIe bridge node [v2,12/21] arm64: dts: qcom: qcs404: Add PCIe bridge node [v2,13/21] arm64: dts: qcom: sc8180x: Add PCIe bridge node [v2,14/21] arm64: dts: qcom: msm8996: Add PCIe bridge node [v2,15/21] arm64: dts: qcom: ipq8074: Add PCIe bridge node [v2,16/21] arm64: dts: qcom: ipq6018: Add PCIe bridge node [v2,17/21] ARM: dts: qcom: ipq8064: Add PCIe bridge node [v2,18/21] ARM: dts: qcom: ipq4019: Add PCIe bridge node [v2,19/21] ARM: dts: qcom: apq8064: Add PCIe bridge node [v2,20/21] ARM: dts: qcom: sdx55: Add PCIe bridge node [v2,21/21] arm64: dts: qcom: sm8650: Use "pcie" as the node name instead of "pci"

Message ID

20240321-pcie-qcom-bridge-dts-v2-5-1eb790c53e43@linaro.org

State

Accepted

Commit

4261fd53582df00dc7d3a384a552c35d76ab0ace

Headers

From: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Date: Thu, 21 Mar 2024 16:46:25 +0530
Subject: [PATCH v2 05/21] arm64: dts: qcom: sm8450: Add PCIe bridge node
Precedence: bulk
MIME-Version: 1.0
Content-Type: text/plain; charset="utf-8"
Content-Transfer-Encoding: 7bit
Message-Id: <20240321-pcie-qcom-bridge-dts-v2-5-1eb790c53e43@linaro.org>
References: <20240321-pcie-qcom-bridge-dts-v2-0-1eb790c53e43@linaro.org>
In-Reply-To: <20240321-pcie-qcom-bridge-dts-v2-0-1eb790c53e43@linaro.org>
To: Bjorn Andersson <andersson@kernel.org>,
 Konrad Dybcio <konrad.dybcio@linaro.org>, Rob Herring <robh+dt@kernel.org>,
 Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
 Conor Dooley <conor+dt@kernel.org>, cros-qcom-dts-watchers@chromium.org,
 Rob Herring <robh@kernel.org>
Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org,
 linux-kernel@vger.kernel.org,
 Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>,
 Neil Armstrong <neil.armstrong@linaro.org>

Series

Add PCIe bridge node in DT for Qcom SoCs | expand

Commit Message

Manivannan Sadhasivam March 21, 2024, 11:16 a.m. UTC

On Qcom SoCs, the PCIe host bridge is connected to a single PCIe bridge
for each controller instance. Hence, add a node to represent the bridge.

Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>
Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
---
 arch/arm64/boot/dts/qcom/sm8450.dtsi | 20 ++++++++++++++++++++
 1 file changed, 20 insertions(+)

diff --git a/arch/arm64/boot/dts/qcom/sm8450.dtsi b/arch/arm64/boot/dts/qcom/sm8450.dtsi
index b86be34a912b..b42e44b922de 100644
--- a/arch/arm64/boot/dts/qcom/sm8450.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm8450.dtsi
@@ -1850,6 +1850,16 @@  pcie0: pcie@1c00000 {
 			pinctrl-0 = <&pcie0_default_state>;
 
 			status = "disabled";
+
+			pcie@0 {
+				device_type = "pci";
+				reg = <0x0 0x0 0x0 0x0 0x0>;
+				bus-range = <0x01 0xff>;
+
+				#address-cells = <3>;
+				#size-cells = <2>;
+				ranges;
+			};
 		};
 
 		pcie0_phy: phy@1c06000 {
@@ -1971,6 +1981,16 @@  pcie1: pcie@1c08000 {
 			pinctrl-0 = <&pcie1_default_state>;
 
 			status = "disabled";
+
+			pcie@0 {
+				device_type = "pci";
+				reg = <0x0 0x0 0x0 0x0 0x0>;
+				bus-range = <0x01 0xff>;
+
+				#address-cells = <3>;
+				#size-cells = <2>;
+				ranges;
+			};
 		};
 
 		pcie1_phy: phy@1c0e000 {

[v2,05/21] arm64: dts: qcom: sm8450: Add PCIe bridge node

Commit Message

Patch