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Wed, 10 Jul 2024 11:08:35 GMT Received: from hu-krichai-hyd.qualcomm.com (10.80.80.8) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Wed, 10 Jul 2024 04:08:30 -0700 From: Krishna chaitanya chundru Date: Wed, 10 Jul 2024 16:38:15 +0530 Subject: [PATCH v7 2/4] PCI: qcom-ep: Add support for D-state change notification Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-ID: <20240710-dstate_notifier-v7-2-8d45d87b2b24@quicinc.com> References: <20240710-dstate_notifier-v7-0-8d45d87b2b24@quicinc.com> In-Reply-To: <20240710-dstate_notifier-v7-0-8d45d87b2b24@quicinc.com> To: Manivannan Sadhasivam , =?utf-8?q?Krzy?= =?utf-8?q?sztof_Wilczy=C5=84ski?= , Kishon Vijay Abraham I , Bjorn Helgaas , Jonathan Corbet , Lorenzo Pieralisi , Rob Herring CC: , , , , , , , , , , "Krishna chaitanya chundru" , Manivannan Sadhasivam X-Mailer: b4 0.13-dev-83828 X-Developer-Signature: v=1; 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Read perst value to determine if the link is in D3Cold/D3hot. Reviewed-by: Manivannan Sadhasivam Signed-off-by: Krishna chaitanya chundru --- drivers/pci/controller/dwc/pcie-qcom-ep.c | 8 +++++++- 1 file changed, 7 insertions(+), 1 deletion(-) diff --git a/drivers/pci/controller/dwc/pcie-qcom-ep.c b/drivers/pci/controller/dwc/pcie-qcom-ep.c index 236229f66c80..817fad805c51 100644 --- a/drivers/pci/controller/dwc/pcie-qcom-ep.c +++ b/drivers/pci/controller/dwc/pcie-qcom-ep.c @@ -648,6 +648,7 @@ static irqreturn_t qcom_pcie_ep_global_irq_thread(int irq, void *data) struct device *dev = pci->dev; u32 status = readl_relaxed(pcie_ep->parf + PARF_INT_ALL_STATUS); u32 mask = readl_relaxed(pcie_ep->parf + PARF_INT_ALL_MASK); + pci_power_t state; u32 dstate, val; writel_relaxed(status, pcie_ep->parf + PARF_INT_ALL_CLEAR); @@ -671,11 +672,16 @@ static irqreturn_t qcom_pcie_ep_global_irq_thread(int irq, void *data) dstate = dw_pcie_readl_dbi(pci, DBI_CON_STATUS) & DBI_CON_STATUS_POWER_STATE_MASK; dev_dbg(dev, "Received D%d state event\n", dstate); - if (dstate == 3) { + state = dstate; + if (dstate == PCI_D3hot) { val = readl_relaxed(pcie_ep->parf + PARF_PM_CTRL); val |= PARF_PM_CTRL_REQ_EXIT_L1; writel_relaxed(val, pcie_ep->parf + PARF_PM_CTRL); + + if (gpiod_get_value(pcie_ep->reset)) + state = PCI_D3cold; } + pci_epc_dstate_notify(pci->ep.epc, state); } else if (FIELD_GET(PARF_INT_ALL_LINK_UP, status)) { dev_dbg(dev, "Received Linkup event. Enumeration complete!\n"); dw_pcie_ep_linkup(&pci->ep);