From patchwork Fri Aug 9 01:43:22 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Konrad Dybcio X-Patchwork-Id: 818136 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 61C1517BC9; Fri, 9 Aug 2024 01:43:37 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1723167818; cv=none; b=dF5xb7+JoSdwZglzPrf0QMnqUsmjq76hQL38JLyisP7WZ46TTMyNEURdiCKJpOh8wH4xk92UekyEWHM92PlABOqBUEyIHVUdc0l4bSv6IEjhXWkhbt9nlM9zjUoy/4LkyeTFZnvwWxxEwgMDcjDB8RHWOEm4WVxXCi4GqIVNsrc= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1723167818; c=relaxed/simple; bh=bT/fwgV49uTeD5E5U5PyN6g2VlugFUBLQSy7HvJnDik=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=MEzfQuX71WJv7Cf4B7OTimH56Dsp5B31+sgk0fSjqA/D5IUMbppGjlKRLi9dsEt2FWIjbQHGOjE0GlckQLPrMRDo6jmVvfUC0uid8OL6QUcdnAF/tnAtpVLt0+WRVIv5H6Dt1zkStpH3i7nBA0Lbyaa7wl5fyg9eGRjauxvyF9Y= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=WILfVNw9; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="WILfVNw9" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 3ACD7C32786; Fri, 9 Aug 2024 01:43:33 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1723167817; bh=bT/fwgV49uTeD5E5U5PyN6g2VlugFUBLQSy7HvJnDik=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=WILfVNw9EhQnossFGwH9JeRyssh8wopN+0+ksXgHnQ/Sz176PxeKtCTu2xbEQdm1L uJhv1RzbZDgjKZ3aVa/eryDKHuy+TmZFrM03ZT0OYW+dJ2huCy4J0pZhrjn0d0EUX1 CIv9SF15Kas4ZG9H/qmDmVSz5Oxq4O4FIS4EKvSQeO4dfZMGcSE85ducFqcW2YqG/T gajJV8fniSj/Va7ufTIf//tZ2u1SFbWE0Co4HQPvNxvg6EF3OSXxz59wu6tGr4KkEH 6rbmIUmcOV9JjKq+JxTXt5pPSCZzMEw3CCwx5TqPGkXQaAG6tFTkogE3IihAHVoPXS aPLccS7U7nCtw== From: Konrad Dybcio Date: Fri, 09 Aug 2024 03:43:22 +0200 Subject: [PATCH 3/4] arm64: dts: qcom: x1e80100: Add UART2 Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20240809-topic-sl7-v1-3-2090433d8dfc@quicinc.com> References: <20240809-topic-sl7-v1-0-2090433d8dfc@quicinc.com> In-Reply-To: <20240809-topic-sl7-v1-0-2090433d8dfc@quicinc.com> To: Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: Marijn Suijten , linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Konrad Dybcio X-Mailer: b4 0.14.1 X-Developer-Signature: v=1; a=ed25519-sha256; t=1723167803; l=2149; i=quic_kdybcio@quicinc.com; s=20230215; h=from:subject:message-id; bh=TtHdNs+6i3n8jsKuyaD5jBPXgL3GwwIPNx7CnO3pjEY=; b=8ngqqAzlfGyYJN5lFg9gsHawPgyTJQC8I2/Z/iVx9Gq3yLq6nupFJzdtSx0fS+JNqEJT2bjW6 tvQvoUYWWKFDidXjx+JHZ+H4c++Qnh/LkxyG6vaXTNkYDy6zr9wxEC6 X-Developer-Key: i=quic_kdybcio@quicinc.com; a=ed25519; pk=iclgkYvtl2w05SSXO5EjjSYlhFKsJ+5OSZBjOkQuEms= From: Konrad Dybcio GENI SE2 within QUP0 is used as UART on some devices, describe it. Signed-off-by: Konrad Dybcio --- arch/arm64/boot/dts/qcom/x1e80100.dtsi | 52 ++++++++++++++++++++++++++++++++++ 1 file changed, 52 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/x1e80100.dtsi b/arch/arm64/boot/dts/qcom/x1e80100.dtsi index 326283822aee..a2a011702752 100644 --- a/arch/arm64/boot/dts/qcom/x1e80100.dtsi +++ b/arch/arm64/boot/dts/qcom/x1e80100.dtsi @@ -2142,6 +2142,28 @@ &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>, status = "disabled"; }; + uart2: serial@b88000 { + compatible = "qcom,geni-uart"; + reg = <0 0x00b88000 0 0x4000>; + + interrupts = ; + + clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; + clock-names = "se"; + + interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "qup-core", + "qup-config"; + + pinctrl-0 = <&qup_uart2_default>; + pinctrl-names = "default"; + + status = "disabled"; + }; + spi2: spi@b88000 { compatible = "qcom,geni-spi"; reg = <0 0x00b88000 0 0x4000>; @@ -5365,6 +5387,36 @@ qup_spi23_data_clk: qup-spi23-data-clk-state { bias-disable; }; + qup_uart2_default: qup-uart2-default-state { + cts-pins { + pins = "gpio8"; + function = "qup0_se2"; + drive-strength = <2>; + bias-disable; + }; + + rts-pins { + pins = "gpio9"; + function = "qup0_se2"; + drive-strength = <2>; + bias-disable; + }; + + tx-pins { + pins = "gpio10"; + function = "qup0_se2"; + drive-strength = <2>; + bias-disable; + }; + + rx-pins { + pins = "gpio11"; + function = "qup0_se2"; + drive-strength = <2>; + bias-disable; + }; + }; + qup_uart21_default: qup-uart21-default-state { /* TX, RX */ pins = "gpio86", "gpio87";