From patchwork Wed Oct 9 09:15:35 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Qiang Yu X-Patchwork-Id: 834055 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 60DD817BB35; Wed, 9 Oct 2024 09:15:55 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.168.131 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1728465356; cv=none; b=im0Q7Yyr09NLipI6UC5SJg8Z03vHhOSeSjJmIjrxKVwS8Tug7sg7nPNKQd2ZtmlDTD7RdeUBubE4VaUpajYSuOno5YTJAyAogJL3ObMoM5z06sdp/pgi75kw3BGmFkWz3PoUSCo31bi+dVGGWL+DFZwO5Z49DHZiDWVWIe2+hfs= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1728465356; c=relaxed/simple; bh=XVqBF3uU6H3gRvE1VXGdpEedqjqbhY5OV4rF9o9T3RA=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=svmJHp9HFW6oNGMQKkamUMrDj+ievGxQyLaWtAJwzp5+pWXsYfTaT1lLGfguBQwery7vDQ+vgC818xzzaF5/NyJltyxDiOZm523K5AQfH4LSoz8HHEfohRUNn0gEu46r+rZQ4NsIxKdwNvwvdRccrIycwJlkImvBNoF957DJY7A= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=quicinc.com; spf=pass smtp.mailfrom=qualcomm.com; dkim=pass (2048-bit key) header.d=quicinc.com header.i=@quicinc.com header.b=Uz8Gni29; arc=none smtp.client-ip=205.220.168.131 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=quicinc.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=qualcomm.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=quicinc.com header.i=@quicinc.com header.b="Uz8Gni29" Received: from pps.filterd (m0279865.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.2/8.18.1.2) with ESMTP id 4998FNL9001750; Wed, 9 Oct 2024 09:15:46 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; h= cc:content-transfer-encoding:date:from:in-reply-to:message-id :mime-version:references:subject:to; s=qcppdkim1; bh=AdcktK5D9O1 N/CDpsnC+gVeX8zMqbfI9hnTcbdr6Dss=; b=Uz8Gni29Nm3wV/wyQeauOVV7TFW yJsK+SN8jZy8ipaFW78Q+NomxKv+WivOAHeeq/7bbWZgcIJIx0Gv4+JM0496AK+T Jn6Z37Xlee9+EeyO3TsWnR99wIpTqncOi9oUjF0wr8u2ZQSkLFecJ3lOtvizH9b8 H4SfCHY30UOKYdhYOxjH/sRAFzjlQiEc2wZ1o5GAjg82P24tlrBIyRh3kxf5MNsw T/qvOejlf+iW0G+WbON6Qja8em2KVaWf1MIQwTZQWoUzvCCf6E8HLTrNoHGrW5hv NKleL+vXZA+gltPwSI+3c42/ZAMm68/oFBNTbKywzQqPnoDM+AVc9IEZeOQ== Received: from nalasppmta03.qualcomm.com (Global_NAT1.qualcomm.com [129.46.96.20]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 42513u3nwm-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Wed, 09 Oct 2024 09:15:45 +0000 (GMT) Received: from pps.filterd (NALASPPMTA03.qualcomm.com [127.0.0.1]) by NALASPPMTA03.qualcomm.com (8.18.1.2/8.18.1.2) with ESMTP id 4999Bsaw024666; Wed, 9 Oct 2024 09:15:45 GMT Received: from pps.reinject (localhost [127.0.0.1]) by NALASPPMTA03.qualcomm.com (PPS) with ESMTPS id 425fv1uthj-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Wed, 09 Oct 2024 09:15:45 +0000 Received: from NALASPPMTA03.qualcomm.com (NALASPPMTA03.qualcomm.com [127.0.0.1]) by pps.reinject (8.17.1.5/8.17.1.5) with ESMTP id 49999E9b016589; Wed, 9 Oct 2024 09:15:45 GMT Received: from hu-devc-lv-u22-c.qualcomm.com (hu-qianyu-lv.qualcomm.com [10.81.25.114]) by NALASPPMTA03.qualcomm.com (PPS) with ESMTPS id 4999FikA002510 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Wed, 09 Oct 2024 09:15:45 +0000 Received: by hu-devc-lv-u22-c.qualcomm.com (Postfix, from userid 4098150) id B03B3656; Wed, 9 Oct 2024 02:15:44 -0700 (PDT) From: Qiang Yu To: manivannan.sadhasivam@linaro.org, vkoul@kernel.org, kishon@kernel.org, robh@kernel.org, andersson@kernel.org, konradybcio@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, mturquette@baylibre.com, sboyd@kernel.org, abel.vesa@linaro.org, quic_msarkar@quicinc.com, quic_devipriy@quicinc.com Cc: dmitry.baryshkov@linaro.org, kw@linux.com, lpieralisi@kernel.org, neil.armstrong@linaro.org, linux-arm-msm@vger.kernel.org, linux-phy@lists.infradead.org, linux-kernel@vger.kernel.org, linux-pci@vger.kernel.org, devicetree@vger.kernel.org, linux-clk@vger.kernel.org, Qiang Yu , Krzysztof Kozlowski Subject: [PATCH v5 2/7] dt-bindings: PCI: qcom: Move OPP table to qcom,pcie-common.yaml Date: Wed, 9 Oct 2024 02:15:35 -0700 Message-Id: <20241009091540.1446-3-quic_qianyu@quicinc.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241009091540.1446-1-quic_qianyu@quicinc.com> References: <20241009091540.1446-1-quic_qianyu@quicinc.com> Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-QCInternal: smtphost X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-ORIG-GUID: CdHOyEjbYpjGLZqyO6O_QqTRb6lv3jf3 X-Proofpoint-GUID: CdHOyEjbYpjGLZqyO6O_QqTRb6lv3jf3 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.60.29 definitions=2024-09-06_09,2024-09-06_01,2024-09-02_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 adultscore=0 lowpriorityscore=0 mlxlogscore=999 malwarescore=0 spamscore=0 priorityscore=1501 impostorscore=0 phishscore=0 suspectscore=0 bulkscore=0 mlxscore=0 clxscore=1015 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2409260000 definitions=main-2410090060 OPP table is a generic property that is also required by other qcom platforms. Hence move this property to qcom,pcie-common.yaml so that PCIe on other qcom platforms is able to adjust power domain performance state and ICC peak bw according to PCIe gen speed and link width. Signed-off-by: Qiang Yu Reviewed-by: Manivannan Sadhasivam Reviewed-by: Krzysztof Kozlowski --- Documentation/devicetree/bindings/pci/qcom,pcie-common.yaml | 4 ++++ Documentation/devicetree/bindings/pci/qcom,pcie-sm8450.yaml | 4 ---- 2 files changed, 4 insertions(+), 4 deletions(-) diff --git a/Documentation/devicetree/bindings/pci/qcom,pcie-common.yaml b/Documentation/devicetree/bindings/pci/qcom,pcie-common.yaml index 704c0f58eea5..3c6430fe9331 100644 --- a/Documentation/devicetree/bindings/pci/qcom,pcie-common.yaml +++ b/Documentation/devicetree/bindings/pci/qcom,pcie-common.yaml @@ -78,6 +78,10 @@ properties: description: GPIO controlled connection to WAKE# signal maxItems: 1 + operating-points-v2: true + opp-table: + type: object + required: - reg - reg-names diff --git a/Documentation/devicetree/bindings/pci/qcom,pcie-sm8450.yaml b/Documentation/devicetree/bindings/pci/qcom,pcie-sm8450.yaml index 46bd59eefadb..6e0a6d8f0ed0 100644 --- a/Documentation/devicetree/bindings/pci/qcom,pcie-sm8450.yaml +++ b/Documentation/devicetree/bindings/pci/qcom,pcie-sm8450.yaml @@ -70,10 +70,6 @@ properties: - const: msi7 - const: global - operating-points-v2: true - opp-table: - type: object - resets: maxItems: 1