@@ -133,6 +133,14 @@ static int gdsc_update_collapse_bit(struct gdsc *sc, bool val)
if (ret)
return ret;
+ if (sc->collapse_sleep_ctrl) {
+ ret = regmap_update_bits(sc->regmap, sc->collapse_sleep_ctrl, mask, val ? mask : 0);
+ if (ret) {
+ regmap_update_bits(sc->regmap, reg, mask, val ? 0 : mask);
+ return ret;
+ }
+ }
+
return 0;
}
@@ -19,6 +19,7 @@ struct reset_controller_dev;
* @regmap: regmap for MMIO accesses
* @gdscr: gsdc control register
* @collapse_ctrl: APCS collapse-vote register
+ * @collapse_sleep_ctrl: APCS collapse-vote register for the sleep state
* @collapse_mask: APCS collapse-vote mask
* @gds_hw_ctrl: gds_hw_ctrl register
* @cxcs: offsets of branch registers to toggle mem/periph bits in
@@ -37,6 +38,7 @@ struct gdsc {
struct regmap *regmap;
unsigned int gdscr;
unsigned int collapse_ctrl;
+ unsigned int collapse_sleep_ctrl;
unsigned int collapse_mask;
unsigned int gds_hw_ctrl;
unsigned int clamp_io_ctrl;
Some platforms use separate collapse vote registers for the active and sleep states. Extend gdsc_update_collapse_bit() to support separate collapse_sleep_ctrl register. Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> --- drivers/clk/qcom/gdsc.c | 8 ++++++++ drivers/clk/qcom/gdsc.h | 2 ++ 2 files changed, 10 insertions(+)