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Tue, 15 Apr 2025 07:28:53 GMT Received: from hu-kaushalk-hyd.qualcomm.com (10.80.80.8) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Tue, 15 Apr 2025 00:28:48 -0700 From: Kaushal Kumar To: , , , , , , , , , , CC: , , , , , Kaushal Kumar Subject: [PATCH v2 4/5] arm64: dts: qcom: sdx75: Add QPIC NAND support Date: Tue, 15 Apr 2025 12:57:55 +0530 Message-ID: <20250415072756.20046-5-quic_kaushalk@quicinc.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20250415072756.20046-1-quic_kaushalk@quicinc.com> References: <20250415072756.20046-1-quic_kaushalk@quicinc.com> Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nalasex01a.na.qualcomm.com (10.47.209.196) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Authority-Analysis: v=2.4 cv=E9TNpbdl c=1 sm=1 tr=0 ts=67fe0ab6 cx=c_pps a=ouPCqIW2jiPt+lZRy3xVPw==:117 a=ouPCqIW2jiPt+lZRy3xVPw==:17 a=GEpy-HfZoHoA:10 a=XR8D0OoHHMoA:10 a=COk6AnOGAAAA:8 a=EhM7gG_zESjhUU7MHiYA:9 a=TjNXssC_j7lpFel5tvFf:22 X-Proofpoint-ORIG-GUID: 4GLSRAsC5K8RzxVDTjg71ghNPYQVx-z0 X-Proofpoint-GUID: 4GLSRAsC5K8RzxVDTjg71ghNPYQVx-z0 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1095,Hydra:6.0.680,FMLib:17.12.68.34 definitions=2025-04-15_03,2025-04-10_01,2024-11-22_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 malwarescore=0 adultscore=0 mlxscore=0 bulkscore=0 clxscore=1015 phishscore=0 lowpriorityscore=0 suspectscore=0 mlxlogscore=892 spamscore=0 priorityscore=1501 impostorscore=0 classifier=spam authscore=0 authtc=n/a authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2502280000 definitions=main-2504150050 Add devicetree node to enable support for QPIC NAND controller on Qualcomm SDX75 platform. Signed-off-by: Kaushal Kumar --- arch/arm64/boot/dts/qcom/sdx75.dtsi | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sdx75.dtsi b/arch/arm64/boot/dts/qcom/sdx75.dtsi index e3a0ee661c4a..61ec8e7a0e21 100644 --- a/arch/arm64/boot/dts/qcom/sdx75.dtsi +++ b/arch/arm64/boot/dts/qcom/sdx75.dtsi @@ -894,6 +894,25 @@ status = "disabled"; }; + qpic_nand: nand-controller@1cc8000 { + compatible = "qcom,sdx75-nand", "qcom,sdx55-nand"; + reg = <0x0 0x01cc8000 0x0 0x10000>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&rpmhcc RPMH_QPIC_CLK>, + <&sleep_clk>; + clock-names = "core", + "aon"; + dmas = <&qpic_bam 0>, + <&qpic_bam 1>, + <&qpic_bam 2>; + dma-names = "tx", + "rx", + "cmd"; + iommus = <&apps_smmu 0x100 0x3>; + status = "disabled"; + }; + tcsr_mutex: hwlock@1f40000 { compatible = "qcom,tcsr-mutex"; reg = <0x0 0x01f40000 0x0 0x40000>;