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Tue, 15 Apr 2025 09:54:52 GMT Received: from 087e9057f447.qualcomm.com (10.80.80.8) by nasanex01b.na.qualcomm.com (10.46.141.250) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Tue, 15 Apr 2025 02:54:47 -0700 From: Raviteja Laggyshetty To: Georgi Djakov , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Bjorn Andersson , Konrad Dybcio CC: Odelu Kukatla , Jeff Johnson , Dmitry Baryshkov , Mike Tipton , , , , , Jagadeesh Kona , Shivnandan Kumar , Raviteja Laggyshetty Subject: [PATCH V11 7/7] arm64: dts: qcom: sa8775p: Add CPU OPP tables to scale DDR/L3 Date: Tue, 15 Apr 2025 09:53:43 +0000 Message-ID: <20250415095343.32125-8-quic_rlaggysh@quicinc.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250415095343.32125-1-quic_rlaggysh@quicinc.com> References: <20250415095343.32125-1-quic_rlaggysh@quicinc.com> Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nasanex01b.na.qualcomm.com (10.46.141.250) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: Ped9WythIuF88UFv9hjJgUP4V1P65BRN X-Authority-Analysis: v=2.4 cv=JNc7s9Kb c=1 sm=1 tr=0 ts=67fe2ced cx=c_pps a=JYp8KDb2vCoCEuGobkYCKw==:117 a=JYp8KDb2vCoCEuGobkYCKw==:17 a=GEpy-HfZoHoA:10 a=XR8D0OoHHMoA:10 a=COk6AnOGAAAA:8 a=EUspDBNiAAAA:8 a=UERuPk7d7HPuaWx_DlYA:9 a=TjNXssC_j7lpFel5tvFf:22 X-Proofpoint-ORIG-GUID: Ped9WythIuF88UFv9hjJgUP4V1P65BRN X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1095,Hydra:6.0.680,FMLib:17.12.68.34 definitions=2025-04-15_04,2025-04-10_01,2024-11-22_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 mlxscore=0 malwarescore=0 suspectscore=0 mlxlogscore=999 lowpriorityscore=0 bulkscore=0 impostorscore=0 clxscore=1015 phishscore=0 adultscore=0 priorityscore=1501 spamscore=0 classifier=spam authscore=0 authtc=n/a authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2502280000 definitions=main-2504150069 From: Jagadeesh Kona Add OPP tables required to scale DDR and L3 per freq-domain on SA8775P platform. If a single OPP table is used for both CPU domains, then _allocate_opp_table() won't be invoked for CPU4 but instead CPU4 will be added as device under the CPU0 OPP table. Due to this, dev_pm_opp_of_find_icc_paths() won't be invoked for CPU4 device and hence CPU4 won't be able to independently scale it's interconnects. Both CPU0 and CPU4 devices will scale the same ICC path which can lead to one device overwriting the BW vote placed by other device. Hence CPU0 and CPU4 require separate OPP tables to allow independent scaling of DDR and L3 frequencies for each CPU domain, with the final DDR and L3 frequencies being an aggregate of both. Co-developed-by: Shivnandan Kumar Signed-off-by: Shivnandan Kumar Signed-off-by: Raviteja Laggyshetty Signed-off-by: Jagadeesh Kona Reviewed-by: Dmitry Baryshkov --- arch/arm64/boot/dts/qcom/sa8775p.dtsi | 210 ++++++++++++++++++++++++++ 1 file changed, 210 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sa8775p.dtsi b/arch/arm64/boot/dts/qcom/sa8775p.dtsi index fac5dfb147fd..800db236a1e0 100644 --- a/arch/arm64/boot/dts/qcom/sa8775p.dtsi +++ b/arch/arm64/boot/dts/qcom/sa8775p.dtsi @@ -52,6 +52,11 @@ cpu0: cpu@0 { next-level-cache = <&l2_0>; capacity-dmips-mhz = <1024>; dynamic-power-coefficient = <100>; + operating-points-v2 = <&cpu0_opp_table>; + interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>, + <&epss_l3_cl0 MASTER_EPSS_L3_APPS + &epss_l3_cl0 SLAVE_EPSS_L3_SHARED>; l2_0: l2-cache { compatible = "cache"; cache-level = <2>; @@ -76,6 +81,11 @@ cpu1: cpu@100 { next-level-cache = <&l2_1>; capacity-dmips-mhz = <1024>; dynamic-power-coefficient = <100>; + operating-points-v2 = <&cpu0_opp_table>; + interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>, + <&epss_l3_cl0 MASTER_EPSS_L3_APPS + &epss_l3_cl0 SLAVE_EPSS_L3_SHARED>; l2_1: l2-cache { compatible = "cache"; cache-level = <2>; @@ -95,6 +105,11 @@ cpu2: cpu@200 { next-level-cache = <&l2_2>; capacity-dmips-mhz = <1024>; dynamic-power-coefficient = <100>; + operating-points-v2 = <&cpu0_opp_table>; + interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>, + <&epss_l3_cl0 MASTER_EPSS_L3_APPS + &epss_l3_cl0 SLAVE_EPSS_L3_SHARED>; l2_2: l2-cache { compatible = "cache"; cache-level = <2>; @@ -114,6 +129,11 @@ cpu3: cpu@300 { next-level-cache = <&l2_3>; capacity-dmips-mhz = <1024>; dynamic-power-coefficient = <100>; + operating-points-v2 = <&cpu0_opp_table>; + interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>, + <&epss_l3_cl0 MASTER_EPSS_L3_APPS + &epss_l3_cl0 SLAVE_EPSS_L3_SHARED>; l2_3: l2-cache { compatible = "cache"; cache-level = <2>; @@ -133,6 +153,11 @@ cpu4: cpu@10000 { next-level-cache = <&l2_4>; capacity-dmips-mhz = <1024>; dynamic-power-coefficient = <100>; + operating-points-v2 = <&cpu4_opp_table>; + interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>, + <&epss_l3_cl1 MASTER_EPSS_L3_APPS + &epss_l3_cl1 SLAVE_EPSS_L3_SHARED>; l2_4: l2-cache { compatible = "cache"; cache-level = <2>; @@ -158,6 +183,11 @@ cpu5: cpu@10100 { next-level-cache = <&l2_5>; capacity-dmips-mhz = <1024>; dynamic-power-coefficient = <100>; + operating-points-v2 = <&cpu4_opp_table>; + interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>, + <&epss_l3_cl1 MASTER_EPSS_L3_APPS + &epss_l3_cl1 SLAVE_EPSS_L3_SHARED>; l2_5: l2-cache { compatible = "cache"; cache-level = <2>; @@ -177,6 +207,11 @@ cpu6: cpu@10200 { next-level-cache = <&l2_6>; capacity-dmips-mhz = <1024>; dynamic-power-coefficient = <100>; + operating-points-v2 = <&cpu4_opp_table>; + interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>, + <&epss_l3_cl1 MASTER_EPSS_L3_APPS + &epss_l3_cl1 SLAVE_EPSS_L3_SHARED>; l2_6: l2-cache { compatible = "cache"; cache-level = <2>; @@ -196,6 +231,11 @@ cpu7: cpu@10300 { next-level-cache = <&l2_7>; capacity-dmips-mhz = <1024>; dynamic-power-coefficient = <100>; + operating-points-v2 = <&cpu4_opp_table>; + interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>, + <&epss_l3_cl1 MASTER_EPSS_L3_APPS + &epss_l3_cl1 SLAVE_EPSS_L3_SHARED>; l2_7: l2-cache { compatible = "cache"; cache-level = <2>; @@ -285,6 +325,176 @@ cluster_sleep_apss_rsc_pc: cluster-sleep-1 { }; }; + cpu0_opp_table: opp-table-cpu0 { + compatible = "operating-points-v2"; + opp-shared; + + opp-1267200000 { + opp-hz = /bits/ 64 <1267200000>; + opp-peak-kBps = <(1555200 * 4) (921600 * 32)>; + }; + + opp-1363200000 { + opp-hz = /bits/ 64 <1363200000>; + opp-peak-kBps = <(1555200 * 4) (921600 * 32)>; + }; + + opp-1459200000 { + opp-hz = /bits/ 64 <1459200000>; + opp-peak-kBps = <(1555200 * 4) (921600 * 32)>; + }; + + opp-1536000000 { + opp-hz = /bits/ 64 <1536000000>; + opp-peak-kBps = <(1555200 * 4) (921600 * 32)>; + }; + + opp-1632000000 { + opp-hz = /bits/ 64 <1632000000>; + opp-peak-kBps = <(1708800 * 4) (1228800 * 32)>; + }; + + opp-1708800000 { + opp-hz = /bits/ 64 <1708800000>; + opp-peak-kBps = <(1708800 * 4) (1228800 * 32)>; + }; + + opp-1785600000 { + opp-hz = /bits/ 64 <1785600000>; + opp-peak-kBps = <(1708800 * 4) (1228800 * 32)>; + }; + + opp-1862400000 { + opp-hz = /bits/ 64 <1862400000>; + opp-peak-kBps = <(1708800 * 4) (1228800 * 32)>; + }; + + opp-1939200000 { + opp-hz = /bits/ 64 <1939200000>; + opp-peak-kBps = <(1708800 * 4) (1228800 * 32)>; + }; + + opp-2016000000 { + opp-hz = /bits/ 64 <2016000000>; + opp-peak-kBps = <(1708800 * 4) (1228800 * 32)>; + }; + + opp-2112000000 { + opp-hz = /bits/ 64 <2112000000>; + opp-peak-kBps = <(2092800 * 4) (1555200 * 32)>; + }; + + opp-2188800000 { + opp-hz = /bits/ 64 <2188800000>; + opp-peak-kBps = <(2092800 * 4) (1555200 * 32)>; + }; + + opp-2265600000 { + opp-hz = /bits/ 64 <2265600000>; + opp-peak-kBps = <(2092800 * 4) (1555200 * 32)>; + }; + + opp-2361600000 { + opp-hz = /bits/ 64 <2361600000>; + opp-peak-kBps = <(3196800 * 4) (1612800 * 32)>; + }; + + opp-2457600000 { + opp-hz = /bits/ 64 <2457600000>; + opp-peak-kBps = <(3196800 * 4) (1612800 * 32)>; + }; + + opp-2553600000 { + opp-hz = /bits/ 64 <2553600000>; + opp-peak-kBps = <(3196800 * 4) (1708800 * 32)>; + }; + }; + + cpu4_opp_table: opp-table-cpu4 { + compatible = "operating-points-v2"; + opp-shared; + + opp-1267200000 { + opp-hz = /bits/ 64 <1267200000>; + opp-peak-kBps = <(1555200 * 4) (921600 * 32)>; + }; + + opp-1363200000 { + opp-hz = /bits/ 64 <1363200000>; + opp-peak-kBps = <(1555200 * 4) (921600 * 32)>; + }; + + opp-1459200000 { + opp-hz = /bits/ 64 <1459200000>; + opp-peak-kBps = <(1555200 * 4) (921600 * 32)>; + }; + + opp-1536000000 { + opp-hz = /bits/ 64 <1536000000>; + opp-peak-kBps = <(1555200 * 4) (921600 * 32)>; + }; + + opp-1632000000 { + opp-hz = /bits/ 64 <1632000000>; + opp-peak-kBps = <(1708800 * 4) (1228800 * 32)>; + }; + + opp-1708800000 { + opp-hz = /bits/ 64 <1708800000>; + opp-peak-kBps = <(1708800 * 4) (1228800 * 32)>; + }; + + opp-1785600000 { + opp-hz = /bits/ 64 <1785600000>; + opp-peak-kBps = <(1708800 * 4) (1228800 * 32)>; + }; + + opp-1862400000 { + opp-hz = /bits/ 64 <1862400000>; + opp-peak-kBps = <(1708800 * 4) (1228800 * 32)>; + }; + + opp-1939200000 { + opp-hz = /bits/ 64 <1939200000>; + opp-peak-kBps = <(1708800 * 4) (1228800 * 32)>; + }; + + opp-2016000000 { + opp-hz = /bits/ 64 <2016000000>; + opp-peak-kBps = <(1708800 * 4) (1228800 * 32)>; + }; + + opp-2112000000 { + opp-hz = /bits/ 64 <2112000000>; + opp-peak-kBps = <(2092800 * 4) (1555200 * 32)>; + }; + + opp-2188800000 { + opp-hz = /bits/ 64 <2188800000>; + opp-peak-kBps = <(2092800 * 4) (1555200 * 32)>; + }; + + opp-2265600000 { + opp-hz = /bits/ 64 <2265600000>; + opp-peak-kBps = <(2092800 * 4) (1555200 * 32)>; + }; + + opp-2361600000 { + opp-hz = /bits/ 64 <2361600000>; + opp-peak-kBps = <(3196800 * 4) (1612800 * 32)>; + }; + + opp-2457600000 { + opp-hz = /bits/ 64 <2457600000>; + opp-peak-kBps = <(3196800 * 4) (1612800 * 32)>; + }; + + opp-2553600000 { + opp-hz = /bits/ 64 <2553600000>; + opp-peak-kBps = <(3196800 * 4) (1708800 * 32)>; + }; + }; + dummy-sink { compatible = "arm,coresight-dummy-sink";