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[209.132.180.67]) by mx.google.com with ESMTP id h189si17321100pge.152.2019.02.28.04.28.13; Thu, 28 Feb 2019 04:28:13 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-arm-msm-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=liqYSAAa; spf=pass (google.com: best guess record for domain of linux-arm-msm-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-arm-msm-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1731963AbfB1M2N (ORCPT + 15 others); Thu, 28 Feb 2019 07:28:13 -0500 Received: from mail-wm1-f65.google.com ([209.85.128.65]:53386 "EHLO mail-wm1-f65.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1731334AbfB1M2L (ORCPT ); Thu, 28 Feb 2019 07:28:11 -0500 Received: by mail-wm1-f65.google.com with SMTP id e74so8980156wmg.3 for ; Thu, 28 Feb 2019 04:28:10 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :in-reply-to:references; bh=aLsMVwtpgSOaGBz4AILnRl4PUyhZEZVIsjfHxCwTaGk=; b=liqYSAAaRLAxjf7E18Jg20APdR6ztu6B4pKk1U3HBLgv6nlh82wSfLAPzNfPn/zgSi aTPD4d2HPqVKHIp6PhSxktLepegSGSCiD8kgxm1kH8Xj8wxaJS9Y43ilCOYL1n2CSqjA G/uRdoLH2fRFpLmOC7YDy/JE0RhpyZGEfAs5NrJREEAe8LiOzfoQOG4hlktWsfnd8B0T PGiU5zU/0hpe2RNmDadTp4XyhJVisjZ6RghX9Nu3hJyU6PnZ2uAwMoZbWy0PnnEIiHgZ lc8ov+A5efgF9rCl9e6fZ801rasqNGRSa9mIvrHbSdOCacsPxPYAQ714sMebcCExcM2L uwYw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:in-reply-to:references; bh=aLsMVwtpgSOaGBz4AILnRl4PUyhZEZVIsjfHxCwTaGk=; b=g96mddx75CtL+ZPBAsc1UbrlMwCDjJ8sgkk7qh/QbiOaj37BhPWGfs1alHEReWab3P 2DfjqYMFy4QTMFw2rjidj+AeIu8CAlnjp97fzCRbxZ5BxBnMJcxrsSZ8xo0Uv3eJE2yP kTfLK4hdMRHPEXmznR2TtrN5oSbhnrEVVwYvTXetuQ+ZUku+ceIhDQosOPY3fKxAyiNm 0oGqZrrWLzBJnxOLm61cLX5vF2rM3tZumSRGO5OuPjgwhQIMq6ceVxCZPHrazrr2ryza ar8Uwt5sIizlUSMw0qp/dmOXxa1Rk8U779bi8VVv10wGk1BVPP95Xo9o5f6znZqyB3bH KLsw== X-Gm-Message-State: AHQUAuYEVKRgWE5nEH1SuV3xoEAo2VsL09YijvZ5hspz26CdfiF+RHaz G8zMpKrxFcYGpRg+RZ0MxPTsyQ== X-Received: by 2002:a1c:2947:: with SMTP id p68mr2789122wmp.104.1551356889992; Thu, 28 Feb 2019 04:28:09 -0800 (PST) Received: from localhost ([49.248.54.130]) by smtp.gmail.com with ESMTPSA id h62sm4760705wmf.11.2019.02.28.04.28.08 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Thu, 28 Feb 2019 04:28:09 -0800 (PST) From: Amit Kucheria To: linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, bjorn.andersson@linaro.org, edubezval@gmail.com, andy.gross@linaro.org, Daniel Lezcano , David Brown , Zhang Rui Cc: devicetree@vger.kernel.org Subject: [PATCH v2 22/24] arm64: dts: qcom: qcs404: Add tsens controller Date: Thu, 28 Feb 2019 17:51:12 +0530 Message-Id: <59921d5433cb82e79e5ef9d70218beb5230f80ea.1551355503.git.amit.kucheria@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: References: In-Reply-To: References: Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org qcs404 has a single TSENS IP block with 10 sensors. The calibration data is stored in an eeprom (qfprom) that is accessed through the nvmem framework. We add the qfprom node to allow the tsens sensors to be calibrated correctly. Signed-off-by: Amit Kucheria --- arch/arm64/boot/dts/qcom/qcs404.dtsi | 20 ++++++++++++++++++++ 1 file changed, 20 insertions(+) -- 2.17.1 diff --git a/arch/arm64/boot/dts/qcom/qcs404.dtsi b/arch/arm64/boot/dts/qcom/qcs404.dtsi index 9b5c16562bbe..57d14d8f0c90 100644 --- a/arch/arm64/boot/dts/qcom/qcs404.dtsi +++ b/arch/arm64/boot/dts/qcom/qcs404.dtsi @@ -253,6 +253,16 @@ reg = <0x00060000 0x6000>; }; + qfprom: qfprom@a4000 { + compatible = "qcom,qfprom"; + reg = <0x000a4000 0x1000>; + #address-cells = <1>; + #size-cells = <1>; + tsens_caldata: caldata@d0 { + reg = <0x1f8 0x14>; + }; + }; + rng: rng@e3000 { compatible = "qcom,prng-ee"; reg = <0x000e3000 0x1000>; @@ -260,6 +270,16 @@ clock-names = "core"; }; + tsens: thermal-sensor@4a9000 { + compatible = "qcom,qcs404-tsens", "qcom,tsens-v1"; + reg = <0x004a9000 0x1000>, /* TM */ + <0x004a8000 0x1000>; /* SROT */ + nvmem-cells = <&tsens_caldata>; + nvmem-cell-names = "calib"; + #qcom,sensors = <10>; + #thermal-sensor-cells = <1>; + }; + tlmm: pinctrl@1000000 { compatible = "qcom,qcs404-pinctrl"; reg = <0x01000000 0x200000>,