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Fri, 1 Sep 2023 14:11:08 +0000 From: Ziyang Huang To: agross@kernel.org Cc: andersson@kernel.org, konrad.dybcio@linaro.org, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, conor+dt@kernel.org, quic_gokulsri@quicinc.com, quic_srichara@quicinc.com, quic_varada@quicinc.com, linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Ziyang Huang Subject: [PATCH v3] arm64: dts: ipq5018: Correct uart1_pins pinconf Date: Fri, 1 Sep 2023 22:10:42 +0800 Message-ID: X-Mailer: git-send-email 2.40.1 X-TMN: [goJzEa1HI8zmfnpTu+7hRD9f1kJuvQHTD+COuP4gzLCLngiBi+fUBw==] X-ClientProxiedBy: BYAPR06CA0001.namprd06.prod.outlook.com (2603:10b6:a03:d4::14) To TYZPR01MB5556.apcprd01.prod.exchangelabs.com (2603:1096:400:363::9) X-Microsoft-Original-Message-ID: <20230901141042.1333694-1-hzyitc@outlook.com> MIME-Version: 1.0 X-MS-Exchange-MessageSentRepresentingType: 1 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: TYZPR01MB5556:EE_|SG2PR01MB3708:EE_ X-MS-Office365-Filtering-Correlation-Id: f0786a0b-1577-47e7-4a11-08dbaaf5499d X-MS-Exchange-SLBlob-MailProps: AZnQBsB9XmoY4vkZoXkQjSGaegPD/PwJbO0RmtOC6dXHu8Lgs2e8ue3xdn/dkXKN6A81VQDacrsW2bxhWiWdrV9AM11xEHqFUSWUWeABGnhvPoWV1CQ6SqcqXCyVHtTeoXV9EHpTBaZJJnm+m5qSgT3OLNTJ8z37u7jm+tH+PqNj+7amFiMCzdJdGQPqTVoo9dV+NY5f1nL5mOTa5yP4AxQxXwsyWaobAyzes9Dsmd/GJrzoTQXBSmYAuN3CECP3R3rEe6o3TVsKiZvdUgokwh7xzote99ONvvVieKp7FdqGofRdfy4r7V5eM0YxhkzKdBJ65FxquSulHYdRmcI+XeoW/SiUV2HwXb67JgVFAawUyiAbLSrMXJbDJjE8M3mZtwtr8bsG0Ptc3kj5PfbT1ykt2Cs0MxEuwUnnOGMptbywKUd1qJsNxE2E6zSKEqpohGbRO/ctxjnP8pqSmhqzPuiF3Yt5TrS0aS7cy97YCk3zUl1khn/TJWLeFTrUFJwKd928BbHo9xUFz6ZPx7+Mg9IVkCUT+rxhuEkdAh6JZtqy5b6elf1Ly96pYpe3dSY6qPaWP+2TvhmNDE353+QtW4tCJo+i+lExQJAwAvo1rz0+8AEzQ0xux3vU3ZpgcIycV3VVAP8fFI9UHhkoBnuR7AjBi28sg8jrcxaWDLOAIs8I0mk87QaM8cRLDUXB3OmJSc82FCoD5Ju8k6REsywXT9DqkULmOYTtxYoSXfF/kXNTDWm+7Qe5K024AInpeeS59ZQ3OZ1WtRw= X-Microsoft-Antispam: BCL:0; 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X is the UART ID. Starts from 1. 1-6 are in BLSP Block 1. 7-12 are in BLSP Block 2. Y is the index of mux config. Starts from 0. In dts, the serials are also named "blspX_uartY", but with different logic. X is the BLSP Block ID. Starts from 1. Y is the uart id inside block. In "ipq6018.dtsi" and "ipq8074.dtsi", it starts from 1. But in "ipq5332.dtsi" and "ipq9574.dtsi", it starts from 0. +-----------------+-----------------+-------------+-----------------+ | Block ID | ID inside Block | dts name | pinconfig name | | (Starts from 1) | (Starts from 1) | | | +-----------------+-----------------+-------------+-----------------+ | 1 | 1 | blsp1_uart1 | blsp0_uartY | | 1 | 2 | blsp1_uart2 | blsp1_uartY | | 1 | 6 | blsp1_uart6 | blsp5_uartY | | 2 | 1 | blsp2_uart1 | blsp6_uartY | | 2 | 6 | blsp2_uart6 | blsp12_uartY | +-----------------+-----------------+-------------+-----------------+ In "ipq5018.dts", "blsp1_uart1" (dts name) is the first serial (confimed by the address), So its pinconfig should be "blsp0_uart0" (pinconfig name, use GPIO 20 and 21) or "blsp0_uart1" (pinconfig name, use GPIO 28 and 29). Fixes: 570006756a16 ("arm64: dts: Add ipq5018 SoC and rdp432-c2 board support") Signed-off-by: Ziyang Huang --- Changes since v1: - Use corrent name in From Changes since v2: - Define 2 pinconfs for uart1 in ipq5018.dtsi - rdp432-c2 use uart1_pins_a arch/arm64/boot/dts/qcom/ipq5018-rdp432-c2.dts | 2 +- arch/arm64/boot/dts/qcom/ipq5018.dtsi | 15 +++++++++++---- 2 files changed, 12 insertions(+), 5 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/ipq5018-rdp432-c2.dts b/arch/arm64/boot/dts/qcom/ipq5018-rdp432-c2.dts index e636a1cb9b77..e83d1863e89c 100644 --- a/arch/arm64/boot/dts/qcom/ipq5018-rdp432-c2.dts +++ b/arch/arm64/boot/dts/qcom/ipq5018-rdp432-c2.dts @@ -23,7 +23,7 @@ chosen { }; &blsp1_uart1 { - pinctrl-0 = <&uart1_pins>; + pinctrl-0 = <&uart1_pins_a>; pinctrl-names = "default"; status = "okay"; }; diff --git a/arch/arm64/boot/dts/qcom/ipq5018.dtsi b/arch/arm64/boot/dts/qcom/ipq5018.dtsi index 9f13d2dcdfd5..50b4a2bd6fd3 100644 --- a/arch/arm64/boot/dts/qcom/ipq5018.dtsi +++ b/arch/arm64/boot/dts/qcom/ipq5018.dtsi @@ -103,11 +103,18 @@ tlmm: pinctrl@1000000 { interrupt-controller; #interrupt-cells = <2>; - uart1_pins: uart1-state { - pins = "gpio31", "gpio32", "gpio33", "gpio34"; - function = "blsp1_uart1"; + uart1_pins_a: uart1@0 { + pins = "gpio20", "gpio21"; + function = "blsp0_uart0"; drive-strength = <8>; - bias-pull-down; + bias-disabled; + }; + + uart1_pins_b: uart1@1 { + pins = "gpio28", "gpio29"; + function = "blsp0_uart1"; + drive-strength = <8>; + bias-disabled; }; };