| Message ID | d36f8c70e103bd6f740ebfaa512d246188aadf10.1708551850.git.quic_uchalich@quicinc.com |
|---|---|
| State | Superseded |
| Headers | show |
| Series | LLCC: Support for Broadcast_AND region | expand |
On 23/02/2024 00:07, Unnathi Chalicheemala wrote:
> Mapping Broadcast_AND region for LLCC in SM8550.
I don't understand this sentence and I still do not know why.
Best regards,
Krzysztof
On 2/27/2024 7:49 AM, Krzysztof Kozlowski wrote: > On 23/02/2024 00:07, Unnathi Chalicheemala wrote: >> Mapping Broadcast_AND region for LLCC in SM8550. > > I don't understand this sentence and I still do not know why. > The check of whether status bit is 1 in the driver is being done with the wrong register all along (sm8450 onwards). So I am adding the base address of the right register region in the DeviceTree files. I can add this explanation to the commit message of these patches if you think that would help. > Best regards, > Krzysztof >
diff --git a/arch/arm64/boot/dts/qcom/sm8550.dtsi b/arch/arm64/boot/dts/qcom/sm8550.dtsi index ee1ba5a8c8fc..1a52e30330c3 100644 --- a/arch/arm64/boot/dts/qcom/sm8550.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8550.dtsi @@ -4193,12 +4193,14 @@ system-cache-controller@25000000 { <0 0x25200000 0 0x200000>, <0 0x25400000 0 0x200000>, <0 0x25600000 0 0x200000>, - <0 0x25800000 0 0x200000>; + <0 0x25800000 0 0x200000>, + <0 0x25a00000 0 0x200000>; reg-names = "llcc0_base", "llcc1_base", "llcc2_base", "llcc3_base", - "llcc_broadcast_base"; + "llcc_broadcast_base", + "llcc_broadcast_and_base"; interrupts = <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>; };
Mapping Broadcast_AND region for LLCC in SM8550. Signed-off-by: Unnathi Chalicheemala <quic_uchalich@quicinc.com> --- arch/arm64/boot/dts/qcom/sm8550.dtsi | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-)