| Message ID | 20211217093325.30612-1-conor.dooley@microchip.com |
|---|---|
| Headers | show |
| Series | Update the Icicle Kit device tree | expand |
On Fri, Dec 17, 2021 at 09:33:15AM +0000, conor.dooley@microchip.com wrote: > From: Conor Dooley <conor.dooley@microchip.com> > > Add device tree bindings for the real time clock on > the Microchip PolarFire SoC. > > Signed-off-by: Conor Dooley <conor.dooley@microchip.com> > Signed-off-by: Daire McNamara <daire.mcnamara@microchip.com> > --- > .../bindings/rtc/microchip,mfps-rtc.yaml | 63 +++++++++++++++++++ > 1 file changed, 63 insertions(+) > create mode 100644 Documentation/devicetree/bindings/rtc/microchip,mfps-rtc.yaml > > diff --git a/Documentation/devicetree/bindings/rtc/microchip,mfps-rtc.yaml b/Documentation/devicetree/bindings/rtc/microchip,mfps-rtc.yaml > new file mode 100644 > index 000000000000..d57460cbe5e3 > --- /dev/null > +++ b/Documentation/devicetree/bindings/rtc/microchip,mfps-rtc.yaml > @@ -0,0 +1,63 @@ > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) > +%YAML 1.2 > +--- > +$id: http://devicetree.org/schemas/rtc/microchip,mfps-rtc.yaml# > + > +$schema: http://devicetree.org/meta-schemas/core.yaml# > + > +title: Microchip PolarFire Soc (MPFS) RTC Device Tree Bindings > + > +allOf: > + - $ref: rtc.yaml# > + > +maintainers: > + - Daire McNamara <daire.mcnamara@microchip.com> > + - Lewis Hanly <lewis.hanly@microchip.com> > + > +properties: > + compatible: > + enum: > + - microchip,mpfs-rtc > + > + reg: > + maxItems: 1 > + > + interrupts: > + maxItems: 2 Need to define what each one is. > + > + microchip,prescaler: > + description: | > + The prescaler divides the input frequency to create a time-based strobe (typically 1 Hz) for > + the calendar counter. The Alarm and Compare Registers, in conjunction with the calendar > + counter, facilitate time-matched events. To properly operate in Calendar or Binary mode, > + the 26-bit prescaler must be programmed to generate a strobe to the RTC. > + maxItems: 1 > + $ref: /schemas/types.yaml#/definitions/uint32 > + > + clocks: > + maxItems: 1 > + > + clock-names: > + items: > + - const: rtc > + > +required: > + - compatible > + - reg > + - interrupts > + - clocks > + - clock-names > + > +additionalProperties: false > + > +examples: > + - | > + #include <dt-bindings/clock/microchip,mpfs-clock.h> > + rtc@20124000 { > + compatible = "microchip,mpfs-rtc"; > + reg = <0x20124000 0x1000>; > + clocks = <&clkcfg CLK_RTC>; > + clock-names = "rtc"; > + interrupts = <80>, <81>; > + }; > +... > -- > 2.33.1 > >
On Fri, Dec 17, 2021 at 09:33:19AM +0000, conor.dooley@microchip.com wrote: > From: Conor Dooley <conor.dooley@microchip.com> > > Add device tree bindings for the usb controller on > the Microchip PolarFire SoC. > > Signed-off-by: Conor Dooley <conor.dooley@microchip.com> > --- > .../bindings/usb/microchip,mpfs-musb.yaml | 61 +++++++++++++++++++ > 1 file changed, 61 insertions(+) > create mode 100644 Documentation/devicetree/bindings/usb/microchip,mpfs-musb.yaml > > diff --git a/Documentation/devicetree/bindings/usb/microchip,mpfs-musb.yaml b/Documentation/devicetree/bindings/usb/microchip,mpfs-musb.yaml > new file mode 100644 > index 000000000000..eec918046c73 > --- /dev/null > +++ b/Documentation/devicetree/bindings/usb/microchip,mpfs-musb.yaml > @@ -0,0 +1,61 @@ > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) > +%YAML 1.2 > +--- > +$id: http://devicetree.org/schemas/usb/microchip,mpfs-musb.yaml# > +$schema: http://devicetree.org/meta-schemas/core.yaml# > + > +title: Microchip MPFS USB Controller Device Tree Bindings > + > +maintainers: > + - Conor Dooley <conor.dooley@microchip.com> > + > +properties: > + compatible: > + enum: > + - microchip,mpfs-musb > + > + reg: > + maxItems: 1 > + > + interrupts: > + minItems: 2 > + maxItems: 2 > + > + interrupt-names: > + items: > + - const: dma > + - const: mc > + > + clocks: > + maxItems: 1 > + > + dr_mode: > + enum: > + - host > + - otg > + - peripheral Reference usb-drd.yaml and you can drop this. > + > +required: > + - compatible > + - reg > + - interrupts > + - interrupt-names > + - clocks > + - dr_mode > + > +additionalProperties: false > + > +examples: > + - | > + #include "dt-bindings/clock/microchip,mpfs-clock.h" > + usb: usb@20201000 { Drop unused labels. > + compatible = "microchip,mpfs-musb"; > + reg = <0x20201000 0x1000>; > + clocks = <&clkcfg CLK_USB>; > + interrupt-parent = <&plic>; > + interrupts = <86>, <87>; > + interrupt-names = "dma","mc"; space ^ > + dr_mode = "host"; > + }; > + > +... > -- > 2.33.1 > >
On Fri, 17 Dec 2021 09:33:09 +0000, conor.dooley@microchip.com wrote: > From: Ivan Griffin <ivan.griffin@microchip.com> > > Provide named identifiers for device tree for RISC-V interrupts. > > Licensed under GPL and MIT, as this file may be useful to any OS that > uses device tree. > > Signed-off-by: Ivan Griffin <ivan.griffin@microchip.com> > Signed-off-by: Conor Dooley <conor.dooley@microchip.com> > --- > .../interrupt-controller/riscv-hart.h | 19 +++++++++++++++++++ > 1 file changed, 19 insertions(+) > create mode 100644 include/dt-bindings/interrupt-controller/riscv-hart.h > Acked-by: Rob Herring <robh@kernel.org>
On Fri, Dec 17, 2021 at 09:33:11AM +0000, conor.dooley@microchip.com wrote: > From: Conor Dooley <conor.dooley@microchip.com> > > Make the system controller on the Polarfire SoC > a "simple,mfd" so that the services can be child > nodes of the system controller node. > > Signed-off-by: Conor Dooley <conor.dooley@microchip.com> > --- > .../microchip,mpfs-sys-controller.yaml | 33 +++++++++++++++++-- > 1 file changed, 30 insertions(+), 3 deletions(-) > > diff --git a/Documentation/devicetree/bindings/soc/microchip/microchip,mpfs-sys-controller.yaml b/Documentation/devicetree/bindings/soc/microchip/microchip,mpfs-sys-controller.yaml > index f699772fedf3..014cb44b8f31 100644 > --- a/Documentation/devicetree/bindings/soc/microchip/microchip,mpfs-sys-controller.yaml > +++ b/Documentation/devicetree/bindings/soc/microchip/microchip,mpfs-sys-controller.yaml > @@ -13,13 +13,34 @@ description: | > The PolarFire SoC system controller is communicated with via a mailbox. > This document describes the bindings for the client portion of that mailbox. > > - > properties: > mboxes: > maxItems: 1 > > compatible: > - const: microchip,mpfs-sys-controller > + items: > + - const: microchip,mpfs-sys-controller > + - const: simple-mfd 'simple-mfd' means there is zero dependency on the parent for the child nodes. Isn't 'mboxes' a dependency? > + > + hwrandom: > + type: object > + > + properties: > + compatible: > + const: microchip,mpfs-rng > + > + required: > + - compatible > + > + sysserv: > + type: object > + > + properties: > + compatible: > + const: microchip,mpfs-generic-service > + > + required: > + - compatible There's not really any need to have child nodes which have no resources. The driver for microchip,mpfs-sys-controller can create child devices. Rob
On Tuesday, December 21st, 2021 at 17:55, Rob Herring <robh@kernel.org> wrote: >On Fri, Dec 17, 2021 at 09:33:11AM +0000, conor.dooley@microchip.com wrote: >> From: Conor Dooley <conor.dooley@microchip.com> >> >> Make the system controller on the Polarfire SoC >> a "simple,mfd" so that the services can be child >> nodes of the system controller node. >> >> Signed-off-by: Conor Dooley <conor.dooley@microchip.com> >> --- >> .../microchip,mpfs-sys-controller.yaml | 33 +++++++++++++++++-- >> 1 file changed, 30 insertions(+), 3 deletions(-) >> >> diff --git a/Documentation/devicetree/bindings/soc/microchip/microchip,mpfs-sys-controller.yaml b/>Documentation/devicetree/bindings/soc/microchip/microchip,mpfs-sys-controller.yaml >> index f699772fedf3..014cb44b8f31 100644 >> --- a/Documentation/devicetree/bindings/soc/microchip/microchip,mpfs-sys-controller.yaml >> +++ b/Documentation/devicetree/bindings/soc/microchip/microchip,mpfs-sys-controller.yaml >> @@ -13,13 +13,34 @@ description: | >> The PolarFire SoC system controller is communicated with via a mailbox. >> This document describes the bindings for the client portion of that mailbox. >> >> - >> properties: >> mboxes: >> maxItems: 1 >> >> compatible: >> - const: microchip,mpfs-sys-controller >> + items: >> + - const: microchip,mpfs-sys-controller >> + - const: simple-mfd > >'simple-mfd' means there is zero dependency on the parent for the child >nodes. Isn't 'mboxes' a dependency? I suppose it is. I was going off what had been done for the bcm2835 firmware for the rpi its also a mailbox providing "services". (arm/bcm/raspberrypi,bcm2835-firmware.yaml) > >> + >> + hwrandom: >> + type: object >> + >> + properties: >> + compatible: >> + const: microchip,mpfs-rng >> + >> + required: >> + - compatible >> + >> + sysserv: >> + type: object >> + >> + properties: >> + compatible: >> + const: microchip,mpfs-generic-service >> + >> + required: >> + - compatible > >There's not really any need to have child nodes which have no resources. >The driver for microchip,mpfs-sys-controller can create child devices. I am assuming by this you mean say, take a list of boolean properties and convert those into child devices? There's a fairly decent number of services provided by the system controller and these children just represent the subset that we've implemented so far. Conor > >Rob
On 17/12/2021 15:09, Krzysztof Kozlowski wrote: > EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe > > On 17/12/2021 10:33, conor.dooley@microchip.com wrote: >> From: Conor Dooley <conor.dooley@microchip.com> >> >> Update the RISC-V/Microchip entry by adding the microchip dts >> directory and myself as maintainer >> >> Signed-off-by: Conor Dooley <conor.dooley@microchip.com> >> --- >> MAINTAINERS | 2 ++ >> 1 file changed, 2 insertions(+) >> >> diff --git a/MAINTAINERS b/MAINTAINERS >> index 7a2345ce8521..3b1d6be7bd56 100644 >> --- a/MAINTAINERS >> +++ b/MAINTAINERS >> @@ -16348,8 +16348,10 @@ K: riscv >> >> RISC-V/MICROCHIP POLARFIRE SOC SUPPORT >> M: Lewis Hanly <lewis.hanly@microchip.com> >> +M: Conor Dooley <conor.dooley@microchip.com> >> L: linux-riscv@lists.infradead.org >> S: Supported >> +F: arch/riscv/boot/dts/microchip/ >> F: drivers/mailbox/mailbox-mpfs.c >> F: drivers/soc/microchip/ >> F: include/soc/microchip/mpfs.h >> > > Good to have the DTS covered, so FWIW: > Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com> > > You still should get Lewis' ack (unless he merges it) Aye, it'll be an ack. We don't currently have a tree & would rather do this via risc-v than the at91/sam arm soc tree. > > Best regards, > Krzysztof >
On Thu, 23 Dec 2021 06:56:45 PST (-0800), Conor.Dooley@microchip.com wrote: > On 17/12/2021 15:09, Krzysztof Kozlowski wrote: >> EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe >> >> On 17/12/2021 10:33, conor.dooley@microchip.com wrote: >>> From: Conor Dooley <conor.dooley@microchip.com> >>> >>> Update the RISC-V/Microchip entry by adding the microchip dts >>> directory and myself as maintainer >>> >>> Signed-off-by: Conor Dooley <conor.dooley@microchip.com> >>> --- >>> MAINTAINERS | 2 ++ >>> 1 file changed, 2 insertions(+) >>> >>> diff --git a/MAINTAINERS b/MAINTAINERS >>> index 7a2345ce8521..3b1d6be7bd56 100644 >>> --- a/MAINTAINERS >>> +++ b/MAINTAINERS >>> @@ -16348,8 +16348,10 @@ K: riscv >>> >>> RISC-V/MICROCHIP POLARFIRE SOC SUPPORT >>> M: Lewis Hanly <lewis.hanly@microchip.com> >>> +M: Conor Dooley <conor.dooley@microchip.com> >>> L: linux-riscv@lists.infradead.org >>> S: Supported >>> +F: arch/riscv/boot/dts/microchip/ >>> F: drivers/mailbox/mailbox-mpfs.c >>> F: drivers/soc/microchip/ >>> F: include/soc/microchip/mpfs.h >>> >> >> Good to have the DTS covered, so FWIW: >> Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com> >> >> You still should get Lewis' ack (unless he merges it) > Aye, it'll be an ack. We don't currently have a tree & would rather do > this via risc-v than the at91/sam arm soc tree. WFM. I'll be awaiting the ack. I don't see any fundamental issues from my end, as long is it's got all the acks/reviews then I'm generally fine with this sort of stuff. I'll take a look before merging it, I'm kind of buried right now. Sorry! >> >> Best regards, >> Krzysztof >> >
On 17/12/2021 15:09, Krzysztof Kozlowski wrote: > EXTERNAL EMAIL: Do not click links or open attachments unless you know > the content is safe > > On 17/12/2021 10:33, conor.dooley@microchip.com wrote: >> From: Conor Dooley <conor.dooley@microchip.com> >> >> Update the RISC-V/Microchip entry by adding the microchip dts >> directory and myself as maintainer >> >> Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Lewis Hanly <lewis.hanly@microchip.com> >> --- >> MAINTAINERS | 2 ++ >> 1 file changed, 2 insertions(+) >> >> diff --git a/MAINTAINERS b/MAINTAINERS index >> 7a2345ce8521..3b1d6be7bd56 100644 >> --- a/MAINTAINERS >> +++ b/MAINTAINERS >> @@ -16348,8 +16348,10 @@ K: riscv >> >> RISC-V/MICROCHIP POLARFIRE SOC SUPPORT >> M: Lewis Hanly <lewis.hanly@microchip.com> >> +M: Conor Dooley <conor.dooley@microchip.com> >> L: linux-riscv@lists.infradead.org >> S: Supported >> +F: arch/riscv/boot/dts/microchip/ >> F: drivers/mailbox/mailbox-mpfs.c >> F: drivers/soc/microchip/ >> F: include/soc/microchip/mpfs.h >> > > Good to have the DTS covered, so FWIW: > Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com> > > You still should get Lewis' ack (unless he merges it) Aye, it'll be an ack. We don't currently have a tree & would rather do this via risc-v than the at91/sam arm soc tree. > > Best regards, > Krzysztof >
From: Conor Dooley <conor.dooley@microchip.com> This series updates the Microchip Icicle Kit device tree by adding a host of peripherals, and some updates to the memory map. In addition, the device tree has been split into a third part, which contains "soft" peripherals that are in the fpga fabric. Several of the entries are for peripherals that have not get had their drivers upstreamed, so in those cases the dt bindings are included where appropriate in order to avoid as many "DT compatible string <x> appears un-documented" errors as possible. Depends on mpfs clock driver series [1] to provide: dt-bindings/clock/microchip,mpfs-clock.h and on the other changes to the icicle/mpfs device tree (mmc) that are already in linux/riscv/for-next. Also depends on Geert's format changes to interrupt grouping etc [2]. Additionally, the interrupt-extended warnings on the plic/clint are cleared by [3] & [4], which lore appears to have been very confused about. [1] https://lore.kernel.org/linux-clk/20211216140022.16146-1-conor.dooley@microchip.com/T/ [2] https://lore.kernel.org/linux-riscv/cover.1639660956.git.geert@linux-m68k.org/T/ [3] https://patchwork.kernel.org/project/linux-riscv/cover/cover.1639662093.git.geert@linux-m68k.org/ [4] https://patchwork.kernel.org/project/linux-riscv/cover/cover.1639661878.git.geert@linux-m68k.org/ Conor Dooley (16): dt-bindings: soc/microchip: update syscontroller compatibles dt-bindings: soc/microchip: make systemcontroller a mfd mailbox: change mailbox-mpfs compatible string dt-bindings: i2c: add bindings for microchip mpfs i2c dt-bindings: rng: add bindings for microchip mpfs rng dt-bindings: rtc: add bindings for microchip mpfs rtc dt-bindings: soc/microchip: add bindings for mpfs system services dt-bindings: gpio: add bindings for microchip mpfs gpio dt-bindings: spi: add bindings for microchip mpfs spi dt-bindings: usb: add bindings for microchip mpfs musb dt-bindings: pwm: add microchip corePWM binding riscv: dts: microchip: use hart and clk defines for icicle kit riscv: dts: microchip: add fpga fabric section to icicle kit riscv: dts: microchip: refactor icicle kit device tree riscv: dts: microchip: update peripherals in icicle kit device tree MAINTAINERS: update riscv/microchip entry Ivan Griffin (1): dt-bindings: interrupt-controller: create a header for RISC-V interrupts .../bindings/gpio/microchip,mpfs-gpio.yaml | 80 +++++ .../bindings/i2c/microchip,mpfs-i2c.yaml | 54 ++++ ...ilbox.yaml => microchip,mpfs-mailbox.yaml} | 6 +- .../bindings/pwm/microchip,corepwm.yaml | 61 ++++ .../bindings/rng/microchip,mpfs-rng.yaml | 29 ++ .../bindings/rtc/microchip,mfps-rtc.yaml | 63 ++++ .../microchip,mpfs-generic-service.yaml | 33 ++ .../microchip,mpfs-sys-controller.yaml | 62 ++++ ...icrochip,polarfire-soc-sys-controller.yaml | 35 --- .../bindings/spi/microchip,mpfs-spi.yaml | 61 ++++ .../bindings/usb/microchip,mpfs-musb.yaml | 61 ++++ MAINTAINERS | 2 + .../dts/microchip/microchip-mpfs-fabric.dtsi | 13 + .../microchip/microchip-mpfs-icicle-kit.dts | 111 +++++-- .../boot/dts/microchip/microchip-mpfs.dtsi | 295 ++++++++++++++---- drivers/mailbox/mailbox-mpfs.c | 2 +- .../interrupt-controller/riscv-hart.h | 19 ++ 17 files changed, 872 insertions(+), 115 deletions(-) create mode 100644 Documentation/devicetree/bindings/gpio/microchip,mpfs-gpio.yaml create mode 100644 Documentation/devicetree/bindings/i2c/microchip,mpfs-i2c.yaml rename Documentation/devicetree/bindings/mailbox/{microchip,polarfire-soc-mailbox.yaml => microchip,mpfs-mailbox.yaml} (82%) create mode 100644 Documentation/devicetree/bindings/pwm/microchip,corepwm.yaml create mode 100644 Documentation/devicetree/bindings/rng/microchip,mpfs-rng.yaml create mode 100644 Documentation/devicetree/bindings/rtc/microchip,mfps-rtc.yaml create mode 100644 Documentation/devicetree/bindings/soc/microchip/microchip,mpfs-generic-service.yaml create mode 100644 Documentation/devicetree/bindings/soc/microchip/microchip,mpfs-sys-controller.yaml delete mode 100644 Documentation/devicetree/bindings/soc/microchip/microchip,polarfire-soc-sys-controller.yaml create mode 100644 Documentation/devicetree/bindings/spi/microchip,mpfs-spi.yaml create mode 100644 Documentation/devicetree/bindings/usb/microchip,mpfs-musb.yaml create mode 100644 arch/riscv/boot/dts/microchip/microchip-mpfs-fabric.dtsi create mode 100644 include/dt-bindings/interrupt-controller/riscv-hart.h