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[209.132.180.67]) by mx.google.com with ESMTP id q16si2824191pfg.221.2018.03.10.07.23.03; Sat, 10 Mar 2018 07:23:03 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-crypto-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=VMf6V7QQ; spf=pass (google.com: best guess record for domain of linux-crypto-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-crypto-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S932308AbeCJPXC (ORCPT + 1 other); Sat, 10 Mar 2018 10:23:02 -0500 Received: from mail-wm0-f66.google.com ([74.125.82.66]:50589 "EHLO mail-wm0-f66.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S932325AbeCJPXA (ORCPT ); Sat, 10 Mar 2018 10:23:00 -0500 Received: by mail-wm0-f66.google.com with SMTP id w128so8941889wmw.0 for ; Sat, 10 Mar 2018 07:22:59 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=ghtE/+HMhJ7+BEn8JVj07Uf/eaORWShrkPULyd1WCu8=; b=VMf6V7QQDK1FdmxfpKtNnLbFsdW5ywaElZ+MUDBevO5/6hGLvC2p+mpzayQBOluVa4 DVZ4pLMe3/1JAHYXiLF829Or0FglWvOUFrOEQH3+2oY54mis9Np5hyaUs/shwLn6yEpz s7rQGiyK9CbdbJoA/C5VfHJwEycb5VH3TTEbM= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=ghtE/+HMhJ7+BEn8JVj07Uf/eaORWShrkPULyd1WCu8=; b=stRVMQpjd/2iB8b2mtQzx5wEtO+4oXS7zk+UHRtoN5voyUF1pa3cP0lqRpJNKwikVn TFio6z2GbM8Dinavd8Jld3Z5HRBvVAsUJ1Vnbdndkc6eaW2mvtS+J77RiHufmQBW444J v1pVeD1OdPg1OqaLPnHuFYUJhtVKrgIOWTHX+Czh0uEVA+9mjbnRFWrw4a4jkj0fr9l9 OH+BECLiZaDCl95iJQeF9XXgMv0a6iL0b1V6rlD4Yjyw/XCwjYSJjapyECys3ZMrnsug Iy/uLIA95hu5UuynjDHdV9M0X0how6uipGkzE0fMCWbmFIXVONCQXbUFfFpkJ9jb215J fU+A== X-Gm-Message-State: AElRT7Gb1XULrk8eb0TI6xRQypY85zjBYhXMfStbMwijB47Ho5rLHaAq 00lfoqoFkMFM6b93Wm77k3dFoSfMxOA= X-Received: by 10.28.1.14 with SMTP id 14mr1318939wmb.40.1520695378429; Sat, 10 Mar 2018 07:22:58 -0800 (PST) Received: from localhost.localdomain ([105.148.128.186]) by smtp.gmail.com with ESMTPSA id m9sm7027531wrf.13.2018.03.10.07.22.56 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Sat, 10 Mar 2018 07:22:57 -0800 (PST) From: Ard Biesheuvel To: linux-crypto@vger.kernel.org Cc: herbert@gondor.apana.org.au, linux-arm-kernel@lists.infradead.org, Ard Biesheuvel , Dave Martin , Russell King - ARM Linux , Sebastian Andrzej Siewior , Mark Rutland , linux-rt-users@vger.kernel.org, Peter Zijlstra , Catalin Marinas , Will Deacon , Steven Rostedt , Thomas Gleixner Subject: [PATCH v5 10/23] arm64: assembler: add utility macros to push/pop stack frames Date: Sat, 10 Mar 2018 15:21:55 +0000 Message-Id: <20180310152208.10369-11-ard.biesheuvel@linaro.org> X-Mailer: git-send-email 2.15.1 In-Reply-To: <20180310152208.10369-1-ard.biesheuvel@linaro.org> References: <20180310152208.10369-1-ard.biesheuvel@linaro.org> Sender: linux-crypto-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-crypto@vger.kernel.org We are going to add code to all the NEON crypto routines that will turn them into non-leaf functions, so we need to manage the stack frames. To make this less tedious and error prone, add some macros that take the number of callee saved registers to preserve and the extra size to allocate in the stack frame (for locals) and emit the ldp/stp sequences. Signed-off-by: Ard Biesheuvel --- arch/arm64/include/asm/assembler.h | 70 ++++++++++++++++++++ 1 file changed, 70 insertions(+) -- 2.15.1 diff --git a/arch/arm64/include/asm/assembler.h b/arch/arm64/include/asm/assembler.h index 053d83e8db6f..eef1fd2c1c0b 100644 --- a/arch/arm64/include/asm/assembler.h +++ b/arch/arm64/include/asm/assembler.h @@ -555,6 +555,19 @@ USER(\label, ic ivau, \tmp2) // invalidate I line PoU #endif .endm +/* + * Errata workaround post TTBR0_EL1 update. + */ + .macro post_ttbr0_update_workaround +#ifdef CONFIG_CAVIUM_ERRATUM_27456 +alternative_if ARM64_WORKAROUND_CAVIUM_27456 + ic iallu + dsb nsh + isb +alternative_else_nop_endif +#endif + .endm + /** * Errata workaround prior to disable MMU. Insert an ISB immediately prior * to executing the MSR that will change SCTLR_ELn[M] from a value of 1 to 0. @@ -565,4 +578,61 @@ USER(\label, ic ivau, \tmp2) // invalidate I line PoU #endif .endm + /* + * frame_push - Push @regcount callee saved registers to the stack, + * starting at x19, as well as x29/x30, and set x29 to + * the new value of sp. Add @extra bytes of stack space + * for locals. + */ + .macro frame_push, regcount:req, extra + __frame st, \regcount, \extra + .endm + + /* + * frame_pop - Pop the callee saved registers from the stack that were + * pushed in the most recent call to frame_push, as well + * as x29/x30 and any extra stack space that may have been + * allocated. + */ + .macro frame_pop + __frame ld + .endm + + .macro __frame_regs, reg1, reg2, op, num + .if .Lframe_regcount == \num + \op\()r \reg1, [sp, #(\num + 1) * 8] + .elseif .Lframe_regcount > \num + \op\()p \reg1, \reg2, [sp, #(\num + 1) * 8] + .endif + .endm + + .macro __frame, op, regcount, extra=0 + .ifc \op, st + .if (\regcount) < 0 || (\regcount) > 10 + .error "regcount should be in the range [0 ... 10]" + .endif + .if ((\extra) % 16) != 0 + .error "extra should be a multiple of 16 bytes" + .endif + .set .Lframe_regcount, \regcount + .set .Lframe_extra, \extra + .set .Lframe_local_offset, ((\regcount + 3) / 2) * 16 + stp x29, x30, [sp, #-.Lframe_local_offset - .Lframe_extra]! + mov x29, sp + .elseif .Lframe_regcount == -1 // && op == 'ld' + .error "frame_push/frame_pop may not be nested" + .endif + + __frame_regs x19, x20, \op, 1 + __frame_regs x21, x22, \op, 3 + __frame_regs x23, x24, \op, 5 + __frame_regs x25, x26, \op, 7 + __frame_regs x27, x28, \op, 9 + + .ifc \op, ld + ldp x29, x30, [sp], #.Lframe_local_offset + .Lframe_extra + .set .Lframe_regcount, -1 + .endif + .endm + #endif /* __ASM_ASSEMBLER_H */