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[v4,03/11] RISC-V: add TOOLCHAIN_HAS_VECTOR_CRYPTO in kconfig

Message ID 20231231152743.6304-4-jerry.shih@sifive.com
State New
Headers show
Series RISC-V: provide some accelerated cryptography implementations using vector extensions | expand

Commit Message

Jerry Shih Dec. 31, 2023, 3:27 p.m. UTC 
LLVM main and binutils master now both fully support v1.0 of the RISC-V
vector crypto extensions. Check the assembler capability for using the
vector crypto asm mnemonics in kernel.

Co-developed-by: Eric Biggers <ebiggers@google.com>
Signed-off-by: Eric Biggers <ebiggers@google.com>
Signed-off-by: Jerry Shih <jerry.shih@sifive.com>
---
 arch/riscv/Kconfig | 8 ++++++++
 1 file changed, 8 insertions(+)
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Patch

diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig
index 0a03d72706b5..8647392ece0b 100644
--- a/arch/riscv/Kconfig
+++ b/arch/riscv/Kconfig
@@ -636,6 +636,14 @@  config TOOLCHAIN_NEEDS_OLD_ISA_SPEC
 	  versions of clang and GCC to be passed to GAS, which has the same result
 	  as passing zicsr and zifencei to -march.
 
+# This option indicates that the toolchain supports all v1.0 vector crypto
+# extensions, including Zvk*, Zvbb, and Zvbc. The LLVM added all of these at
+# once. The binutils added all except Zvkb, then added Zvkb. So we just check
+# for Zvkb.
+config TOOLCHAIN_HAS_VECTOR_CRYPTO
+	def_bool $(as-instr, .option arch$(comma) +zvkb)
+	depends on AS_HAS_OPTION_ARCH
+
 config FPU
 	bool "FPU support"
 	default y