diff mbox series

[v5,1/7] crypto: stm32 - Save 54 CSR registers

Message ID E1pYOKD-000GYe-HX@formenos.hmeau.com
State Superseded
Headers show
Series crypto: stm32 - Save and restore between each request | expand

Commit Message

Herbert Xu March 4, 2023, 9:37 a.m. UTC
The CSR registers go from 0 to 53.  So the number of registers
should be 54.

Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
---

 drivers/crypto/stm32/stm32-hash.c |    2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

Comments

Linus Walleij March 5, 2023, 9:48 p.m. UTC | #1
On Sat, Mar 4, 2023 at 10:37 AM Herbert Xu <herbert@gondor.apana.org.au> wrote:

> The CSR registers go from 0 to 53.  So the number of registers
> should be 54.
>
> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>

Hm I don't know where this misunderstanding comes from.
I think it's this tendency by some engineers to use index 1 :/

The datasheet for U8500 says:
0xF8            HASH_CSFULL      HASH context full register
0xFC            HASH_CSDATAIN    HASH context swap data input register
0x100           HASH_CSR0        HASH context swap register 0
0x104 to 0x1CC  HASH_CSR1 to 51  HASH context swap register 1 to 51

0xf8, 0xfc, 0x100 = 3 registers
0x104 to 0x1cc = 51 registers

Indeed 54.

Reviewed-by: Linus Walleij <linus.walleij@linaro.org>
Tested-by: Linus Walleij <linus.walleij@linaro.org>

Yours,
Linus Walleij
diff mbox series

Patch

diff --git a/drivers/crypto/stm32/stm32-hash.c b/drivers/crypto/stm32/stm32-hash.c
index 7bf805563ac2..bde2b40a6a32 100644
--- a/drivers/crypto/stm32/stm32-hash.c
+++ b/drivers/crypto/stm32/stm32-hash.c
@@ -68,7 +68,7 @@ 
 #define HASH_MASK_DATA_INPUT		BIT(1)
 
 /* Context swap register */
-#define HASH_CSR_REGISTER_NUMBER	53
+#define HASH_CSR_REGISTER_NUMBER	54
 
 /* Status Flags */
 #define HASH_SR_DATA_INPUT_READY	BIT(0)