From patchwork Tue Dec 12 18:02:23 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alexandre TORGUE X-Patchwork-Id: 121616 Delivered-To: patch@linaro.org Received: by 10.140.22.227 with SMTP id 90csp4442930qgn; Tue, 12 Dec 2017 10:03:26 -0800 (PST) X-Google-Smtp-Source: ACJfBosJdkbDbFfsTFFCHF6PC+RovA3bW88WQRsLkER/8HJVq3mFpcB8zSiKlLlYfj/Fhl8g4yLp X-Received: by 10.98.130.4 with SMTP id w4mr3064763pfd.238.1513101806013; Tue, 12 Dec 2017 10:03:26 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1513101806; cv=none; d=google.com; s=arc-20160816; b=tdK6dFqUVcsIvdpRTVbIPmFaxQq3oS9lQ4npZOGQXSfodc0wIGk2I3uROiVOrG3TrL qkSJcpN1LREtJ8kqQDKDzBglT4cAUWLECKRbqkw24aAJiyDnPzEIsJzUeV5WikvdQtoh 9SAmM4M27lo7jMKG8Gz4P2k/bFYp75kVKyJhnkO2HPhyr7e5xt3rUT7LnVz0kpjcEqZ1 3mYFSW8xiKU4MrJt838I3TTmruJIQc+UyklNZiLi6smvg9W1/wWqImmPceZKRJNz8Xo0 hTWMqV6IEhqVjMYdQVHiLWiZ1phwec9ytUbWNOrHwe8b5/hnTbvWzxQbF+UeUwA2qGki HpKA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:mime-version:message-id:date:subject:cc :to:from:arc-authentication-results; bh=9C59FQbiDXvaRFt/zzlre3InlNZftFBbYvaGpsQCoO8=; b=aty0PEoy8zClakpHT1SKW/xoWDrEEjgxtlxgaX5wI5aH64FMXNDhNzuCxwAlDsjM5J BGSAmf7FX17MyBTFdtYsur8qmjGuGEg1TEqLTej9eqGyh36Na+cuN/wKNSUDlrQSsDwv Lrm00P93K2jUitIZciOvWpEuEk9EtxcM53pAcltSKdPJ89aiSl3j2mShOl0xCu8i41Xj siJpnOFJPtWT3FOW0vxiv6kW5zZGwaApeZoGvDePcDJQOJsUVV2ik9y1sSBBCn+34Pus +ywJsL1MUqqS58EW+fH5QOhTO2lzjwLwl4b1RIKfLpCByt4OTjvvGahKSFfUh0Rx13OC CXpw== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id w5si9400569plz.214.2017.12.12.10.03.25; Tue, 12 Dec 2017 10:03:26 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752601AbdLLSDX (ORCPT + 6 others); Tue, 12 Dec 2017 13:03:23 -0500 Received: from mx08-00178001.pphosted.com ([91.207.212.93]:58945 "EHLO mx07-00178001.pphosted.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1752588AbdLLSDV (ORCPT ); Tue, 12 Dec 2017 13:03:21 -0500 Received: from pps.filterd (m0046660.ppops.net [127.0.0.1]) by mx08-.pphosted.com (8.16.0.21/8.16.0.21) with SMTP id vBCHx3ux022448; Tue, 12 Dec 2017 19:02:28 +0100 Received: from beta.dmz-eu.st.com (beta.dmz-eu.st.com [164.129.1.35]) by mx08-00178001.pphosted.com with ESMTP id 2etjpercd7-1 (version=TLSv1 cipher=ECDHE-RSA-AES256-SHA bits=256 verify=NOT); Tue, 12 Dec 2017 19:02:28 +0100 Received: from zeta.dmz-eu.st.com (zeta.dmz-eu.st.com [164.129.230.9]) by beta.dmz-eu.st.com (STMicroelectronics) with ESMTP id BAC0E38; Tue, 12 Dec 2017 18:02:27 +0000 (GMT) Received: from Webmail-eu.st.com (sfhdag3node2.st.com [10.75.127.8]) by zeta.dmz-eu.st.com (STMicroelectronics) with ESMTP id 96BFB5255; Tue, 12 Dec 2017 18:02:27 +0000 (GMT) Received: from localhost (10.75.127.45) by SFHDAG3NODE2.st.com (10.75.127.8) with Microsoft SMTP Server (TLS) id 15.0.1347.2; Tue, 12 Dec 2017 19:02:27 +0100 From: Alexandre Torgue To: Maxime Coquelin , , , , , , CC: , Subject: [PATCH 0/3] Enable DMA on STM32 MCU based on cortex-M7 Date: Tue, 12 Dec 2017 19:02:23 +0100 Message-ID: <1513101746-18030-1-git-send-email-alexandre.torgue@st.com> X-Mailer: git-send-email 2.7.4 MIME-Version: 1.0 X-Originating-IP: [10.75.127.45] X-ClientProxiedBy: SFHDAG5NODE1.st.com (10.75.127.13) To SFHDAG3NODE2.st.com (10.75.127.8) X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10432:, , definitions=2017-12-12_10:, , signatures=0 Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org This series enable DMA on several STM32 MCU based on cortex-M7. To make it possible, a dedicated dma pool memory area has to be created. This patchset activate also ARM_MPU flag which will configure MPU (Memory Protection Unit) according to devicetree information (mem and dma-pool). Note that on cortex-M7 DMA has to use a NO cache-able memory region. Regards Alex Alexandre Torgue (3): ARM: dts: stm32: add DMA memory pool on MCU which embed a cortex-M7 ARM: configs: stm32: Enable ARM_MPU ARM: dts: stm32: enable dma on MCU which embed a cortex-M7 arch/arm/boot/dts/stm32746g-eval.dts | 21 +++++++++++++++++++++ arch/arm/boot/dts/stm32f769-disco.dts | 21 +++++++++++++++++++++ arch/arm/boot/dts/stm32h743i-disco.dts | 21 +++++++++++++++++++++ arch/arm/boot/dts/stm32h743i-eval.dts | 21 +++++++++++++++++++++ arch/arm/configs/stm32_defconfig | 1 + 5 files changed, 85 insertions(+) -- 2.7.4 -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html