From patchwork Thu Jun 18 08:38:07 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kunihiko Hayashi X-Patchwork-Id: 191087 Delivered-To: patch@linaro.org Received: by 2002:a54:30ca:0:0:0:0:0 with SMTP id e10csp1125720ecs; Thu, 18 Jun 2020 01:38:32 -0700 (PDT) X-Google-Smtp-Source: ABdhPJzLa/cOplVGKYnb/9YVJDlQf7pLAvd0RXsDHMODQugKMw1U4C19zwMr4jPqDD2ezpzTiHPB X-Received: by 2002:a17:906:3c4c:: with SMTP id i12mr2016099ejg.464.1592469512471; Thu, 18 Jun 2020 01:38:32 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1592469512; cv=none; d=google.com; s=arc-20160816; b=XRR9RVqc++iNCdVzj29OaX8vDbYraqxMGSepcKb4EerTSa1xFzWGRa2BFOwcG1jh7y yPMCh6dABnem68PcXf4jQ7VFxkZrtF0MJYu9U5yd5mLsUe0h46/G7Ye50zVfjQlkknTY S1Z38H2IAJrTjhw+gQCqsr1oztpQfBMunAEY2PSb+mKFID9olVOs1BtnFzqlS1kgO4hu AoSG1pp7MD1Qw6F8TEd5QObNcETdbxy/yaBGWtrTNAvwIzGUIrDjyhnWGVP4Eq0EDcyI HIrjnx9OhEJwM+YnfImX4AXDOYiPwTw+qGdGDcj12fcpY5EKXnfXSmT0+0bT8sXKy8X6 v0LA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:message-id:date:subject:cc:to:from; bh=cQNpM/DvwVHxZ6AaM+qWKXxVPahQT3Ax/68K3bf5ZC0=; b=oPrPaRzwvre+DQvDRWzW0gWrH40xTAw+haTKqOvXzVomreZscQUfiLo1LuRF0P7NCE fUH7orc/AnxUiZhxdMrc85wLp7FZF+/k5OgJEP/kfaBCn34vZDbxgW5kLAS/JQ6axPzo HM49biK2hFBiIrrJ3l4rOhRLqm3OZTbYCjyPbNeYHHJJn1Abdvqa9jNaEXRiHOMdFALm 2xAh3JmGBgRBLg6ZFMx8GQOK5nPkTTXUdNJDPgWVkWVEj1bPU2K3H4gstTNDtulH+ged CY+ognPEulXqAfU6O8qNbLYycsQhiIW+pnN+UH0cCajr/PO6w2Kkk/Je3ESU3arHFbk9 p39A== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [23.128.96.18]) by mx.google.com with ESMTP id t23si1229408eji.737.2020.06.18.01.38.32; Thu, 18 Jun 2020 01:38:32 -0700 (PDT) Received-SPF: pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; spf=pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728834AbgFRIi3 (ORCPT + 6 others); Thu, 18 Jun 2020 04:38:29 -0400 Received: from mx.socionext.com ([202.248.49.38]:19334 "EHLO mx.socionext.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1728731AbgFRIiZ (ORCPT ); Thu, 18 Jun 2020 04:38:25 -0400 Received: from unknown (HELO iyokan-ex.css.socionext.com) ([172.31.9.54]) by mx.socionext.com with ESMTP; 18 Jun 2020 17:38:23 +0900 Received: from mail.mfilter.local (m-filter-1 [10.213.24.61]) by iyokan-ex.css.socionext.com (Postfix) with ESMTP id 4B19960066; Thu, 18 Jun 2020 17:38:23 +0900 (JST) Received: from 172.31.9.51 (172.31.9.51) by m-FILTER with ESMTP; Thu, 18 Jun 2020 17:38:23 +0900 Received: from plum.e01.socionext.com (unknown [10.213.132.32]) by kinkan.css.socionext.com (Postfix) with ESMTP id D588B1A12AD; Thu, 18 Jun 2020 17:38:22 +0900 (JST) From: Kunihiko Hayashi To: Bjorn Helgaas , Lorenzo Pieralisi , Jingoo Han , Gustavo Pimentel , Rob Herring , Masahiro Yamada , Marc Zyngier Cc: linux-pci@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Masami Hiramatsu , Jassi Brar , Kunihiko Hayashi Subject: [PATCH v5 0/6] PCI: uniphier: Add features for UniPhier PCIe host controller Date: Thu, 18 Jun 2020 17:38:07 +0900 Message-Id: <1592469493-1549-1-git-send-email-hayashi.kunihiko@socionext.com> X-Mailer: git-send-email 2.7.4 Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org This series adds some features for UniPhier PCIe host controller. - Add support for PME and AER invoked by MSI interrupt - Add iATU register view support for PCIe version >= 4.80 - Add an error message when failing to get phy driver This adds a new function called by MSI handler in DesignWare PCIe framework, that invokes PME and AER funcions to detect the factor from SoC-dependent registers. Changes since v4: - Add Acked-by: line to dwc patch Changes since v3: - Move msi_host_isr() call into dw_handle_msi_irq() - Move uniphier_pcie_misc_isr() call into the guard of chained_irq - Use a bool argument is_msi instead of pci_msi_enabled() - Consolidate handler calls for the same interrupt - Fix typos in commit messages Changes since v2: - Avoid printing phy error message in case of EPROBE_DEFER - Fix iATU register mapping method - dt-bindings: Add Acked-by: line - Fix typos in commit messages - Use devm_platform_ioremap_resource_byname() Changes since v1: - Add check if struct resource is NULL - Fix warning in the type of dev_err() argument Kunihiko Hayashi (6): PCI: dwc: Add msi_host_isr() callback PCI: uniphier: Add misc interrupt handler to invoke PME and AER dt-bindings: PCI: uniphier: Add iATU register description PCI: uniphier: Add iATU register support PCI: uniphier: Add error message when failed to get phy PCI: uniphier: Use devm_platform_ioremap_resource_byname() .../devicetree/bindings/pci/uniphier-pcie.txt | 1 + drivers/pci/controller/dwc/pcie-designware-host.c | 3 + drivers/pci/controller/dwc/pcie-designware.h | 1 + drivers/pci/controller/dwc/pcie-uniphier.c | 73 +++++++++++++++++----- 4 files changed, 63 insertions(+), 15 deletions(-) -- 2.7.4