| Message ID | 1627581885-32165-1-git-send-email-sibis@codeaurora.org |
|---|---|
| Headers | show |
| Series | Fixup register offsets to support per core L3 DCVS | expand |
On Thu, 29 Jul 2021 23:34:42 +0530, Sibi Sankar wrote: > Re-arranging the register regions to support per core L3 DCVS would lead > to bindings breakage when using an older dt with a newer kernel. So, > document the EPSS compatible for SM8250/SM8350 SoCs and use them in the > CPUFreq-hw driver to prevent such breakages. > > Signed-off-by: Sibi Sankar <sibis@codeaurora.org> > --- > Documentation/devicetree/bindings/cpufreq/cpufreq-qcom-hw.txt | 6 +++++- > 1 file changed, 5 insertions(+), 1 deletion(-) > Acked-by: Rob Herring <robh@kernel.org>
Quoting Sibi Sankar (2021-07-29 11:04:42) > Re-arranging the register regions to support per core L3 DCVS would lead > to bindings breakage when using an older dt with a newer kernel. So, > document the EPSS compatible for SM8250/SM8350 SoCs and use them in the > CPUFreq-hw driver to prevent such breakages. > > Signed-off-by: Sibi Sankar <sibis@codeaurora.org> > --- Reviewed-by: Stephen Boyd <swboyd@chromium.org>
On Thu, Jul 29, 2021 at 11:34:44PM +0530, Sibi Sankar wrote: > Fixup the register regions used by the cpufreq node on SC7280 SoC to > support per core L3 DCVS. > > Fixes: 7dbd121a2c58 ("arm64: dts: qcom: sc7280: Add cpufreq hw node") > Signed-off-by: Sibi Sankar <sibis@codeaurora.org> This patch landed in the Bjorn's tree, however the corresponding driver change ("cpufreq: qcom: Re-arrange register offsets to support per core L3 DCVS" / https://patchwork.kernel.org/project/linux-arm-msm/patch/1627581885-32165-3-git-send-email-sibis@codeaurora.org/) did not land in any maintainer tree yet AFAIK. IIUC the DT change alone breaks cpufreq since the changed register regions require the changed offset in the cpufreq driver. Sibi, please confirm or clarify that my concern is unwarranted.
On 2021-08-31 22:34, Bjorn Andersson wrote: > On Tue 31 Aug 08:30 PDT 2021, Matthias Kaehlcke wrote: > >> On Thu, Jul 29, 2021 at 11:34:44PM +0530, Sibi Sankar wrote: >> > Fixup the register regions used by the cpufreq node on SC7280 SoC to >> > support per core L3 DCVS. >> > >> > Fixes: 7dbd121a2c58 ("arm64: dts: qcom: sc7280: Add cpufreq hw node") >> > Signed-off-by: Sibi Sankar <sibis@codeaurora.org> >> >> This patch landed in the Bjorn's tree, however the corresponding >> driver >> change ("cpufreq: qcom: Re-arrange register offsets to support per >> core >> L3 DCVS" / >> https://patchwork.kernel.org/project/linux-arm-msm/patch/1627581885-32165-3-git-send-email-sibis@codeaurora.org/) >> did not land in any maintainer tree yet AFAIK. IIUC the DT change >> alone >> breaks cpufreq since the changed register regions require the changed >> offset in the cpufreq driver. >> > > Thanks for the note Matthias, it must have slipped by as I scraped the > inbox for things that looked ready. > > I'm actually not in favor of splitting these memory blocks in DT to > facilitate the Linux implementation of splitting that in multiple > drivers... > > But I've not been following up on that discussion. > > Regards, > Bjorn > >> Sibi, please confirm or clarify that my concern is unwarranted. Let's drop the patch asap as it breaks SC7280 cpufreq on lnext without the driver changes. -- Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, a Linux Foundation Collaborative Project.
Qualcomm SoCs (starting with SM8350) support per core voting for L3 cache frequency. The patch series re-arranges the cpufreq register offsets to allow access for the L3 interconnect to implement per core control i.e. the first 0x100 is now accessed by the L3 interconnect driver instead. L3 interconnect provider node on SC7280 SoC: epss_l3: interconnect@18590000 { compatible = "qcom,sc7280-epss-l3"; reg = <0 0x18590000 0 0x1000>, <0 0x18591000 0 0x100>, <0 0x18592000 0 0x100>, <0 0x18593000 0 0x100>; ... }; CPUFREQ node on SC7280 SoC: cpufreq_hw: cpufreq@18591000 { compatible = "qcom,cpufreq-epss"; reg = <0 0x18591100 0 0x900>, <0 0x18592100 0 0x900>, <0 0x18593100 0 0x900>; ... }; The patch series also prevents binding breakage by using the SM8250/SM8350 EPSS compatible. Sibi Sankar (4): dt-bindings: cpufreq: cpufreq-qcom-hw: Add compatible for SM8250/8350 cpufreq: qcom: Re-arrange register offsets to support per core L3 DCVS arm64: dts: qcom: sc7280: Fixup the cpufreq node arm64: dts: qcom: sm8350: Fixup the cpufreq node .../bindings/cpufreq/cpufreq-qcom-hw.txt | 6 +++++- arch/arm64/boot/dts/qcom/sc7280.dtsi | 6 +++--- arch/arm64/boot/dts/qcom/sm8350.dtsi | 9 ++++----- drivers/cpufreq/qcom-cpufreq-hw.c | 23 ++++++++++++++++++---- 4 files changed, 31 insertions(+), 13 deletions(-)