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[v5,0/5] PCI: qcom: Add support for OPP

Message ID 1694066433-8677-1-git-send-email-quic_krichai@quicinc.com
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Series PCI: qcom: Add support for OPP | expand

Message

Krishna Chaitanya Chundru Sept. 7, 2023, 6 a.m. UTC
This patch adds support for OPP to vote for the performance state of RPMH
power domain based upon GEN speed it PCIe got enumerated.

Before link up PCIe driver will vote for the maximum performance state.

Add API dev_pm_opp_find_level_floor to find To find the highest opp for a device
based on the level.

Changes from v4:
	- Added a separate patch for returning error from the qcom_pcie_upadate
	  and moved opp update logic to icc_update and used a bool variable to 
	  update the opp.
	- Addressed comments made by pavan.
changes from v3:
	- Removing the opp vote on suspend when the link is not up and link is not
	  up and add debug prints as suggested by pavan.
	- Added dev_pm_opp_find_level_floor API to find the highest opp to vote.
changes from v2:
	- Instead of using the freq based opp search use level based as suggested
	  by Dmitry Baryshkov.
Changes from v1:
        - Addressed comments from Krzysztof Kozlowski.
        - Added the rpmhpd_opp_xxx phandle as suggested by pavan.
        - Added dev_pm_opp_set_opp API call which was missed on previous patch.

Krishna chaitanya chundru (5):
  dt-bindings: pci: qcom: Add opp table
  arm64: dts: qcom: sm8450: Add opp table support to PCIe
  opp: Add dev_pm_opp_find_level_floor()
  PCI: qcom: Return error from 'qcom_pcie_icc_update'
  PCI: qcom: Add OPP support to scale performance state of power domain

 .../devicetree/bindings/pci/qcom,pcie.yaml         |  4 ++
 arch/arm64/boot/dts/qcom/sm8450.dtsi               | 47 ++++++++++++++++
 drivers/opp/core.c                                 | 25 +++++++++
 drivers/pci/controller/dwc/pcie-qcom.c             | 63 ++++++++++++++++++----
 include/linux/pm_opp.h                             |  9 ++++
 5 files changed, 137 insertions(+), 11 deletions(-)

Comments

Krishna Chaitanya Chundru Sept. 7, 2023, 9:56 a.m. UTC | #1
On 9/7/2023 2:34 PM, Konrad Dybcio wrote:
> On 7.09.2023 08:00, Krishna chaitanya chundru wrote:
>> PCIe needs to choose the appropriate performance state of RPMH power
>> domain based up on the PCIe gen speed.
>>
>> So let's add the OPP table support to specify RPMH performance states.
>>
>> Use opp-level for the PCIe gen speed for easier use.
>>
>> Signed-off-by: Krishna chaitanya chundru <quic_krichai@quicinc.com>
>> ---
> [...]
>
>> +
>> +			pcie1_opp_table: opp-table {
>> +				compatible = "operating-points-v2";
>> +
>> +				opp-1 {
>> +					opp-level = <1>;
>> +					required-opps = <&rpmhpd_opp_low_svs>;
>> +				};
>> +
>> +				opp-2 {
>> +					opp-level = <2>;
>> +					required-opps = <&rpmhpd_opp_low_svs>;
>> +				};
>> +
>> +				opp-3 {
>> +					opp-level = <3>;
>> +					required-opps = <&rpmhpd_opp_low_svs>;
> Is gen3 not supposed to require nom like on pcie0?
This particular controller instance can operate at low svs for GEN3.
> Also, can all non-maximum OPPs run at just low_svs?
This depends on the hardware capability, for this instance expect GEN4 
remaining can operate in LOW svs. It varies from controller instance to 
instance and also from target to target.
> Konrad

- KC