From patchwork Thu Dec 14 16:09:54 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Shameerali Kolothum Thodi X-Patchwork-Id: 121987 Delivered-To: patch@linaro.org Received: by 10.140.22.227 with SMTP id 90csp7006493qgn; Thu, 14 Dec 2017 08:11:55 -0800 (PST) X-Google-Smtp-Source: ACJfBovYUaBLBdhibLogqaZhdAGW+v2Q/Zm3dQjChVwGF9pwlimeorTdUDbDDZ2MosKpCD3hH7Zo X-Received: by 10.84.174.129 with SMTP id r1mr10178431plb.337.1513267915600; Thu, 14 Dec 2017 08:11:55 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1513267915; cv=none; d=google.com; s=arc-20160816; b=ODKGyspfSabKlCmSgzlWdRIZ6sSUlur1O0uV+C191EWnaFv/ggJtQ9Cwb4LBxx9ULK G44SUhEHzj1QUzqM8lYwzOWg8ODVUn1bvf0ebHhtwrYCAsMxWcoVdlaxk32SslY1JXFc BpIYiNP4JjBLggog2BePgJIeKZklaN+/WK6ycFyMJRUjJoKIptMHfe8ucUeLTKx3nMna t6EnnEMFZV+/Q2V+E+xTNpIwJXdcL/mGZzPj6226rVOLFPRYBC78sIYxD/ewK/JR3TYu GyA0d6R5YM6dfHZ+Cj7WN/UKCCtrz3BYEm9AlcHUx+NQubWPlayA7e75WzFURsOnWu1b A7Cw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:mime-version:message-id:date:subject:cc :to:from:arc-authentication-results; bh=E74OFo8Dq28eq/KYaL1ilmtmbzpQNDbMii6w//Wqu0I=; b=m4qNeODK32wcoQCODgYSX4DPcNffk3ooKfz7kz+H5YZaPHToc3SpakZnEVtNweQiBX 2LE9IVGxsulS6/b5w1CK6I0jo9iSr0wAC1xCvHNxuWvUsMaS4aC/MzapIrNVUkmuuHHa mEkC1hMPLw8iND1cDI45xIzmQ5XSw2eZ+OfJTrcQ1YJxOBYqX4AtVOyU59Qcq3Ir0cFJ x+YTc1ronZo6sRNKIhc3uvu5vsB9beldyFAit3jaY/Br5sPzlUCOfESGgfKe52l3hVuF eftoTNznwhX/PoTADp+oFVx/D3DYZiBhtIOcrWbzKC0tASDeZrVz4q1vsHZGKy7HkWFy JRjg== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id w88si3480079pfj.200.2017.12.14.08.11.54; Thu, 14 Dec 2017 08:11:55 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753327AbdLNQLw (ORCPT + 6 others); Thu, 14 Dec 2017 11:11:52 -0500 Received: from szxga04-in.huawei.com ([45.249.212.190]:2683 "EHLO huawei.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1753285AbdLNQLs (ORCPT ); Thu, 14 Dec 2017 11:11:48 -0500 Received: from DGGEMS401-HUB.china.huawei.com (unknown [172.30.72.59]) by Forcepoint Email with ESMTP id 14F7713480777; Fri, 15 Dec 2017 00:11:33 +0800 (CST) Received: from S00345302A-PC.china.huawei.com (10.202.227.237) by DGGEMS401-HUB.china.huawei.com (10.3.19.201) with Microsoft SMTP Server id 14.3.361.1; Fri, 15 Dec 2017 00:11:24 +0800 From: Shameer Kolothum To: , , , CC: , , , , , , , , , Shameer Kolothum Subject: [PATCH v12 0/3] iommu/smmu-v3: Workaround for hisilicon 161010801 erratum(reserve HW MSI) Date: Thu, 14 Dec 2017 16:09:54 +0000 Message-ID: <20171214160957.13716-1-shameerali.kolothum.thodi@huawei.com> X-Mailer: git-send-email 2.12.0.windows.1 MIME-Version: 1.0 X-Originating-IP: [10.202.227.237] X-CFilter-Loop: Reflected Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org On certain HiSilicon platforms (hip06/hip07) the GIC ITS and PCIe RC deviates from the standard implementation and this breaks PCIe MSI functionality when SMMU is enabled. The HiSilicon erratum 161010801 describes this limitation of certain HiSilicon platforms to support the SMMU mappings for MSI transactions. On these platforms GICv3 ITS translator is presented with the deviceID by extending the MSI payload data to 64 bits to include the deviceID. Hence, the PCIe controller on this platforms has to differentiate the MSI payload against other DMA payload and has to modify the MSI payload. This basically makes it difficult for this platforms to have a SMMU translation for MSI. This patch implements an ACPI based quirk to reserve the hw msi regions in the smmu-v3 driver which means these address regions will not be translated and will be excluded from iova allocations. To implement this quirk, the following changes are incorporated: 1. Added a generic helper function to IORT code to retrieve and reserve the associated ITS base address from a device IORT node. The function has a check for smmu model to determine whether the platform requires the HW MSI reservation or not. 2. Added smmu node entries and explicitly disabled them in hip06/hip07 dts files so that users are warned about the non-DT support for this erratum. Changelog: v11--> v12 -Thanks to Lorenzo, Fixed !CONFIG_IOMMU_API compile error(patch #1). v10 --> v11 -Addressed comments from Lorenzo(patch#1) -Added Robin's Reviewed-by to patch #2 v9 --> v10 Addressed comments: -Moved smmu model check to iort helper function to selectively apply the msi reservation which will make the fn call generic from iommu-dma. -Removed PCI blacklisting patch, instead added smmu nodes(disabled) with comments to hip06/hip07 dts file. v8 --> v9 -Thanks to Marc, fixed IORT helper function to reserve the ITS translater region only. -Removed the DT support for MSI reservation and blacklisted HiSilicon PCIe controllers on DT based systems when SMMUv3 is enabled. v7 --> v8 Addressed comments from Rob and Lorenzo: -Modified to use DT compatible string for errata. -Changed logic to retrieve the msi-parent for DT case. v6 --> v7 Addressed request from Will to add DT support for the erratum: - added bt binding - add of_iommu_msi_get_resv_regions() New arm64 silicon errata entry Rename iort_iommu_{its->msi}_get_resv_regions v5 --> v6 Addressed comments from Robin and Lorenzo: -No change to patch#1 . -Reverted v5 patch#2 as this might break the platforms where this quirk is not applicable. Provided a generic function in iommu code and added back the quirk implementation in SMMU v3 driver(patch#3) v4 --> v5 Addressed comments from Robin and Lorenzo: -Added a comment to make it clear that, for now, only straightforward HW topologies are handled while reserving ITS regions(patch #1). v3 --> v4 Rebased on 4.13-rc1. Addressed comments from Robin, Will and Lorenzo: -As suggested by Robin, moved the ITS msi reservation into iommu_dma_get_resv_regions(). -Added its_count != resv region failure case(patch #1). v2 --> v3 Addressed comments from Lorenzo and Robin: -Removed dev_is_pci() check in smmuV3 driver. -Don't treat device not having an ITS mapping as an error in iort helper function. v1 --> v2 -patch 2/2: Invoke iort helper fn based on fwnode type(acpi). RFCv2 -->PATCH -Incorporated Lorenzo's review comments. RFC v1 --> RFC v2 Based on Robin's review comments, -Removed the generic erratum framework. -Using IORT/MADT tables to retrieve the ITS base addr instead of vendor specific CSRT table. Shameer Kolothum (3): ACPI/IORT: Add msi address regions reservation helper iommu/dma: Add HW MSI(GICv3 ITS) address regions reservation arm64:dts:hisilicon Disable hisilicon smmu node on hip06/hip07 arch/arm64/boot/dts/hisilicon/hip06.dtsi | 56 ++++++++++++++++ arch/arm64/boot/dts/hisilicon/hip07.dtsi | 25 +++++++ drivers/acpi/arm64/iort.c | 111 ++++++++++++++++++++++++++++++- drivers/iommu/dma-iommu.c | 8 ++- drivers/irqchip/irq-gic-v3-its.c | 3 +- include/linux/acpi_iort.h | 7 +- 6 files changed, 204 insertions(+), 6 deletions(-) -- 1.9.1 -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html