From patchwork Tue Sep 15 08:43:01 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Zhen Lei X-Patchwork-Id: 303980 Delivered-To: patch@linaro.org Received: by 2002:a92:5ad1:0:0:0:0:0 with SMTP id b78csp2338101ilg; Tue, 15 Sep 2020 01:43:40 -0700 (PDT) X-Google-Smtp-Source: ABdhPJxiOBHBK24k9aYsLRPhv9IxNExe5xR/fCufXEaV2L4P4e/C/ig894xbtqnzBSV0HChYMoRm X-Received: by 2002:a05:6402:456:: with SMTP id p22mr20891761edw.177.1600159420058; Tue, 15 Sep 2020 01:43:40 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1600159420; cv=none; d=google.com; s=arc-20160816; b=Mwxblwhgqsgjypobz4HyD5Sao1oSZ46hq05CcAusZ2u9aMAuK035inweitzO3H/kWV aIFbx+FPpA/PG6O72EGgbtFRPzXBuzCOn6fjpri4yoO/VJhV91WjqJrWWZAm17gdw+jD ro4HwkM45jRwmJ8mg9S1ZtCI0HsSaSFTW0Tl7wnU4sF9xWfqLyTZSNyBCGLu2CNUpeux QcmN/QPIE0/NYIFVWFoEVhSl5BFjABpNhlChSzhlthzzjiKHIlviOd2MK0cznmkt7wLH n5/7/UfAd6mNPhCBKkI4v9VDlsIF7EZpFqKpqkRW9+k6rtwCwECtspRU1fzJfZs67pVC /Ykg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:content-transfer-encoding:mime-version :message-id:date:subject:cc:to:from; bh=h4Qz1tWbsy+QZIhgK46Mhd4KlCqRX7wppvy4N7CGA84=; b=rZgKke3Q1wL2adYPHXGJAZEt+GUbV1QCPpK8kmzYITaMQp/hB10s9cgZnn0yFHicL8 ku78fobY+uctmnzTsiyv9D5d4qGRrQDT/yGiCsvC2hX95Ow69U6l2EI2jbDigP8/0Od4 /LCb1A/HCRBRtxCU6J6S7rzF13h4GGOPeUP2loAc0e4wUYhO7S+cEWOjfcSUjbmeFF9h suAKsj5kEGoFaaVonVPV8z9vph3/ki9knfXt/HfMKs4emYq3bJ3kW1xvr3jzbAryxKs0 V8cgnFDIYTERmOoTLkwFiOsfXABUXY0E7Sz/Gj07YVTT9gUDWAzmfTKN68NMfght3SQs 0tQg== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [23.128.96.18]) by mx.google.com with ESMTP id i19si8725816ejd.384.2020.09.15.01.43.39; Tue, 15 Sep 2020 01:43:40 -0700 (PDT) Received-SPF: pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; spf=pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726122AbgIOIni (ORCPT + 6 others); Tue, 15 Sep 2020 04:43:38 -0400 Received: from szxga05-in.huawei.com ([45.249.212.191]:12263 "EHLO huawei.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1726087AbgIOInh (ORCPT ); Tue, 15 Sep 2020 04:43:37 -0400 Received: from DGGEMS412-HUB.china.huawei.com (unknown [172.30.72.59]) by Forcepoint Email with ESMTP id 45AAE387E0E933AA5B0E; Tue, 15 Sep 2020 16:43:35 +0800 (CST) Received: from thunder-town.china.huawei.com (10.174.177.253) by DGGEMS412-HUB.china.huawei.com (10.3.19.212) with Microsoft SMTP Server id 14.3.487.0; Tue, 15 Sep 2020 16:43:30 +0800 From: Zhen Lei To: Thomas Gleixner , Jason Cooper , Marc Zyngier , Rob Herring , Guo Ren , devicetree , linux-csky , linux-kernel CC: Zhen Lei , Sebastian Hesselbarth , Haoyu Lv , Libin , Kefeng Wang , "Jianguo Chen" Subject: [PATCH v4 0/4] irqchip: dw-apb-ictl: support hierarchy irq domain Date: Tue, 15 Sep 2020 16:43:01 +0800 Message-ID: <20200915084305.3085-1-thunder.leizhen@huawei.com> X-Mailer: git-send-email 2.26.0.windows.1 MIME-Version: 1.0 X-Originating-IP: [10.174.177.253] X-CFilter-Loop: Reflected Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org v3 --> v4: 1. remove "gc->chip_types[0].chip.irq_eoi = irq_gc_noop;", the "chip.irq_eoi" hook is not needed by handle_level_irq(). Thanks for Marc Zyngier's review. 2. Add a new patch: define an empty function set_handle_irq() if !GENERIC_IRQ_MULTI_HANDLER to avoid compilation error on arch/arc system. v2 --> v3: 1. change (1 << hwirq) to BIT(hwirq). 2. change __exception_irq_entry to __irq_entry, so we can "#include " instead of "#include ". Ohterwise, an compilation error will be reported on arch/csky. drivers/irqchip/irq-dw-apb-ictl.c:20:10: fatal error: asm/exception.h: No such file or directory 3. use "if (!parent || (np == parent))" to determine whether it is primary interrupt controller. 4. make the primary interrupt controller case also use function handle_level_irq(), I used handle_fasteoi_irq() as flow_handler before. 5. Other minor changes are not detailed. v1 --> v2: According to Marc Zyngier's suggestion, discard adding an independent SD5203-VIC driver, but make the dw-apb-ictl irqchip driver to support hierarchy irq domain. It was originally available only for secondary interrupt controller, now it can also be used as primary interrupt controller. The related dt-bindings is updated appropriately. Add "Suggested-by: Marc Zyngier ". Add "Tested-by: Haoyu Lv ". v1: The interrupt controller of SD5203 SoC is VIC(vector interrupt controller), it's based on Synopsys DesignWare APB interrupt controller (dw_apb_ictl) IP, but it can not directly use dw_apb_ictl driver. The main reason is that VIC is used as primary interrupt controller and dw_apb_ictl driver worked for secondary interrupt controller. So add a new driver: "hisilicon,sd5203-vic". Zhen Lei (4): genirq: define an empty function set_handle_irq() if !GENERIC_IRQ_MULTI_HANDLER irqchip: dw-apb-ictl: prepare for support hierarchy irq domain irqchip: dw-apb-ictl: support hierarchy irq domain dt-bindings: dw-apb-ictl: support hierarchy irq domain .../interrupt-controller/snps,dw-apb-ictl.txt | 14 +++- drivers/irqchip/Kconfig | 2 +- drivers/irqchip/irq-dw-apb-ictl.c | 83 ++++++++++++++++++---- include/linux/irq.h | 2 + 4 files changed, 87 insertions(+), 14 deletions(-) -- 1.8.3