From patchwork Tue Jan 12 01:55:59 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Leizhen \(ThunderTown\)" X-Patchwork-Id: 361139 Delivered-To: patch@linaro.org Received: by 2002:a02:85a7:0:0:0:0:0 with SMTP id d36csp3364050jai; Mon, 11 Jan 2021 18:01:59 -0800 (PST) X-Google-Smtp-Source: ABdhPJy733BKcSYRC1ASQNPvSkCuzqhzHKtZa7oBpv4gHy5dpa/VaswDJXkiSmGUbJZNp2G8JGea X-Received: by 2002:a17:906:5f92:: with SMTP id a18mr1612004eju.126.1610416919753; Mon, 11 Jan 2021 18:01:59 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1610416919; cv=none; d=google.com; s=arc-20160816; b=TlmvgTaO0yux+QzFD7l5gGYkhEsQJWy8a8m9GVomjBs9v3ed9p9IypjWWw6R1RYdGU xDK4M6WytFT5zDYhYBZjiafHlhigqjFdyg3hi1GABWGeHT1oGBJ1NkPDRS27V104QFXf zQz5XEUXVSBGfBxkTub4L7bHlvoU741qKO2xN3n6IbMwnhaq4r6kB5UChOjre60gEGRu +IkrZJk34VJPNUjwWKZ77AyGP9ANsu2F8nb04b5Baadnj7PUoI1pfvXZgc0bKZPSZ3pQ 43+HIgVCPMCeDyD4L/olTbJUk/MOGh1F6fntbsP7QKpz/6R7MN1AEwU6Sp6OZR0wiKRm 69Tg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :message-id:date:subject:cc:to:from; bh=Wj6gr+Ux7kMGYHv5h4gukiqxFvslTpHvqDrpWnAk7Rg=; b=eGTx30MqkXPVeekdFqLWmM5AT6BDJHVKbgNATzZ62wLBuwVIMiVMwJzDun6ObE3kBU 8d+/UVYdMZi5FwR1UrBWhy/W6wws7OzP9G97r5g18EiWiAO/X70SUndzbYeKQJMgjWkV MulWa5X5SiDtUXdsVnDnRGJaH35SeHpB4ffHiYUDgQgHRAWSg5f6oAx3+3K0RtmIZHVJ 0Xmf+vws9IrIBvzthOLec3u1RvnP+YjbVzpZuPRY5ZPj5T97ieJrR7+fxLCALyWF1/Z9 xc9DslsnyEZ4FQLfDBhxvPxHeWl4HaUfdt44oMCr6YG/U7dgzwgVSw+MN2nrniv6+o6/ oV6Q== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [23.128.96.18]) by mx.google.com with ESMTP id pw3si472761ejb.186.2021.01.11.18.01.59; Mon, 11 Jan 2021 18:01:59 -0800 (PST) Received-SPF: pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; spf=pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1725957AbhALCBe (ORCPT + 6 others); Mon, 11 Jan 2021 21:01:34 -0500 Received: from szxga04-in.huawei.com ([45.249.212.190]:10706 "EHLO szxga04-in.huawei.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1729060AbhALCBd (ORCPT ); Mon, 11 Jan 2021 21:01:33 -0500 Received: from DGGEMS413-HUB.china.huawei.com (unknown [172.30.72.60]) by szxga04-in.huawei.com (SkyGuard) with ESMTP id 4DFDKL20q2zl3xJ; Tue, 12 Jan 2021 09:59:34 +0800 (CST) Received: from thunder-town.china.huawei.com (10.174.176.220) by DGGEMS413-HUB.china.huawei.com (10.3.19.213) with Microsoft SMTP Server id 14.3.498.0; Tue, 12 Jan 2021 10:00:42 +0800 From: Zhen Lei To: Russell King , Greg Kroah-Hartman , Will Deacon , "Haojian Zhuang" , Arnd Bergmann , Rob Herring , Wei Xu , devicetree , linux-arm-kernel , linux-kernel CC: Zhen Lei Subject: [PATCH v3 0/3] Add Hisilicon L3 cache controller support Date: Tue, 12 Jan 2021 09:55:59 +0800 Message-ID: <20210112015602.497-1-thunder.leizhen@huawei.com> X-Mailer: git-send-email 2.26.0.windows.1 MIME-Version: 1.0 X-Originating-IP: [10.174.176.220] X-CFilter-Loop: Reflected Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org v2 --> v3: Add Hisilicon L3 cache controller driver and its document. That's: patch 2-3. v1 --> v2: Discard the middle-tier functions and do silent narrowing cast in the outcache hook functions. For example: -static void l2c220_inv_range(unsigned long start, unsigned long end) +static void l2c220_inv_range(phys_addr_t pa_start, phys_addr_t pa_end) { + unsigned long start = pa_start; + unsigned long end = pa_end; v1: Do cast phys_addr_t to unsigned long by adding a middle-tier function. For example: -static void l2c220_inv_range(unsigned long start, unsigned long end) +static void __l2c220_inv_range(unsigned long start, unsigned long end) { ... } +static void l2c220_inv_range(phys_addr_t start, phys_addr_t end) +{ + __l2c220_inv_range(start, end); +} Zhen Lei (3): ARM: LPAE: Use phys_addr_t instead of unsigned long in outercache hooks dt-bindings: arm: hisilicon: Add binding for L3 cache controller ARM: Add Hisilicon L3 cache controller support .../bindings/arm/hisilicon/l3cache.yaml | 37 +++++ arch/arm/include/asm/outercache.h | 6 +- arch/arm/mm/Kconfig | 9 ++ arch/arm/mm/Makefile | 1 + arch/arm/mm/cache-feroceon-l2.c | 15 +- arch/arm/mm/cache-hisi-l3.c | 153 ++++++++++++++++++ arch/arm/mm/cache-hisi-l3.h | 30 ++++ arch/arm/mm/cache-l2x0.c | 50 ++++-- arch/arm/mm/cache-tauros2.c | 15 +- arch/arm/mm/cache-uniphier.c | 6 +- arch/arm/mm/cache-xsc3l2.c | 12 +- 11 files changed, 305 insertions(+), 29 deletions(-) create mode 100644 Documentation/devicetree/bindings/arm/hisilicon/l3cache.yaml create mode 100644 arch/arm/mm/cache-hisi-l3.c create mode 100644 arch/arm/mm/cache-hisi-l3.h -- 2.26.0.106.g9fadedd