| Message ID | 20210218064019.29189-1-lizhih@xilinx.com |
|---|---|
| Headers | show |
| Series | XRT Alveo driver overview | expand |
On 2/17/21 10:40 PM, Lizhi Hou wrote: > Hello, > > This is V3 of patch series which adds management physical function driver for Xilinx > Alveo PCIe accelerator cards, https://www.xilinx.com/products/boards-and-kits/alveo.html > This driver is part of Xilinx Runtime (XRT) open source stack. > > XILINX ALVEO PLATFORM ARCHITECTURE Thanks for refreshing this patchset. It will take me a while to do the full review, so I thought I would give some early feed back. It applies to char-misc-next, but will have conflicts with in-flight patches around the MAINTAINERS file. This is not a big deal. The checkpatch is much better over v2, the complaints are WARNING: added, moved or deleted file(s), does MAINTAINERS need updating? #21: new file mode 100644 WARNING: From:/Signed-off-by: email address mismatch: 'From: Lizhi Hou <lizhi.hou@xilinx.com>' != 'Signed-off-by: Lizhi Hou <lizhih@xilinx.com>' MAINTAINERS warning i believe you address in the last patch. In the next revisions, please fix the signoff. The test robot is complaining about hppa64. While it may be an unlikely config, it would be best to fix it. Tom > > Alveo PCIe FPGA based platforms have a static *shell* partition and a partial > re-configurable *user* partition. The shell partition is automatically loaded from > flash when host is booted and PCIe is enumerated by BIOS. Shell cannot be changed > till the next cold reboot. The shell exposes two PCIe physical functions: > > 1. management physical function > 2. user physical function > > The patch series includes Documentation/xrt.rst which describes Alveo platform, > XRT driver architecture and deployment model in more detail. > > Users compile their high level design in C/C++/OpenCL or RTL into FPGA image using > Vitis https://www.xilinx.com/products/design-tools/vitis/vitis-platform.html > tools. The compiled image is packaged as xclbin which contains partial bitstream > for the user partition and necessary metadata. Users can dynamically swap the image > running on the user partition in order to switch between different workloads by > loading different xclbins. > > XRT DRIVERS FOR XILINX ALVEO > > XRT Linux kernel driver *xmgmt* binds to management physical function of Alveo > platform. The modular driver framework is organized into several platform drivers > which primarily handle the following functionality: > > 1. Loading firmware container also called xsabin at driver attach time > 2. Loading of user compiled xclbin with FPGA Manager integration > 3. Clock scaling of image running on user partition > 4. In-band sensors: temp, voltage, power, etc. > 5. Device reset and rescan > > The platform drivers are packaged into *xrt-lib* helper module with well > defined interfaces. The module provides a pseudo-bus implementation for the > platform drivers. More details on the driver model can be found in > Documentation/xrt.rst. > > User physical function driver is not included in this patch series. > > LIBFDT REQUIREMENT > > XRT driver infrastructure uses Device Tree as a metadata format to discover > HW subsystems in the Alveo PCIe device. The Device Tree schema used by XRT > is documented in Documentation/xrt.rst. Unlike previous V1 and V2 version > of patch series, V3 version does not require export of libfdt symbols. > > TESTING AND VALIDATION > > xmgmt driver can be tested with full XRT open source stack which includes user > space libraries, board utilities and (out of tree) first generation user physical > function driver xocl. XRT open source runtime stack is available at > https://github.com/Xilinx/XRT > > Complete documentation for XRT open source stack including sections on Alveo/XRT > security and platform architecture can be found here: > > https://xilinx.github.io/XRT/master/html/index.html > https://xilinx.github.io/XRT/master/html/security.html > https://xilinx.github.io/XRT/master/html/platforms_partitions.html > > Changes since v2: > - Streamlined the driver framework into *xleaf*, *group* and *xroot* > - Updated documentation to show the driver model with examples > - Addressed kernel test robot errors > - Added a selftest for basic driver framework > - Documented device tree schema > - Removed need to export libfdt symbols > > Changes since v1: > - Updated the driver to use fpga_region and fpga_bridge for FPGA > programming > - Dropped platform drivers not related to PR programming to focus on XRT > core framework > - Updated Documentation/fpga/xrt.rst with information on XRT core framework > - Addressed checkpatch issues > - Dropped xrt- prefix from some header files > > For reference V1 version of patch series can be found here: > > https://lore.kernel.org/lkml/20201217075046.28553-1-sonals@xilinx.com/ > https://lore.kernel.org/lkml/20201217075046.28553-2-sonals@xilinx.com/ > https://lore.kernel.org/lkml/20201217075046.28553-3-sonals@xilinx.com/ > https://lore.kernel.org/lkml/20201217075046.28553-4-sonals@xilinx.com/ > https://lore.kernel.org/lkml/20201217075046.28553-5-sonals@xilinx.com/ > https://lore.kernel.org/lkml/20201217075046.28553-6-sonals@xilinx.com/ > https://lore.kernel.org/lkml/20201217075046.28553-7-sonals@xilinx.com/ > > Lizhi Hou (18): > Documentation: fpga: Add a document describing XRT Alveo drivers > fpga: xrt: driver metadata helper functions > fpga: xrt: xclbin file helper functions > fpga: xrt: xrt-lib platform driver manager > fpga: xrt: group platform driver > fpga: xrt: platform driver infrastructure > fpga: xrt: management physical function driver (root) > fpga: xrt: main platform driver for management function device > fpga: xrt: fpga-mgr and region implementation for xclbin download > fpga: xrt: VSEC platform driver > fpga: xrt: UCS platform driver > fpga: xrt: ICAP platform driver > fpga: xrt: devctl platform driver > fpga: xrt: clock platform driver > fpga: xrt: clock frequence counter platform driver > fpga: xrt: DDR calibration platform driver > fpga: xrt: partition isolation platform driver > fpga: xrt: Kconfig and Makefile updates for XRT drivers > > Documentation/fpga/index.rst | 1 + > Documentation/fpga/xrt.rst | 842 ++++++++++++++++++++++ > MAINTAINERS | 11 + > drivers/Makefile | 1 + > drivers/fpga/Kconfig | 2 + > drivers/fpga/Makefile | 4 + > drivers/fpga/xrt/Kconfig | 8 + > drivers/fpga/xrt/include/events.h | 48 ++ > drivers/fpga/xrt/include/group.h | 27 + > drivers/fpga/xrt/include/metadata.h | 229 ++++++ > drivers/fpga/xrt/include/subdev_id.h | 43 ++ > drivers/fpga/xrt/include/xclbin-helper.h | 52 ++ > drivers/fpga/xrt/include/xleaf.h | 276 +++++++ > drivers/fpga/xrt/include/xleaf/axigate.h | 25 + > drivers/fpga/xrt/include/xleaf/calib.h | 30 + > drivers/fpga/xrt/include/xleaf/clkfreq.h | 23 + > drivers/fpga/xrt/include/xleaf/clock.h | 31 + > drivers/fpga/xrt/include/xleaf/devctl.h | 43 ++ > drivers/fpga/xrt/include/xleaf/icap.h | 29 + > drivers/fpga/xrt/include/xleaf/ucs.h | 24 + > drivers/fpga/xrt/include/xmgmt-main.h | 37 + > drivers/fpga/xrt/include/xroot.h | 114 +++ > drivers/fpga/xrt/lib/Kconfig | 16 + > drivers/fpga/xrt/lib/Makefile | 30 + > drivers/fpga/xrt/lib/cdev.c | 231 ++++++ > drivers/fpga/xrt/lib/group.c | 265 +++++++ > drivers/fpga/xrt/lib/main.c | 274 +++++++ > drivers/fpga/xrt/lib/main.h | 17 + > drivers/fpga/xrt/lib/subdev.c | 871 +++++++++++++++++++++++ > drivers/fpga/xrt/lib/subdev_pool.h | 53 ++ > drivers/fpga/xrt/lib/xclbin.c | 394 ++++++++++ > drivers/fpga/xrt/lib/xleaf/axigate.c | 298 ++++++++ > drivers/fpga/xrt/lib/xleaf/calib.c | 226 ++++++ > drivers/fpga/xrt/lib/xleaf/clkfreq.c | 221 ++++++ > drivers/fpga/xrt/lib/xleaf/clock.c | 648 +++++++++++++++++ > drivers/fpga/xrt/lib/xleaf/devctl.c | 206 ++++++ > drivers/fpga/xrt/lib/xleaf/icap.c | 317 +++++++++ > drivers/fpga/xrt/lib/xleaf/ucs.c | 235 ++++++ > drivers/fpga/xrt/lib/xleaf/vsec.c | 359 ++++++++++ > drivers/fpga/xrt/lib/xroot.c | 598 ++++++++++++++++ > drivers/fpga/xrt/metadata/Kconfig | 12 + > drivers/fpga/xrt/metadata/Makefile | 16 + > drivers/fpga/xrt/metadata/metadata.c | 524 ++++++++++++++ > drivers/fpga/xrt/mgmt/Kconfig | 15 + > drivers/fpga/xrt/mgmt/Makefile | 19 + > drivers/fpga/xrt/mgmt/fmgr-drv.c | 187 +++++ > drivers/fpga/xrt/mgmt/fmgr.h | 28 + > drivers/fpga/xrt/mgmt/main-impl.h | 37 + > drivers/fpga/xrt/mgmt/main-region.c | 471 ++++++++++++ > drivers/fpga/xrt/mgmt/main.c | 693 ++++++++++++++++++ > drivers/fpga/xrt/mgmt/root.c | 342 +++++++++ > include/uapi/linux/xrt/xclbin.h | 408 +++++++++++ > include/uapi/linux/xrt/xmgmt-ioctl.h | 46 ++ > 53 files changed, 9957 insertions(+) > create mode 100644 Documentation/fpga/xrt.rst > create mode 100644 drivers/fpga/xrt/Kconfig > create mode 100644 drivers/fpga/xrt/include/events.h > create mode 100644 drivers/fpga/xrt/include/group.h > create mode 100644 drivers/fpga/xrt/include/metadata.h > create mode 100644 drivers/fpga/xrt/include/subdev_id.h > create mode 100644 drivers/fpga/xrt/include/xclbin-helper.h > create mode 100644 drivers/fpga/xrt/include/xleaf.h > create mode 100644 drivers/fpga/xrt/include/xleaf/axigate.h > create mode 100644 drivers/fpga/xrt/include/xleaf/calib.h > create mode 100644 drivers/fpga/xrt/include/xleaf/clkfreq.h > create mode 100644 drivers/fpga/xrt/include/xleaf/clock.h > create mode 100644 drivers/fpga/xrt/include/xleaf/devctl.h > create mode 100644 drivers/fpga/xrt/include/xleaf/icap.h > create mode 100644 drivers/fpga/xrt/include/xleaf/ucs.h > create mode 100644 drivers/fpga/xrt/include/xmgmt-main.h > create mode 100644 drivers/fpga/xrt/include/xroot.h > create mode 100644 drivers/fpga/xrt/lib/Kconfig > create mode 100644 drivers/fpga/xrt/lib/Makefile > create mode 100644 drivers/fpga/xrt/lib/cdev.c > create mode 100644 drivers/fpga/xrt/lib/group.c > create mode 100644 drivers/fpga/xrt/lib/main.c > create mode 100644 drivers/fpga/xrt/lib/main.h > create mode 100644 drivers/fpga/xrt/lib/subdev.c > create mode 100644 drivers/fpga/xrt/lib/subdev_pool.h > create mode 100644 drivers/fpga/xrt/lib/xclbin.c > create mode 100644 drivers/fpga/xrt/lib/xleaf/axigate.c > create mode 100644 drivers/fpga/xrt/lib/xleaf/calib.c > create mode 100644 drivers/fpga/xrt/lib/xleaf/clkfreq.c > create mode 100644 drivers/fpga/xrt/lib/xleaf/clock.c > create mode 100644 drivers/fpga/xrt/lib/xleaf/devctl.c > create mode 100644 drivers/fpga/xrt/lib/xleaf/icap.c > create mode 100644 drivers/fpga/xrt/lib/xleaf/ucs.c > create mode 100644 drivers/fpga/xrt/lib/xleaf/vsec.c > create mode 100644 drivers/fpga/xrt/lib/xroot.c > create mode 100644 drivers/fpga/xrt/metadata/Kconfig > create mode 100644 drivers/fpga/xrt/metadata/Makefile > create mode 100644 drivers/fpga/xrt/metadata/metadata.c > create mode 100644 drivers/fpga/xrt/mgmt/Kconfig > create mode 100644 drivers/fpga/xrt/mgmt/Makefile > create mode 100644 drivers/fpga/xrt/mgmt/fmgr-drv.c > create mode 100644 drivers/fpga/xrt/mgmt/fmgr.h > create mode 100644 drivers/fpga/xrt/mgmt/main-impl.h > create mode 100644 drivers/fpga/xrt/mgmt/main-region.c > create mode 100644 drivers/fpga/xrt/mgmt/main.c > create mode 100644 drivers/fpga/xrt/mgmt/root.c > create mode 100644 include/uapi/linux/xrt/xclbin.h > create mode 100644 include/uapi/linux/xrt/xmgmt-ioctl.h >
On 02/18/2021 05:52 AM, Tom Rix wrote: > On 2/17/21 10:40 PM, Lizhi Hou wrote: >> Hello, >> >> This is V3 of patch series which adds management physical function driver for Xilinx >> Alveo PCIe accelerator cards, https://www.xilinx.com/products/boards-and-kits/alveo.html >> This driver is part of Xilinx Runtime (XRT) open source stack. >> >> XILINX ALVEO PLATFORM ARCHITECTURE > Thanks for refreshing this patchset. > > It will take me a while to do the full review, so I thought I would give some early feed back. > > It applies to char-misc-next, but will have conflicts with in-flight patches around the MAINTAINERS file. This is not a big deal. > > The checkpatch is much better over v2, the complaints are > > WARNING: added, moved or deleted file(s), does MAINTAINERS need updating? > #21: > new file mode 100644 > > WARNING: From:/Signed-off-by: email address mismatch: 'From: Lizhi Hou <lizhi.hou@xilinx.com>' != 'Signed-off-by: Lizhi Hou <lizhih@xilinx.com>' > > MAINTAINERS warning i believe you address in the last patch. > > In the next revisions, please fix the signoff. > > The test robot is complaining about hppa64. While it may be an unlikely config, it would be best to fix it. Thanks for reviewing. I will fix signoff, hppa64 and arm build issue reported by robot in next revision. > > Tom > >> Alveo PCIe FPGA based platforms have a static *shell* partition and a partial >> re-configurable *user* partition. The shell partition is automatically loaded from >> flash when host is booted and PCIe is enumerated by BIOS. Shell cannot be changed >> till the next cold reboot. The shell exposes two PCIe physical functions: >> >> 1. management physical function >> 2. user physical function >> >> The patch series includes Documentation/xrt.rst which describes Alveo platform, >> XRT driver architecture and deployment model in more detail. >> >> Users compile their high level design in C/C++/OpenCL or RTL into FPGA image using >> Vitis https://www.xilinx.com/products/design-tools/vitis/vitis-platform.html >> tools. The compiled image is packaged as xclbin which contains partial bitstream >> for the user partition and necessary metadata. Users can dynamically swap the image >> running on the user partition in order to switch between different workloads by >> loading different xclbins. >> >> XRT DRIVERS FOR XILINX ALVEO >> >> XRT Linux kernel driver *xmgmt* binds to management physical function of Alveo >> platform. The modular driver framework is organized into several platform drivers >> which primarily handle the following functionality: >> >> 1. Loading firmware container also called xsabin at driver attach time >> 2. Loading of user compiled xclbin with FPGA Manager integration >> 3. Clock scaling of image running on user partition >> 4. In-band sensors: temp, voltage, power, etc. >> 5. Device reset and rescan >> >> The platform drivers are packaged into *xrt-lib* helper module with well >> defined interfaces. The module provides a pseudo-bus implementation for the >> platform drivers. More details on the driver model can be found in >> Documentation/xrt.rst. >> >> User physical function driver is not included in this patch series. >> >> LIBFDT REQUIREMENT >> >> XRT driver infrastructure uses Device Tree as a metadata format to discover >> HW subsystems in the Alveo PCIe device. The Device Tree schema used by XRT >> is documented in Documentation/xrt.rst. Unlike previous V1 and V2 version >> of patch series, V3 version does not require export of libfdt symbols. >> >> TESTING AND VALIDATION >> >> xmgmt driver can be tested with full XRT open source stack which includes user >> space libraries, board utilities and (out of tree) first generation user physical >> function driver xocl. XRT open source runtime stack is available at >> https://github.com/Xilinx/XRT >> >> Complete documentation for XRT open source stack including sections on Alveo/XRT >> security and platform architecture can be found here: >> >> https://xilinx.github.io/XRT/master/html/index.html >> https://xilinx.github.io/XRT/master/html/security.html >> https://xilinx.github.io/XRT/master/html/platforms_partitions.html >> >> Changes since v2: >> - Streamlined the driver framework into *xleaf*, *group* and *xroot* >> - Updated documentation to show the driver model with examples >> - Addressed kernel test robot errors >> - Added a selftest for basic driver framework >> - Documented device tree schema >> - Removed need to export libfdt symbols >> >> Changes since v1: >> - Updated the driver to use fpga_region and fpga_bridge for FPGA >> programming >> - Dropped platform drivers not related to PR programming to focus on XRT >> core framework >> - Updated Documentation/fpga/xrt.rst with information on XRT core framework >> - Addressed checkpatch issues >> - Dropped xrt- prefix from some header files >> >> For reference V1 version of patch series can be found here: >> >> https://lore.kernel.org/lkml/20201217075046.28553-1-sonals@xilinx.com/ >> https://lore.kernel.org/lkml/20201217075046.28553-2-sonals@xilinx.com/ >> https://lore.kernel.org/lkml/20201217075046.28553-3-sonals@xilinx.com/ >> https://lore.kernel.org/lkml/20201217075046.28553-4-sonals@xilinx.com/ >> https://lore.kernel.org/lkml/20201217075046.28553-5-sonals@xilinx.com/ >> https://lore.kernel.org/lkml/20201217075046.28553-6-sonals@xilinx.com/ >> https://lore.kernel.org/lkml/20201217075046.28553-7-sonals@xilinx.com/ >> >> Lizhi Hou (18): >> Documentation: fpga: Add a document describing XRT Alveo drivers >> fpga: xrt: driver metadata helper functions >> fpga: xrt: xclbin file helper functions >> fpga: xrt: xrt-lib platform driver manager >> fpga: xrt: group platform driver >> fpga: xrt: platform driver infrastructure >> fpga: xrt: management physical function driver (root) >> fpga: xrt: main platform driver for management function device >> fpga: xrt: fpga-mgr and region implementation for xclbin download >> fpga: xrt: VSEC platform driver >> fpga: xrt: UCS platform driver >> fpga: xrt: ICAP platform driver >> fpga: xrt: devctl platform driver >> fpga: xrt: clock platform driver >> fpga: xrt: clock frequence counter platform driver >> fpga: xrt: DDR calibration platform driver >> fpga: xrt: partition isolation platform driver >> fpga: xrt: Kconfig and Makefile updates for XRT drivers >> >> Documentation/fpga/index.rst | 1 + >> Documentation/fpga/xrt.rst | 842 ++++++++++++++++++++++ >> MAINTAINERS | 11 + >> drivers/Makefile | 1 + >> drivers/fpga/Kconfig | 2 + >> drivers/fpga/Makefile | 4 + >> drivers/fpga/xrt/Kconfig | 8 + >> drivers/fpga/xrt/include/events.h | 48 ++ >> drivers/fpga/xrt/include/group.h | 27 + >> drivers/fpga/xrt/include/metadata.h | 229 ++++++ >> drivers/fpga/xrt/include/subdev_id.h | 43 ++ >> drivers/fpga/xrt/include/xclbin-helper.h | 52 ++ >> drivers/fpga/xrt/include/xleaf.h | 276 +++++++ >> drivers/fpga/xrt/include/xleaf/axigate.h | 25 + >> drivers/fpga/xrt/include/xleaf/calib.h | 30 + >> drivers/fpga/xrt/include/xleaf/clkfreq.h | 23 + >> drivers/fpga/xrt/include/xleaf/clock.h | 31 + >> drivers/fpga/xrt/include/xleaf/devctl.h | 43 ++ >> drivers/fpga/xrt/include/xleaf/icap.h | 29 + >> drivers/fpga/xrt/include/xleaf/ucs.h | 24 + >> drivers/fpga/xrt/include/xmgmt-main.h | 37 + >> drivers/fpga/xrt/include/xroot.h | 114 +++ >> drivers/fpga/xrt/lib/Kconfig | 16 + >> drivers/fpga/xrt/lib/Makefile | 30 + >> drivers/fpga/xrt/lib/cdev.c | 231 ++++++ >> drivers/fpga/xrt/lib/group.c | 265 +++++++ >> drivers/fpga/xrt/lib/main.c | 274 +++++++ >> drivers/fpga/xrt/lib/main.h | 17 + >> drivers/fpga/xrt/lib/subdev.c | 871 +++++++++++++++++++++++ >> drivers/fpga/xrt/lib/subdev_pool.h | 53 ++ >> drivers/fpga/xrt/lib/xclbin.c | 394 ++++++++++ >> drivers/fpga/xrt/lib/xleaf/axigate.c | 298 ++++++++ >> drivers/fpga/xrt/lib/xleaf/calib.c | 226 ++++++ >> drivers/fpga/xrt/lib/xleaf/clkfreq.c | 221 ++++++ >> drivers/fpga/xrt/lib/xleaf/clock.c | 648 +++++++++++++++++ >> drivers/fpga/xrt/lib/xleaf/devctl.c | 206 ++++++ >> drivers/fpga/xrt/lib/xleaf/icap.c | 317 +++++++++ >> drivers/fpga/xrt/lib/xleaf/ucs.c | 235 ++++++ >> drivers/fpga/xrt/lib/xleaf/vsec.c | 359 ++++++++++ >> drivers/fpga/xrt/lib/xroot.c | 598 ++++++++++++++++ >> drivers/fpga/xrt/metadata/Kconfig | 12 + >> drivers/fpga/xrt/metadata/Makefile | 16 + >> drivers/fpga/xrt/metadata/metadata.c | 524 ++++++++++++++ >> drivers/fpga/xrt/mgmt/Kconfig | 15 + >> drivers/fpga/xrt/mgmt/Makefile | 19 + >> drivers/fpga/xrt/mgmt/fmgr-drv.c | 187 +++++ >> drivers/fpga/xrt/mgmt/fmgr.h | 28 + >> drivers/fpga/xrt/mgmt/main-impl.h | 37 + >> drivers/fpga/xrt/mgmt/main-region.c | 471 ++++++++++++ >> drivers/fpga/xrt/mgmt/main.c | 693 ++++++++++++++++++ >> drivers/fpga/xrt/mgmt/root.c | 342 +++++++++ >> include/uapi/linux/xrt/xclbin.h | 408 +++++++++++ >> include/uapi/linux/xrt/xmgmt-ioctl.h | 46 ++ >> 53 files changed, 9957 insertions(+) >> create mode 100644 Documentation/fpga/xrt.rst >> create mode 100644 drivers/fpga/xrt/Kconfig >> create mode 100644 drivers/fpga/xrt/include/events.h >> create mode 100644 drivers/fpga/xrt/include/group.h >> create mode 100644 drivers/fpga/xrt/include/metadata.h >> create mode 100644 drivers/fpga/xrt/include/subdev_id.h >> create mode 100644 drivers/fpga/xrt/include/xclbin-helper.h >> create mode 100644 drivers/fpga/xrt/include/xleaf.h >> create mode 100644 drivers/fpga/xrt/include/xleaf/axigate.h >> create mode 100644 drivers/fpga/xrt/include/xleaf/calib.h >> create mode 100644 drivers/fpga/xrt/include/xleaf/clkfreq.h >> create mode 100644 drivers/fpga/xrt/include/xleaf/clock.h >> create mode 100644 drivers/fpga/xrt/include/xleaf/devctl.h >> create mode 100644 drivers/fpga/xrt/include/xleaf/icap.h >> create mode 100644 drivers/fpga/xrt/include/xleaf/ucs.h >> create mode 100644 drivers/fpga/xrt/include/xmgmt-main.h >> create mode 100644 drivers/fpga/xrt/include/xroot.h >> create mode 100644 drivers/fpga/xrt/lib/Kconfig >> create mode 100644 drivers/fpga/xrt/lib/Makefile >> create mode 100644 drivers/fpga/xrt/lib/cdev.c >> create mode 100644 drivers/fpga/xrt/lib/group.c >> create mode 100644 drivers/fpga/xrt/lib/main.c >> create mode 100644 drivers/fpga/xrt/lib/main.h >> create mode 100644 drivers/fpga/xrt/lib/subdev.c >> create mode 100644 drivers/fpga/xrt/lib/subdev_pool.h >> create mode 100644 drivers/fpga/xrt/lib/xclbin.c >> create mode 100644 drivers/fpga/xrt/lib/xleaf/axigate.c >> create mode 100644 drivers/fpga/xrt/lib/xleaf/calib.c >> create mode 100644 drivers/fpga/xrt/lib/xleaf/clkfreq.c >> create mode 100644 drivers/fpga/xrt/lib/xleaf/clock.c >> create mode 100644 drivers/fpga/xrt/lib/xleaf/devctl.c >> create mode 100644 drivers/fpga/xrt/lib/xleaf/icap.c >> create mode 100644 drivers/fpga/xrt/lib/xleaf/ucs.c >> create mode 100644 drivers/fpga/xrt/lib/xleaf/vsec.c >> create mode 100644 drivers/fpga/xrt/lib/xroot.c >> create mode 100644 drivers/fpga/xrt/metadata/Kconfig >> create mode 100644 drivers/fpga/xrt/metadata/Makefile >> create mode 100644 drivers/fpga/xrt/metadata/metadata.c >> create mode 100644 drivers/fpga/xrt/mgmt/Kconfig >> create mode 100644 drivers/fpga/xrt/mgmt/Makefile >> create mode 100644 drivers/fpga/xrt/mgmt/fmgr-drv.c >> create mode 100644 drivers/fpga/xrt/mgmt/fmgr.h >> create mode 100644 drivers/fpga/xrt/mgmt/main-impl.h >> create mode 100644 drivers/fpga/xrt/mgmt/main-region.c >> create mode 100644 drivers/fpga/xrt/mgmt/main.c >> create mode 100644 drivers/fpga/xrt/mgmt/root.c >> create mode 100644 include/uapi/linux/xrt/xclbin.h >> create mode 100644 include/uapi/linux/xrt/xmgmt-ioctl.h >>
From the documentation, there are a couple of big questions and a bunch of word smithing. pseudo-bus : do we need a bus ? xrt-lib real platform devices that aren't fpga, do they need to move to another subsystem ? Overall looks good, love the ascii art! On 2/17/21 10:40 PM, Lizhi Hou wrote: > Describe XRT driver architecture and provide basic overview of > Xilinx Alveo platform. > > Signed-off-by: Sonal Santan <sonal.santan@xilinx.com> > Signed-off-by: Max Zhen <max.zhen@xilinx.com> > Signed-off-by: Lizhi Hou <lizhih@xilinx.com> > --- > Documentation/fpga/index.rst | 1 + > Documentation/fpga/xrt.rst | 842 +++++++++++++++++++++++++++++++++++ > 2 files changed, 843 insertions(+) > create mode 100644 Documentation/fpga/xrt.rst > > diff --git a/Documentation/fpga/index.rst b/Documentation/fpga/index.rst > index f80f95667ca2..30134357b70d 100644 > --- a/Documentation/fpga/index.rst > +++ b/Documentation/fpga/index.rst > @@ -8,6 +8,7 @@ fpga > :maxdepth: 1 > > dfl > + xrt > > .. only:: subproject and html > > diff --git a/Documentation/fpga/xrt.rst b/Documentation/fpga/xrt.rst > new file mode 100644 > index 000000000000..9bc2d2785cb9 > --- /dev/null > +++ b/Documentation/fpga/xrt.rst > @@ -0,0 +1,842 @@ > +.. SPDX-License-Identifier: GPL-2.0 > + > +================================== > +XRTV2 Linux Kernel Driver Overview > +================================== > + > +Authors: > + > +* Sonal Santan <sonal.santan@xilinx.com> > +* Max Zhen <max.zhen@xilinx.com> > +* Lizhi Hou <lizhi.hou@xilinx.com> > + > +XRTV2 drivers are second generation `XRT <https://github.com/Xilinx/XRT>`_ > +drivers which support `Alveo <https://www.xilinx.com/products/boards-and-kits/alveo.html>`_ > +PCIe platforms from Xilinx. > + > +XRTV2 drivers support *subsystem* style data driven platforms where driver's where the driver's > +configuration and behavior is determined by meta data provided by the platform > +(in *device tree* format). Primary management physical function (MPF) driver > +is called **xmgmt**. Primary user physical function (UPF) driver is called > +**xuser** and is under development. xrt driver framework and HW subsystem > +drivers are packaged into a library module called **xrt-lib**, which is > +shared by **xmgmt** and **xuser** (under development). The xrt driver framework xuser still under development ? > +implements a pseudo-bus which is used to discover HW subsystems and facilitate A pseudo-bus. It would be good if this was close to what was done for dfl here https://lore.kernel.org/linux-fpga/1605159759-3439-1-git-send-email-yilun.xu@intel.com/ > +inter HW subsystem interaction. > + > +Driver Modules > +============== > + > +xrt-lib.ko > +---------- > + > +Repository of all subsystem drivers and pure software modules that can potentially subsystem drivers drivers in fpga/ should be for managing just the fpganess of the fpga. soft devices ex/ a soft tty should go to their respective subsystem location Are there any in this patchset you think might move ? Maybe we can defer reviewing those now. > +be shared between xmgmt and xuser. All these drivers are structured as Linux > +*platform driver* and are instantiated by xmgmt (or xuser under development) based > +on meta data associated with hardware. The metadata is in the form of device tree with the hardware form of a device tree > +as mentioned before. Each platform driver statically defines a subsystem node > +array by using node name or a string in its ``compatible`` property. And this > +array is eventually translated to IOMEM resources of the platform device. > + > +The xrt-lib core infrastructure provides hooks to platform drivers for device node > +management, user file operations and ioctl callbacks. The core also provides pseudo-bus > +functionality for platform driver registration, discovery and inter platform driver > +ioctl calls. core infrastructure. The interfaces to the infrastructure are not in include/linux/fpga/ Maybe this needs to change. > + > +.. note:: > + See code in ``include/xleaf.h`` > + > + > +xmgmt.ko > +-------- > + > +The xmgmt driver is a PCIe device driver driving MPF found on Xilinx's Alveo > +PCIE device. It consists of one *root* driver, one or more *group* drivers > +and one or more *xleaf* drivers. The root and MPF specific xleaf drivers are > +in xmgmt.ko. The group driver and other xleaf drivers are in xrt-lib.ko. I am not sure if *.ko is correct, these will also be intree. > + > +The instantiation of specific group driver or xleaf driver is completely data of a specific > +driven based on meta data (mostly in device tree format) found through VSEC mostly ? what is the deviation from device tree ? > +capability and inside firmware files, such as platform xsabin or user xclbin file. > +The root driver manages life cycle of multiple group drivers, which, in turn, the life cycle > +manages multiple xleaf drivers. This allows a single set of driver code to support set of drivers drop 'code' > +all kinds of subsystems exposed by different shells. The difference among all > +these subsystems will be handled in xleaf drivers with root and group drivers > +being part of the infrastructure and provide common services for all leaves > +found on all platforms. > + > +The driver object model looks like the following:: > + > + +-----------+ > + | xroot | > + +-----+-----+ > + | > + +-----------+-----------+ > + | | > + v v > + +-----------+ +-----------+ > + | group | ... | group | > + +-----+-----+ +------+----+ > + | | > + | | > + +-----+----+ +-----+----+ > + | | | | > + v v v v > + +-------+ +-------+ +-------+ +-------+ > + | xleaf |..| xleaf | | xleaf |..| xleaf | > + +-------+ +-------+ +-------+ +-------+ > + > +As an example for Xilinx Alveo U50 before user xclbin download, the tree > +looks like the following:: > + > + +-----------+ > + | xmgmt | > + +-----+-----+ > + | > + +-------------------------+--------------------+ > + | | | > + v v v > + +--------+ +--------+ +--------+ > + | group0 | | group1 | | group2 | > + +----+---+ +----+---+ +---+----+ > + | | | > + | | | > + +-----+-----+ +----+-----+---+ +-----+-----+----+--------+ > + | | | | | | | | | > + v v | v v | v v | > + +------------+ +------+ | +------+ +------+ | +------+ +-----------+ | > + | xmgmt_main | | VSEC | | | GPIO | | QSPI | | | CMC | | AXI-GATE0 | | > + +------------+ +------+ | +------+ +------+ | +------+ +-----------+ | > + | +---------+ | +------+ +-----------+ | > + +>| MAILBOX | +->| ICAP | | AXI-GATE1 |<+ > + +---------+ | +------+ +-----------+ > + | +-------+ > + +->| CALIB | > + +-------+ > + Nice ascii art! > +After an xclbin is download, group3 will be added and the tree looks like the > +following:: > + > + +-----------+ > + | xmgmt | > + +-----+-----+ > + | > + +-------------------------+--------------------+-----------------+ > + | | | | > + v v v | > + +--------+ +--------+ +--------+ | > + | group0 | | group1 | | group2 | | > + +----+---+ +----+---+ +---+----+ | > + | | | | > + | | | | > + +-----+-----+ +-----+-----+---+ +-----+-----+----+--------+ | > + | | | | | | | | | | > + v v | v v | v v | | > + +------------+ +------+ | +------+ +------+ | +------+ +-----------+ | | > + | xmgmt_main | | VSEC | | | GPIO | | QSPI | | | CMC | | AXI-GATE0 | | | > + +------------+ +------+ | +------+ +------+ | +------+ +-----------+ | | > + | +---------+ | +------+ +-----------+ | | > + +>| MAILBOX | +->| ICAP | | AXI-GATE1 |<+ | > + +---------+ | +------+ +-----------+ | > + | +-------+ | > + +->| CALIB | | > + +-------+ | > + +---+----+ | > + | group3 |<--------------------------------------------+ > + +--------+ > + | > + | > + +-------+--------+---+--+--------+------+-------+ > + | | | | | | | > + v | v | v | v > + +--------+ | +--------+ | +--------+ | +-----+ > + | CLOCK0 | | | CLOCK1 | | | CLOCK2 | | | UCS | > + +--------+ v +--------+ v +--------+ v +-----+ > + +-------------+ +-------------+ +-------------+ > + | CLOCK-FREQ0 | | CLOCK-FREQ1 | | CLOCK-FREQ2 | > + +-------------+ +-------------+ +-------------+ > + > + > +xmgmt-root > +^^^^^^^^^^ > + > +The xmgmt-root driver is a PCIe device driver attached to MPF. It's part of the > +infrastructure of the MPF driver and resides in xmgmt.ko. This driver > + > +* manages one or more group drivers > +* provides access to functionalities that requires pci_dev, such as PCIE config > + space access, to other xleaf drivers through root calls > +* together with group driver, facilities event callbacks for other xleaf drivers > +* together with group driver, facilities inter-leaf driver calls for other xleaf Maybe drop 'together with group driver' > + drivers > + > +When root driver starts, it will explicitly create an initial group instance, > +which contains xleaf drivers that will trigger the creation of other group > +instances. The root driver will wait for all group and leaves to be created > +before it returns from it's probe routine and claim success of the > +initialization of the entire xmgmt driver. What happens if there a failure in one leaf ? Does the whole board go down ? > + > +.. note:: > + See code in ``lib/xroot.c`` and ``mgmt/root.c`` > + > + > +group > +^^^^^ > + > +The group driver is a platform device driver whose life cycle is managed by Maybe call this a 'pseudo device' > +root and does not have real IO mem or IRQ resources. It's part of the > +infrastructure of the MPF driver and resides in xrt-lib.ko. This driver > + > +* manages one or more xleaf drivers so that multiple leaves can be managed as a > + group can drop 'so that multiple leaves can be managed as a group' to me, this is the same as 'one or more' > +* provides access to root from leaves, so that root calls, event notifications > + and inter-leaf calls can happen > + > +In xmgmt, an initial group driver instance will be created by root, which by the root > +contains leaves that will trigger group instances to be created to manage > +groups of leaves found on different partitions on hardware, such as VSEC, Shell, > +and User. > + > +Every *fpga_region* has a group object associated with it. The group is > +created when xclbin image is loaded on the fpga_region. The existing group > +is destroyed when a new xclbin image is loaded. The fpga_region persists > +across xclbin downloads. The connection of a 'group' node to a fpga region region is fairly important, maybe move this section earlier. 'group' as an fpganess thing would be kept in fpga/ subsystem. > + > +.. note:: > + See code in ``lib/group.c`` > + > + > +xleaf > +^^^^^ > + > +The xleaf driver is a platform device driver whose life cycle is managed by > +a group driver and may or may not have real IO mem or IRQ resources. They > +are the real meat of xmgmt and contains platform specific code to Shell and > +User found on a MPF. > + Maybe a split is pseudo device leaves, those without real IO mem, stay in fpga/ others go ? > +A xleaf driver may not have real hardware resources when it merely acts as a > +driver that manages certain in-memory states for xmgmt. These in-memory states > +could be shared by multiple other leaves. > + This implies locking and some message passing. > +Leaf drivers assigned to specific hardware resources drive specific subsystem in drive a specific > +the device. To manipulate the subsystem or carry out a task, a xleaf driver may > +ask help from root via root calls and/or from other leaves via inter-leaf calls. > + > +A xleaf can also broadcast events through infrastructure code for other leaves > +to process. It can also receive event notification from infrastructure about > +certain events, such as post-creation or pre-exit of a particular xleaf. I would like to see some examples of how the inter node communications work. > + > +.. note:: > + See code in ``lib/xleaf/*.c`` > + > + > +FPGA Manager Interaction > +======================== > + > +fpga_manager > +------------ > + > +An instance of fpga_manager is created by xmgmt_main and is used for xclbin for the xclbin > +image download. fpga_manager requires the full xclbin image before it can > +start programming the FPGA configuration engine via ICAP platform driver. via the ICAP what is ICAP ? > + > +fpga_region > +----------- > + > +For every interface exposed by currently loaded xclbin/xsabin in the *parent* by the currently > +fpga_region a new instance of fpga_region is created like a *child* region. fpga_region, > +The device tree of the *parent* fpga_region defines the > +resources for a new instance of fpga_bridge which isolates the parent from and isolates > +child fpga_region. This new instance of fpga_bridge will be used when a > +xclbin image is loaded on the child fpga_region. After the xclbin image is > +downloaded to the fpga_region, an instance of group is created for the > +fpga_region using the device tree obtained as part of xclbin. If this device of the xclbin > +tree defines any child interfaces then it can trigger the creation of interfaces, then > +fpga_bridge and fpga_region for the next region in the chain. a fpga_bridge and a fpga_region > + > +fpga_bridge > +----------- > + > +Like fpga_region, matching fpga_bridge is also created by walking the device Like the fpga_region, a matchin > +tree of the parent group. > + > +Driver Interfaces > +================= > + > +xmgmt Driver Ioctls > +------------------- > + > +Ioctls exposed by xmgmt driver to user space are enumerated in the following > +table: > + > +== ===================== ============================ ========================== > +# Functionality ioctl request code data format > +== ===================== ============================ ========================== > +1 FPGA image download XMGMT_IOCICAPDOWNLOAD_AXLF xmgmt_ioc_bitstream_axlf > +== ===================== ============================ ========================== This data format is described below, maybe swap this section with that so folks will know what xmgmnt_ioc_bitstream_axlf is before this section. > + > +User xclbin can be downloaded by using xbmgmt tool from XRT open source suite. See A user xclbin using the xbmgmt from the XRT > +example usage below:: > + > + xbmgmt partition --program --path /lib/firmware/xilinx/862c7020a250293e32036f19956669e5/test/verify.xclbin --force > + > +xmgmt Driver Sysfs > +------------------ > + > +xmgmt driver exposes a rich set of sysfs interfaces. Subsystem platform > +drivers export sysfs node for every platform instance. > + > +Every partition also exports its UUIDs. See below for examples:: > + > + /sys/bus/pci/devices/0000:06:00.0/xmgmt_main.0/interface_uuids > + /sys/bus/pci/devices/0000:06:00.0/xmgmt_main.0/logic_uuids > + > + > +hwmon > +----- > + > +xmgmt driver exposes standard hwmon interface to report voltage, current, > +temperature, power, etc. These can easily be viewed using *sensors* command > +line utility. > + > +Alveo Platform Overview > +======================= > + > +Alveo platforms are architected as two physical FPGA partitions: *Shell* and > +*User*. The Shell provides basic infrastructure for the Alveo platform like > +PCIe connectivity, board management, Dynamic Function Exchange (DFX), sensors, > +clocking, reset, and security. User partition contains user compiled FPGA the user compiled > +binary which is loaded by a process called DFX also known as partial > +reconfiguration. > + > +Physical partitions require strict HW compatibility with each other for DFX to > +work properly. swap order For DFX to work properly physical partitions .. > Every physical partition has two interface UUIDs: *parent* UUID > +and *child* UUID. For simple single stage platforms, Shell → User forms parent > +child relationship. For complex two stage platforms, Base → Shell → User forms > +the parent child relationship chain. this bit is confusing. is this related to uuid? > + > +.. note:: > + Partition compatibility matching is key design component of Alveo platforms > + and XRT. Partitions have child and parent relationship. A loaded partition have a child > + exposes child partition UUID to advertise its compatibility requirement for the child's can drop 'for child partition' > + child partition. When loading a child partition the xmgmt management driver When loading a child partition, > + matches parent UUID of the child partition against child UUID exported by > + the parent. Parent and child partition UUIDs are stored in the *xclbin* > + (for user) or *xsabin* (for base and shell). this is confusing, is this part of the file image format ? Maybe save/move till the image layout. > Except for root UUID, VSEC, > + hardware itself does not know about UUIDs. UUIDs are stored in xsabin and > + xclbin. This is confusing too, not sure how to untangle. > + > + > +The physical partitions and their loading is illustrated below:: > + > + SHELL USER > + +-----------+ +-------------------+ > + | | | | > + | VSEC UUID | CHILD PARENT | LOGIC UUID | > + | o------->|<--------o | > + | | UUID UUID | | > + +-----+-----+ +--------+----------+ > + | | > + . . > + | | > + +---+---+ +------+--------+ > + | POR | | USER COMPILED | > + | FLASH | | XCLBIN | > + +-------+ +---------------+ > + > + > +Loading Sequence > +---------------- > + > +The Shell partition is loaded from flash at system boot time. It establishes the > +PCIe link and exposes two physical functions to the BIOS. After OS boot, xmgmt the OS boots, the xmgmt > +driver attaches to PCIe physical function 0 exposed by the Shell and then looks > +for VSEC in PCIe extended configuration space. Using VSEC it determines the logic the PCIe The driver uses VSEC to determine the UUID of Shell. The UUID is also used to load a matching ... > +UUID of Shell and uses the UUID to load matching *xsabin* file from Linux firmware > +directory. The xsabin file contains metadata to discover peripherals that are part > +of Shell and firmware(s) for any embedded soft processors in Shell. the firmware needed for any ... > + > +The Shell exports child interface UUID which is used for compatibility check when export a child for a compatibility check > +loading user compiled xclbin over the User partition as part of DFX. When a user > +requests loading of a specific xclbin the xmgmt management driver reads the parent xclbin, the > +interface UUID specified in the xclbin and matches it with child interface UUID > +exported by Shell to determine if xclbin is compatible with the Shell. If match > +fails loading of xclbin is denied. > + > +xclbin loading is requested using ICAP_DOWNLOAD_AXLF ioctl command. When loading > +xclbin, xmgmt driver performs the following *logical* operations: > + > +1. Copy xclbin from user to kernel memory > +2. Sanity check the xclbin contents > +3. Isolate the User partition > +4. Download the bitstream using the FPGA config engine (ICAP) > +5. De-isolate the User partition > +6. Program the clocks (ClockWiz) driving the User partition maybe drop '(ClockWiz)' > +7. Wait for memory controller (MIG) calibration for the > +8. Return the loading status back to the caller > + > +`Platform Loading Overview <https://xilinx.github.io/XRT/master/html/platforms_partitions.html>`_ > +provides more detailed information on platform loading. > + the link works. > + > +xsabin > +------ > + > +Each Alveo platform comes packaged with its own xsabin. The xsabin is trusted is a trusted > +component of the platform. For format details refer to :ref:`xsabin_xclbin_container_format` > +below. xsabin contains basic information like UUIDs, platform name and metadata in the > +form of device tree. See :ref:`device_tree_usage` below for details and example. of a device > + > +xclbin > +------ > + > +xclbin is compiled by end user using > +`Vitis <https://www.xilinx.com/products/design-tools/vitis/vitis-platform.html>`_ this link works, seems reasonable landing > +tool set from Xilinx. The xclbin contains sections describing user compiled > +acceleration engines/kernels, memory subsystems, clocking information etc. It also > +contains bitstream for the user partition, UUIDs, platform name, etc. xclbin uses bitstreams > +the same container format as xsabin which is described below. > + > + > +.. _xsabin_xclbin_container_format: > + > +xsabin/xclbin Container Format > +------------------------------ > + > +xclbin/xsabin is ELF-like binary container format. It is structured as series of > +sections. There is a file header followed by several section headers which is > +followed by sections. A section header points to an actual section. There is an > +optional signature at the end. The format is defined by header file ``xclbin.h``. > +The following figure illustrates a typical xclbin:: > + > + > + +---------------------+ > + | | > + | HEADER | > + +---------------------+ > + | SECTION HEADER | > + | | > + +---------------------+ > + | ... | > + | | > + +---------------------+ > + | SECTION HEADER | > + | | > + +---------------------+ > + | SECTION | > + | | > + +---------------------+ > + | ... | > + | | > + +---------------------+ > + | SECTION | > + | | > + +---------------------+ > + | SIGNATURE | > + | (OPTIONAL) | > + +---------------------+ > + > + > +xclbin/xsabin files can be packaged, un-packaged and inspected using XRT utility > +called **xclbinutil**. xclbinutil is part of XRT open source software stack. The > +source code for xclbinutil can be found at > +https://github.com/Xilinx/XRT/tree/master/src/runtime_src/tools/xclbinutil > + Works, but maybe the location of a manpage or doc would be better. > +For example to enumerate the contents of a xclbin/xsabin use the *--info* switch > +as shown below:: > + > + > + xclbinutil --info --input /opt/xilinx/firmware/u50/gen3x16-xdma/blp/test/bandwidth.xclbin > + xclbinutil --info --input /lib/firmware/xilinx/862c7020a250293e32036f19956669e5/partition.xsabin > + > + > +.. _device_tree_usage: > + > +Device Tree Usage > +----------------- > + > +As mentioned previously xsabin stores metadata which advertise HW subsystems present > +in a partition. The metadata is stored in device tree format with well defined schema. > +XRT management driver uses this information to bind *platform drivers* to the subsystem > +instantiations. The platform drivers are found in **xrt-lib.ko** kernel module defined > +later. > + > +Logic UUID > +^^^^^^^^^^ > +A partition is identified uniquely through ``logic_uuid`` property:: > + > + /dts-v1/; > + / { > + logic_uuid = "0123456789abcdef0123456789abcdef"; > + ... > + } > + > +Schema Version > +^^^^^^^^^^^^^^ > +Schema version is defined through ``schema_version`` node. And it contains ``major`` > +and ``minor`` properties as below:: > + > + /dts-v1/; > + / { > + schema_version { > + major = <0x01>; > + minor = <0x00>; > + }; > + ... > + } > + > +Partition UUIDs > +^^^^^^^^^^^^^^^ > +As said earlier, each partition may have parent and child UUIDs. These UUIDs are > +defined by ``interfaces`` node and ``interface_uuid`` property:: > + > + /dts-v1/; > + / { > + interfaces { > + @0 { > + interface_uuid = "0123456789abcdef0123456789abcdef"; > + }; > + @1 { > + interface_uuid = "fedcba9876543210fedcba9876543210"; > + }; > + ... > + }; > + ... > + } > + > + > +Subsystem Instantiations > +^^^^^^^^^^^^^^^^^^^^^^^^ > +Subsystem instantiations are captured as children of ``addressable_endpoints`` > +node:: > + > + /dts-v1/; > + / { > + addressable_endpoints { > + abc { > + ... > + }; > + def { > + ... > + }; > + ... > + } > + } > + > +Subnode 'abc' and 'def' are the name of subsystem nodes > + > +Subsystem Node > +^^^^^^^^^^^^^^ > +Each subsystem node and its properties define a hardware instance:: > + > + > + addressable_endpoints { > + abc { > + reg = <0xa 0xb> > + pcie_physical_function = <0x0>; > + pcie_bar_mapping = <0x2>; > + compatible = "abc def"; > + firmware { > + firmware_product_name = "abc" > + firmware_branch_name = "def" > + firmware_version_major = <1> > + firmware_version_minor = <2> > + }; > + } > + ... > + } > + > +:reg: > + Property defines address range. '<0xa 0xb>' is BAR offset and length pair, both > + are 64-bit integer. > +:pcie_physical_function: > + Property specifies which PCIe physical function the subsystem node resides. > +:pcie_bar_mapping: > + Property specifies which PCIe BAR the subsystem node resides. '<0x2>' is BAR > + index and it is 0 if this property is not defined. > +:compatible: > + Property is a list of strings. The first string in the list specifies the exact > + subsystem node. The following strings represent other devices that the device > + is compatible with. > +:firmware: > + Subnode defines the firmware required by this subsystem node. > + > +Alveo U50 Platform Example > +^^^^^^^^^^^^^^^^^^^^^^^^^^ > +:: > + > + /dts-v1/; > + > + /{ > + logic_uuid = "f465b0a3ae8c64f619bc150384ace69b"; > + > + schema_version { > + major = <0x01>; > + minor = <0x00>; > + }; > + > + interfaces { > + > + @0 { > + interface_uuid = "862c7020a250293e32036f19956669e5"; > + }; > + }; > + > + addressable_endpoints { > + > + ep_blp_rom_00 { > + reg = <0x00 0x1f04000 0x00 0x1000>; > + pcie_physical_function = <0x00>; > + compatible = "xilinx.com,reg_abs-axi_bram_ctrl-1.0\0axi_bram_ctrl"; > + }; > + > + ep_card_flash_program_00 { > + reg = <0x00 0x1f06000 0x00 0x1000>; > + pcie_physical_function = <0x00>; > + compatible = "xilinx.com,reg_abs-axi_quad_spi-1.0\0axi_quad_spi"; > + interrupts = <0x03 0x03>; > + }; > + > + ep_cmc_firmware_mem_00 { > + reg = <0x00 0x1e20000 0x00 0x20000>; > + pcie_physical_function = <0x00>; > + compatible = "xilinx.com,reg_abs-axi_bram_ctrl-1.0\0axi_bram_ctrl"; > + > + firmware { > + firmware_product_name = "cmc"; > + firmware_branch_name = "u50"; > + firmware_version_major = <0x01>; > + firmware_version_minor = <0x00>; > + }; > + }; > + > + ep_cmc_intc_00 { > + reg = <0x00 0x1e03000 0x00 0x1000>; > + pcie_physical_function = <0x00>; > + compatible = "xilinx.com,reg_abs-axi_intc-1.0\0axi_intc"; > + interrupts = <0x04 0x04>; > + }; > + > + ep_cmc_mutex_00 { > + reg = <0x00 0x1e02000 0x00 0x1000>; > + pcie_physical_function = <0x00>; > + compatible = "xilinx.com,reg_abs-axi_gpio-1.0\0axi_gpio"; > + }; > + > + ep_cmc_regmap_00 { > + reg = <0x00 0x1e08000 0x00 0x2000>; > + pcie_physical_function = <0x00>; > + compatible = "xilinx.com,reg_abs-axi_bram_ctrl-1.0\0axi_bram_ctrl"; > + > + firmware { > + firmware_product_name = "sc-fw"; > + firmware_branch_name = "u50"; > + firmware_version_major = <0x05>; > + }; > + }; > + > + ep_cmc_reset_00 { > + reg = <0x00 0x1e01000 0x00 0x1000>; > + pcie_physical_function = <0x00>; > + compatible = "xilinx.com,reg_abs-axi_gpio-1.0\0axi_gpio"; > + }; > + > + ep_ddr_mem_calib_00 { > + reg = <0x00 0x63000 0x00 0x1000>; > + pcie_physical_function = <0x00>; > + compatible = "xilinx.com,reg_abs-axi_gpio-1.0\0axi_gpio"; > + }; > + > + ep_debug_bscan_mgmt_00 { > + reg = <0x00 0x1e90000 0x00 0x10000>; > + pcie_physical_function = <0x00>; > + compatible = "xilinx.com,reg_abs-debug_bridge-1.0\0debug_bridge"; > + }; > + > + ep_ert_base_address_00 { > + reg = <0x00 0x21000 0x00 0x1000>; > + pcie_physical_function = <0x00>; > + compatible = "xilinx.com,reg_abs-axi_gpio-1.0\0axi_gpio"; > + }; > + > + ep_ert_command_queue_mgmt_00 { > + reg = <0x00 0x40000 0x00 0x10000>; > + pcie_physical_function = <0x00>; > + compatible = "xilinx.com,reg_abs-ert_command_queue-1.0\0ert_command_queue"; > + }; > + > + ep_ert_command_queue_user_00 { > + reg = <0x00 0x40000 0x00 0x10000>; > + pcie_physical_function = <0x01>; > + compatible = "xilinx.com,reg_abs-ert_command_queue-1.0\0ert_command_queue"; > + }; > + > + ep_ert_firmware_mem_00 { > + reg = <0x00 0x30000 0x00 0x8000>; > + pcie_physical_function = <0x00>; > + compatible = "xilinx.com,reg_abs-axi_bram_ctrl-1.0\0axi_bram_ctrl"; > + > + firmware { > + firmware_product_name = "ert"; > + firmware_branch_name = "v20"; > + firmware_version_major = <0x01>; > + }; > + }; > + > + ep_ert_intc_00 { > + reg = <0x00 0x23000 0x00 0x1000>; > + pcie_physical_function = <0x00>; > + compatible = "xilinx.com,reg_abs-axi_intc-1.0\0axi_intc"; > + interrupts = <0x05 0x05>; > + }; > + > + ep_ert_reset_00 { > + reg = <0x00 0x22000 0x00 0x1000>; > + pcie_physical_function = <0x00>; > + compatible = "xilinx.com,reg_abs-axi_gpio-1.0\0axi_gpio"; > + }; > + > + ep_ert_sched_00 { > + reg = <0x00 0x50000 0x00 0x1000>; > + pcie_physical_function = <0x01>; > + compatible = "xilinx.com,reg_abs-ert_sched-1.0\0ert_sched"; > + interrupts = <0x09 0x0c>; > + }; > + > + ep_fpga_configuration_00 { > + reg = <0x00 0x1e88000 0x00 0x8000>; > + pcie_physical_function = <0x00>; > + compatible = "xilinx.com,reg_abs-axi_hwicap-1.0\0axi_hwicap"; > + interrupts = <0x02 0x02>; > + }; > + > + ep_icap_reset_00 { > + reg = <0x00 0x1f07000 0x00 0x1000>; > + pcie_physical_function = <0x00>; > + compatible = "xilinx.com,reg_abs-axi_gpio-1.0\0axi_gpio"; > + }; > + > + ep_msix_00 { > + reg = <0x00 0x00 0x00 0x20000>; > + pcie_physical_function = <0x00>; > + compatible = "xilinx.com,reg_abs-msix-1.0\0msix"; > + pcie_bar_mapping = <0x02>; > + }; > + > + ep_pcie_link_mon_00 { > + reg = <0x00 0x1f05000 0x00 0x1000>; > + pcie_physical_function = <0x00>; > + compatible = "xilinx.com,reg_abs-axi_gpio-1.0\0axi_gpio"; > + }; > + > + ep_pr_isolate_plp_00 { > + reg = <0x00 0x1f01000 0x00 0x1000>; > + pcie_physical_function = <0x00>; > + compatible = "xilinx.com,reg_abs-axi_gpio-1.0\0axi_gpio"; > + }; > + > + ep_pr_isolate_ulp_00 { > + reg = <0x00 0x1000 0x00 0x1000>; > + pcie_physical_function = <0x00>; > + compatible = "xilinx.com,reg_abs-axi_gpio-1.0\0axi_gpio"; > + }; > + > + ep_uuid_rom_00 { > + reg = <0x00 0x64000 0x00 0x1000>; > + pcie_physical_function = <0x00>; > + compatible = "xilinx.com,reg_abs-axi_bram_ctrl-1.0\0axi_bram_ctrl"; > + }; > + > + ep_xdma_00 { > + reg = <0x00 0x00 0x00 0x10000>; > + pcie_physical_function = <0x01>; > + compatible = "xilinx.com,reg_abs-xdma-1.0\0xdma"; > + pcie_bar_mapping = <0x02>; > + }; > + }; > + > + } > + > + > + > +Deployment Models > +================= > + > +Baremetal > +--------- > + > +In bare-metal deployments both MPF and UPF are visible and accessible. xmgmt In bare-meta deployments, > +driver binds to MPF. xmgmt driver operations are privileged and available to > +system administrator. The full stack is illustrated below:: > + > + HOST > + > + [XMGMT] [XUSER] > + | | > + | | > + +-----+ +-----+ > + | MPF | | UPF | > + | | | | > + | PF0 | | PF1 | > + +--+--+ +--+--+ > + ......... ^................. ^.......... > + | | > + | PCIe DEVICE | > + | | > + +--+------------------+--+ > + | SHELL | > + | | > + +------------------------+ > + | USER | > + | | > + | | > + | | > + | | > + +------------------------+ > + > + > + > +Virtualized > +----------- > + > +In virtualized deployments privileged MPF is assigned to host but unprivileged In virtualized deployments, the > +UPF is assigned to guest VM via PCIe pass-through. xmgmt driver in host binds in the host > +to MPF. xmgmt driver operations are privileged and only accessible by hosting to the MPF > +service provider. The full stack is illustrated below:: > + > + > + ............. > + HOST . VM . > + . . > + [XMGMT] . [XUSER] . > + | . | . > + | . | . > + +-----+ . +-----+ . > + | MPF | . | UPF | . > + | | . | | . > + | PF0 | . | PF1 | . > + +--+--+ . +--+--+ . > + ......... ^................. ^.......... > + | | > + | PCIe DEVICE | > + | | > + +--+------------------+--+ > + | SHELL | > + | | > + +------------------------+ > + | USER | > + | | > + | | > + | | > + | | > + +------------------------+ > + > + > + > + > + > +Platform Security Considerations > +================================ > + > +`Security of Alveo Platform <https://xilinx.github.io/XRT/master/html/security.html>`_ > +discusses the deployment options and security implications in great detail. This link works and looks great. Tom
As I am looking through the files, I have this comment. fpga/ is currently a single directory, while files could be organized in subdirectories like dfl/pci.c instead have the possible subdir name as a prefix to the filename. dfl-pci.c For consistency, xrt/metadata/metadata.c should be xrt-metadata.c Likewise the build infra needs to integrated within the existing files fpga/Kconfig,Makefile This is a bigish refactor, so let's get a second opinion. Moritz ? On 2/17/21 10:40 PM, Lizhi Hou wrote: > Update fpga Kconfig/Makefile and add Kconfig/Makefile for new drivers. Expand the comment, there are several new configs that could use an explanation > > Signed-off-by: Sonal Santan <sonal.santan@xilinx.com> > Signed-off-by: Max Zhen <max.zhen@xilinx.com> > Signed-off-by: Lizhi Hou <lizhih@xilinx.com> > --- > MAINTAINERS | 11 +++++++++++ > drivers/Makefile | 1 + > drivers/fpga/Kconfig | 2 ++ > drivers/fpga/Makefile | 4 ++++ > drivers/fpga/xrt/Kconfig | 8 ++++++++ > drivers/fpga/xrt/lib/Kconfig | 16 ++++++++++++++++ > drivers/fpga/xrt/lib/Makefile | 30 ++++++++++++++++++++++++++++++ > drivers/fpga/xrt/metadata/Kconfig | 12 ++++++++++++ > drivers/fpga/xrt/metadata/Makefile | 16 ++++++++++++++++ > drivers/fpga/xrt/mgmt/Kconfig | 15 +++++++++++++++ > drivers/fpga/xrt/mgmt/Makefile | 19 +++++++++++++++++++ > 11 files changed, 134 insertions(+) > create mode 100644 drivers/fpga/xrt/Kconfig > create mode 100644 drivers/fpga/xrt/lib/Kconfig > create mode 100644 drivers/fpga/xrt/lib/Makefile > create mode 100644 drivers/fpga/xrt/metadata/Kconfig > create mode 100644 drivers/fpga/xrt/metadata/Makefile > create mode 100644 drivers/fpga/xrt/mgmt/Kconfig > create mode 100644 drivers/fpga/xrt/mgmt/Makefile > > diff --git a/MAINTAINERS b/MAINTAINERS > index d3e847f7f3dc..e6e147c2454c 100644 > --- a/MAINTAINERS > +++ b/MAINTAINERS > @@ -6973,6 +6973,17 @@ F: Documentation/fpga/ > F: drivers/fpga/ > F: include/linux/fpga/ > > +FPGA XRT DRIVERS > +M: Lizhi Hou <lizhi.hou@xilinx.com> > +R: Max Zhen <max.zhen@xilinx.com> > +R: Sonal Santan <sonal.santan@xilinx.com> > +L: linux-fpga@vger.kernel.org > +S: Maintained > +W: https://github.com/Xilinx/XRT > +F: Documentation/fpga/xrt.rst > +F: drivers/fpga/xrt/ > +F: include/uapi/linux/xrt/ > + > FPU EMULATOR > M: Bill Metzenthen <billm@melbpc.org.au> > S: Maintained > diff --git a/drivers/Makefile b/drivers/Makefile > index fd11b9ac4cc3..e03912af8e48 100644 > --- a/drivers/Makefile > +++ b/drivers/Makefile > @@ -178,6 +178,7 @@ obj-$(CONFIG_STM) += hwtracing/stm/ > obj-$(CONFIG_ANDROID) += android/ > obj-$(CONFIG_NVMEM) += nvmem/ > obj-$(CONFIG_FPGA) += fpga/ > +obj-y += fpga/xrt/metadata/ This is wrong. Move metadata building to fpga/ Makefile and pick an appropriate config, not just 'obj-y' > obj-$(CONFIG_FSI) += fsi/ > obj-$(CONFIG_TEE) += tee/ > obj-$(CONFIG_MULTIPLEXER) += mux/ > diff --git a/drivers/fpga/Kconfig b/drivers/fpga/Kconfig > index 5645226ca3ce..aeca635b1f25 100644 > --- a/drivers/fpga/Kconfig > +++ b/drivers/fpga/Kconfig > @@ -216,4 +216,6 @@ config FPGA_MGR_ZYNQMP_FPGA > to configure the programmable logic(PL) through PS > on ZynqMP SoC. > > +source "drivers/fpga/xrt/Kconfig" > + > endif # FPGA > diff --git a/drivers/fpga/Makefile b/drivers/fpga/Makefile > index d8e21dfc6778..2b4453ff7c52 100644 > --- a/drivers/fpga/Makefile > +++ b/drivers/fpga/Makefile > @@ -46,3 +46,7 @@ dfl-afu-objs += dfl-afu-error.o > > # Drivers for FPGAs which implement DFL > obj-$(CONFIG_FPGA_DFL_PCI) += dfl-pci.o > + > +# XRT drivers for Alveo > +obj-$(CONFIG_FPGA_XRT_LIB) += xrt/lib/ > +obj-$(CONFIG_FPGA_XRT_XMGMT) += xrt/mgmt/ I don't see how mgmnt would work without lib. If that is so these configs could collapse to CONFIG_FPGA_XRT > diff --git a/drivers/fpga/xrt/Kconfig b/drivers/fpga/xrt/Kconfig > new file mode 100644 > index 000000000000..0e2c59589ddd > --- /dev/null > +++ b/drivers/fpga/xrt/Kconfig > @@ -0,0 +1,8 @@ > +# SPDX-License-Identifier: GPL-2.0-only > +# > +# Xilinx Alveo FPGA device configuration > +# > + > +source "drivers/fpga/xrt/metadata/Kconfig" > +source "drivers/fpga/xrt/lib/Kconfig" > +source "drivers/fpga/xrt/mgmt/Kconfig" > diff --git a/drivers/fpga/xrt/lib/Kconfig b/drivers/fpga/xrt/lib/Kconfig > new file mode 100644 > index 000000000000..eed5cb73f5e2 > --- /dev/null > +++ b/drivers/fpga/xrt/lib/Kconfig > @@ -0,0 +1,16 @@ > +# SPDX-License-Identifier: GPL-2.0-only > +# > +# XRT Alveo FPGA device configuration > +# > + > +config FPGA_XRT_LIB > + tristate "XRT Alveo Driver Library" > + depends on HWMON && PCI && HAS_IOMEM > + select FPGA_XRT_METADATA > + help > + Select this option to enable Xilinx XRT Alveo driver library. This > + library is core infrastructure of XRT Alveo FPGA drivers which > + provides functions for working with device nodes, iteration and > + lookup of platform devices, common interfaces for platform devices, > + plumbing of function call and ioctls between platform devices and > + parent partitions. > diff --git a/drivers/fpga/xrt/lib/Makefile b/drivers/fpga/xrt/lib/Makefile > new file mode 100644 > index 000000000000..5641231b2a36 > --- /dev/null > +++ b/drivers/fpga/xrt/lib/Makefile > @@ -0,0 +1,30 @@ > +# SPDX-License-Identifier: GPL-2.0 > +# > +# Copyright (C) 2020-2021 Xilinx, Inc. All rights reserved. > +# > +# Authors: Sonal.Santan@xilinx.com > +# > + > +FULL_XRT_PATH=$(srctree)/$(src)/.. > +FULL_DTC_PATH=$(srctree)/scripts/dtc/libfdt > + > +obj-$(CONFIG_FPGA_XRT_LIB) += xrt-lib.o > + > +xrt-lib-objs := \ > + main.o \ > + xroot.o \ > + xclbin.o \ > + subdev.o \ > + cdev.o \ > + group.o \ > + xleaf/vsec.o \ > + xleaf/axigate.o \ > + xleaf/devctl.o \ > + xleaf/icap.o \ > + xleaf/clock.o \ > + xleaf/clkfreq.o \ > + xleaf/ucs.o \ > + xleaf/calib.o \ > + > +ccflags-y := -I$(FULL_XRT_PATH)/include \ > + -I$(FULL_DTC_PATH) > diff --git a/drivers/fpga/xrt/metadata/Kconfig b/drivers/fpga/xrt/metadata/Kconfig > new file mode 100644 > index 000000000000..5012c9c6584d > --- /dev/null > +++ b/drivers/fpga/xrt/metadata/Kconfig > @@ -0,0 +1,12 @@ > +# SPDX-License-Identifier: GPL-2.0-only > +# > +# XRT Alveo FPGA device configuration > +# > + > +config FPGA_XRT_METADATA > + bool "XRT Alveo Driver Metadata Parser" > + select LIBFDT > + help > + This option provides helper functions to parse Xilinx Alveo FPGA > + firmware metadata. The metadata is in device tree format and XRT and the XRT > + driver uses it to discover HW subsystems behind PCIe BAR. the HW > diff --git a/drivers/fpga/xrt/metadata/Makefile b/drivers/fpga/xrt/metadata/Makefile > new file mode 100644 > index 000000000000..14f65ef1595c > --- /dev/null > +++ b/drivers/fpga/xrt/metadata/Makefile > @@ -0,0 +1,16 @@ > +# SPDX-License-Identifier: GPL-2.0 > +# > +# Copyright (C) 2020-2021 Xilinx, Inc. All rights reserved. > +# > +# Authors: Sonal.Santan@xilinx.com > +# > + > +FULL_XRT_PATH=$(srctree)/$(src)/.. > +FULL_DTC_PATH=$(srctree)/scripts/dtc/libfdt > + > +obj-$(CONFIG_FPGA_XRT_METADATA) += xrt-md.o > + > +xrt-md-objs := metadata.o > + > +ccflags-y := -I$(FULL_XRT_PATH)/include \ > + -I$(FULL_DTC_PATH) > diff --git a/drivers/fpga/xrt/mgmt/Kconfig b/drivers/fpga/xrt/mgmt/Kconfig > new file mode 100644 > index 000000000000..2b2a2c34685c > --- /dev/null > +++ b/drivers/fpga/xrt/mgmt/Kconfig > @@ -0,0 +1,15 @@ > +# SPDX-License-Identifier: GPL-2.0-only > +# > +# Xilinx XRT FPGA device configuration > +# > + > +config FPGA_XRT_XMGMT > + tristate "Xilinx Alveo Management Driver" > + depends on HWMON && PCI && FPGA_XRT_LIB FPGA_XRT_LIB also depends on HWMON and PCI, so this could be minimized. Tom > + select FPGA_XRT_METADATA > + select FPGA_BRIDGE > + select FPGA_REGION > + help > + Select this option to enable XRT PCIe driver for Xilinx Alveo FPGA. > + This driver provides interfaces for userspace application to access > + Alveo FPGA device. > diff --git a/drivers/fpga/xrt/mgmt/Makefile b/drivers/fpga/xrt/mgmt/Makefile > new file mode 100644 > index 000000000000..8051708c361c > --- /dev/null > +++ b/drivers/fpga/xrt/mgmt/Makefile > @@ -0,0 +1,19 @@ > +# SPDX-License-Identifier: GPL-2.0 > +# > +# Copyright (C) 2020-2021 Xilinx, Inc. All rights reserved. > +# > +# Authors: Sonal.Santan@xilinx.com > +# > + > +FULL_XRT_PATH=$(srctree)/$(src)/.. > +FULL_DTC_PATH=$(srctree)/scripts/dtc/libfdt > + > +obj-$(CONFIG_FPGA_XRT_XMGMT) += xmgmt.o > + > +xmgmt-objs := root.o \ > + main.o \ > + fmgr-drv.o \ > + main-region.o > + > +ccflags-y := -I$(FULL_XRT_PATH)/include \ > + -I$(FULL_DTC_PATH)
On 2/17/21 10:40 PM, Lizhi Hou wrote: > Alveo FPGA firmware and partial reconfigure file are in xclbin format. This code enumerates and extracts > Add > code to enumerate and extract sections from xclbin files. xclbin.h is cross > platform and used across all platforms and OS > > Signed-off-by: Sonal Santan <sonal.santan@xilinx.com> > Signed-off-by: Max Zhen <max.zhen@xilinx.com> > Signed-off-by: Lizhi Hou <lizhih@xilinx.com> > --- > drivers/fpga/xrt/include/xclbin-helper.h | 52 +++ > drivers/fpga/xrt/lib/xclbin.c | 394 ++++++++++++++++++++++ > include/uapi/linux/xrt/xclbin.h | 408 +++++++++++++++++++++++ > 3 files changed, 854 insertions(+) > create mode 100644 drivers/fpga/xrt/include/xclbin-helper.h > create mode 100644 drivers/fpga/xrt/lib/xclbin.c > create mode 100644 include/uapi/linux/xrt/xclbin.h > > diff --git a/drivers/fpga/xrt/include/xclbin-helper.h b/drivers/fpga/xrt/include/xclbin-helper.h > new file mode 100644 > index 000000000000..68218efc9d0b > --- /dev/null > +++ b/drivers/fpga/xrt/include/xclbin-helper.h > @@ -0,0 +1,52 @@ > +/* SPDX-License-Identifier: GPL-2.0 */ > +/* > + * Header file for Xilinx Runtime (XRT) driver > + * > + * Copyright (C) 2020-2021 Xilinx, Inc. > + * > + * Authors: > + * David Zhang <davidzha@xilinx.com> > + * Sonal Santan <sonal.santan@xilinx.com> > + */ > + > +#ifndef _XRT_XCLBIN_H > +#define _XRT_XCLBIN_H The header guard should match the filename. > + > +#include <linux/types.h> > +#include <linux/device.h> > +#include <linux/xrt/xclbin.h> > + > +#define ICAP_XCLBIN_V2 "xclbin2" > +#define DMA_HWICAP_BITFILE_BUFFER_SIZE 1024 > +#define MAX_XCLBIN_SIZE (1024 * 1024 * 1024) /* Assuming xclbin <= 1G, always */ #defines should have a prefix, maybe XRT_ or XCLBIN_ > + > +enum axlf_section_kind; > +struct axlf; > + > +/** > + * Bitstream header information as defined by Xilinx tools. > + * Please note that this struct definition is not owned by the driver. > + */ > +struct hw_icap_bit_header { File headers usually have fixed length fields like uint32_t Is this a structure the real header is converted into ? > + unsigned int header_length; /* Length of header in 32 bit words */ > + unsigned int bitstream_length; /* Length of bitstream to read in bytes*/ > + unsigned char *design_name; /* Design name get from bitstream */ > + unsigned char *part_name; /* Part name read from bitstream */ > + unsigned char *date; /* Date read from bitstream header */ > + unsigned char *time; /* Bitstream creation time */ > + unsigned int magic_length; /* Length of the magic numbers */ > + unsigned char *version; /* Version string */ > +}; > + > +const char *xrt_xclbin_kind_to_string(enum axlf_section_kind kind); Only add decl's that are using in multiple files. This is only defined in xclbin.c, why does it need to be in the header ? > +int xrt_xclbin_get_section(const struct axlf *xclbin, > + enum axlf_section_kind kind, void **data, > + uint64_t *len); > +int xrt_xclbin_get_metadata(struct device *dev, const struct axlf *xclbin, char **dtb); > +int xrt_xclbin_parse_bitstream_header(const unsigned char *data, > + unsigned int size, > + struct hw_icap_bit_header *header); > +void xrt_xclbin_free_header(struct hw_icap_bit_header *header); > +const char *xrt_clock_type2epname(enum CLOCK_TYPE type); CLOCK_TYPE needs a prefix, something like XCLBIN_CLOCK_TYPE > + > +#endif /* _XRT_XCLBIN_H */ > diff --git a/drivers/fpga/xrt/lib/xclbin.c b/drivers/fpga/xrt/lib/xclbin.c > new file mode 100644 > index 000000000000..47dc6ca25c1b > --- /dev/null > +++ b/drivers/fpga/xrt/lib/xclbin.c > @@ -0,0 +1,394 @@ > +// SPDX-License-Identifier: GPL-2.0 > +/* > + * Xilinx Alveo FPGA Driver XCLBIN parser > + * > + * Copyright (C) 2020-2021 Xilinx, Inc. > + * > + * Authors: David Zhang <davidzha@xilinx.com> > + */ > + > +#include <asm/errno.h> > +#include <linux/vmalloc.h> > +#include <linux/device.h> > +#include "xclbin-helper.h" > +#include "metadata.h" > + What is XHI ? Maybe expand this, at the lease should comment > +/* Used for parsing bitstream header */ > +#define XHI_EVEN_MAGIC_BYTE 0x0f > +#define XHI_ODD_MAGIC_BYTE 0xf0 > + > +/* Extra mode for IDLE */ > +#define XHI_OP_IDLE -1 > +#define XHI_BIT_HEADER_FAILURE -1 > + > +/* The imaginary module length register */ > +#define XHI_MLR 15 > + > +static inline unsigned char xhi_data_and_inc(const unsigned char *d, int *i, int sz) could move to the *.h > +{_ > + unsigned char data; > + > + if (*i >= sz) > + return -1; The return value of this funtion is not always checked, at the least add a dev_err here > + > + data = d[*i]; > + (*i)++; > + > + return data; > +} > + > +static const struct axlf_section_header * > +xrt_xclbin_get_section_hdr(const struct axlf *xclbin, > + enum axlf_section_kind kind) > +{ > + int i = 0; > + > + for (i = 0; i < xclbin->m_header.m_numSections; i++) { > + if (xclbin->m_sections[i].m_sectionKind == kind) > + return &xclbin->m_sections[i]; > + } > + > + return NULL; > +} > + > +static int > +xrt_xclbin_check_section_hdr(const struct axlf_section_header *header, > + u64 xclbin_len) > +{ > + int ret; > + > + ret = (header->m_sectionOffset + header->m_sectionSize) > xclbin_len ? -EINVAL : 0; Tristate is harder to read, consider replacing with if() int ret = 0 if () ret = > + > + return ret; > +} > + > +static int xrt_xclbin_section_info(const struct axlf *xclbin, > + enum axlf_section_kind kind, > + u64 *offset, u64 *size) > +{ > + const struct axlf_section_header *mem_header = NULL; > + u64 xclbin_len; > + int err = 0; > + > + mem_header = xrt_xclbin_get_section_hdr(xclbin, kind); > + if (!mem_header) > + return -EINVAL; > + > + xclbin_len = xclbin->m_header.m_length; > + if (xclbin_len > MAX_XCLBIN_SIZE) > + return -EINVAL; This check can be added to the function call.. or the sanity checking added to the earier call to *get_section_hdr There a number of small functions that can be combined. > + > + err = xrt_xclbin_check_section_hdr(mem_header, xclbin_len); > + if (err) > + return err; > + > + *offset = mem_header->m_sectionOffset; > + *size = mem_header->m_sectionSize; > + > + return 0; > +} > + > +/* caller should free the allocated memory for **data */ must free This comment also needs to be with the *.h decl > +int xrt_xclbin_get_section(const struct axlf *buf, > + enum axlf_section_kind kind, > + void **data, u64 *len) > +{ > + const struct axlf *xclbin = (const struct axlf *)buf; > + void *section = NULL; > + int err = 0; > + u64 offset = 0; > + u64 size = 0; > + > + err = xrt_xclbin_section_info(xclbin, kind, &offset, &size); > + if (err) > + return err; > + > + section = vmalloc(size); > + if (!section) > + return -ENOMEM; > + > + memcpy(section, ((const char *)xclbin) + offset, size); > + > + *data = section; a general comment for exported function checking the validity of the inputs in more important. here you assume **data is valid, really you should check. > + if (len) > + *len = size; len setting being optional, needs to be in the *.h comment > + > + return 0; > +} > +EXPORT_SYMBOL_GPL(xrt_xclbin_get_section); > + Instead of allocating new memory and making copies of bits of *data why not have the points reference data ? The size operations look like translating big endian data to little endian. This will break on a big endian host. > +/* parse bitstream header */ > +int xrt_xclbin_parse_bitstream_header(const unsigned char *data, > + unsigned int size, > + struct hw_icap_bit_header *header) > +{ > + unsigned int index; > + unsigned int len; > + unsigned int tmp; > + unsigned int i; > + > + memset(header, 0, sizeof(*header)); > + /* Start Index at start of bitstream */ > + index = 0; > + > + /* Initialize HeaderLength. If header returned early inidicates > + * failure. This side effect should be documented in the *.h comment. Also the multi line comment is a bit weird, not sure if it is ok > + */ > + header->header_length = XHI_BIT_HEADER_FAILURE; > + > + /* Get "Magic" length */ > + header->magic_length = xhi_data_and_inc(data, &index, size); > + header->magic_length = (header->magic_length << 8) | xhi_data_and_inc(data, &index, size); > + > + /* Read in "magic" */ > + for (i = 0; i < header->magic_length - 1; i++) { > + tmp = xhi_data_and_inc(data, &index, size); > + if (i % 2 == 0 && tmp != XHI_EVEN_MAGIC_BYTE) > + return -1; /* INVALID_FILE_HEADER_ERROR */ > + > + if (i % 2 == 1 && tmp != XHI_ODD_MAGIC_BYTE) > + return -1; /* INVALID_FILE_HEADER_ERROR */ > + } > + > + /* Read null end of magic data. */ > + tmp = xhi_data_and_inc(data, &index, size); > + > + /* Read 0x01 (short) */ > + tmp = xhi_data_and_inc(data, &index, size); > + tmp = (tmp << 8) | xhi_data_and_inc(data, &index, size); > + > + /* Check the "0x01" half word */ > + if (tmp != 0x01) > + return -1; /* INVALID_FILE_HEADER_ERROR */ > + > + /* Read 'a' */ > + tmp = xhi_data_and_inc(data, &index, size); > + if (tmp != 'a') > + return -1; /* INVALID_FILE_HEADER_ERROR */ > + > + /* Get Design Name length */ > + len = xhi_data_and_inc(data, &index, size); > + len = (len << 8) | xhi_data_and_inc(data, &index, size); > + > + /* allocate space for design name and final null character. */ > + header->design_name = vmalloc(len); > + if (!header->design_name) > + return -ENOMEM; > + > + /* Read in Design Name */ > + for (i = 0; i < len; i++) > + header->design_name[i] = xhi_data_and_inc(data, &index, size); > + > + if (header->design_name[len - 1] != '\0') > + return -1; > + > + header->version = strstr(header->design_name, "Version=") + strlen("Version="); > + > + /* Read 'b' */ > + tmp = xhi_data_and_inc(data, &index, size); > + if (tmp != 'b') > + return -1; /* INVALID_FILE_HEADER_ERROR */ > + > + /* Get Part Name length */ > + len = xhi_data_and_inc(data, &index, size); > + len = (len << 8) | xhi_data_and_inc(data, &index, size); > + > + /* allocate space for part name and final null character. */ > + header->part_name = vmalloc(len); > + if (!header->part_name) > + return -ENOMEM; > + > + /* Read in part name */ > + for (i = 0; i < len; i++) > + header->part_name[i] = xhi_data_and_inc(data, &index, size); > + > + if (header->part_name[len - 1] != '\0') > + return -1; > + > + /* Read 'c' */ > + tmp = xhi_data_and_inc(data, &index, size); > + if (tmp != 'c') > + return -1; /* INVALID_FILE_HEADER_ERROR */ > + > + /* Get date length */ > + len = xhi_data_and_inc(data, &index, size); > + len = (len << 8) | xhi_data_and_inc(data, &index, size); > + > + /* allocate space for date and final null character. */ > + header->date = vmalloc(len); > + if (!header->date) > + return -ENOMEM; > + > + /* Read in date name */ > + for (i = 0; i < len; i++) > + header->date[i] = xhi_data_and_inc(data, &index, size); > + > + if (header->date[len - 1] != '\0') > + return -1; generally -EINVAL is more meaningful than -1 > + > + /* Read 'd' */ > + tmp = xhi_data_and_inc(data, &index, size); > + if (tmp != 'd') > + return -1; /* INVALID_FILE_HEADER_ERROR */ > + > + /* Get time length */ > + len = xhi_data_and_inc(data, &index, size); > + len = (len << 8) | xhi_data_and_inc(data, &index, size); > + > + /* allocate space for time and final null character. */ > + header->time = vmalloc(len); > + if (!header->time) > + return -ENOMEM; > + > + /* Read in time name */ > + for (i = 0; i < len; i++) > + header->time[i] = xhi_data_and_inc(data, &index, size); > + > + if (header->time[len - 1] != '\0') > + return -1; > + > + /* Read 'e' */ > + tmp = xhi_data_and_inc(data, &index, size); > + if (tmp != 'e') > + return -1; /* INVALID_FILE_HEADER_ERROR */ > + > + /* Get byte length of bitstream */ > + header->bitstream_length = xhi_data_and_inc(data, &index, size); > + header->bitstream_length = (header->bitstream_length << 8) | > + xhi_data_and_inc(data, &index, size); > + header->bitstream_length = (header->bitstream_length << 8) | > + xhi_data_and_inc(data, &index, size); > + header->bitstream_length = (header->bitstream_length << 8) | > + xhi_data_and_inc(data, &index, size); generally a problem This is confusing, collect the bytes in a temp[] and construct the header->bitstream_length in on statement. This is a case where xhi_data_and_inc return is not checked and if it failed could blow up later. > + > + header->header_length = index; index is not a good variable name if it going to be stored as a length. consider changing it to something like current_length. > + > + return 0; > +} > +EXPORT_SYMBOL_GPL(xrt_xclbin_parse_bitstream_header); > + > +void xrt_xclbin_free_header(struct hw_icap_bit_header *header) > +{ > + vfree(header->design_name); > + vfree(header->part_name); > + vfree(header->date); > + vfree(header->time); missing header->version > +} > +EXPORT_SYMBOL_GPL(xrt_xclbin_free_header); > + > +struct xrt_clock_desc { > + char *clock_ep_name; > + u32 clock_xclbin_type; > + char *clkfreq_ep_name; > +} clock_desc[] = { > + { > + .clock_ep_name = XRT_MD_NODE_CLK_KERNEL1, > + .clock_xclbin_type = CT_DATA, > + .clkfreq_ep_name = XRT_MD_NODE_CLKFREQ_K1, > + }, > + { > + .clock_ep_name = XRT_MD_NODE_CLK_KERNEL2, > + .clock_xclbin_type = CT_KERNEL, > + .clkfreq_ep_name = XRT_MD_NODE_CLKFREQ_K2, > + }, > + { > + .clock_ep_name = XRT_MD_NODE_CLK_KERNEL3, > + .clock_xclbin_type = CT_SYSTEM, > + .clkfreq_ep_name = XRT_MD_NODE_CLKFREQ_HBM, > + }, > +}; > + > +const char *xrt_clock_type2epname(enum CLOCK_TYPE type) > +{ > + int i; > + > + for (i = 0; i < ARRAY_SIZE(clock_desc); i++) { > + if (clock_desc[i].clock_xclbin_type == type) > + return clock_desc[i].clock_ep_name; > + } > + return NULL; > +} > +EXPORT_SYMBOL_GPL(xrt_clock_type2epname); What is clock stuff doing in xclbin ? I think clock needs its own file > + > +static const char *clock_type2clkfreq_name(u32 type) > +{ > + int i; > + > + for (i = 0; i < ARRAY_SIZE(clock_desc); i++) { > + if (clock_desc[i].clock_xclbin_type == type) > + return clock_desc[i].clkfreq_ep_name; > + } > + return NULL; > +} > + > +static int xrt_xclbin_add_clock_metadata(struct device *dev, > + const struct axlf *xclbin, > + char *dtb) > +{ > + int i; > + u16 freq; > + struct clock_freq_topology *clock_topo; > + int rc = xrt_xclbin_get_section(xclbin, CLOCK_FREQ_TOPOLOGY, > + (void **)&clock_topo, NULL); > + > + if (rc) > + return 0; failing is ok ? > + > + for (i = 0; i < clock_topo->m_count; i++) { > + u8 type = clock_topo->m_clock_freq[i].m_type; > + const char *ep_name = xrt_clock_type2epname(type); > + const char *counter_name = clock_type2clkfreq_name(type); > + > + if (!ep_name || !counter_name) > + continue; > + > + freq = cpu_to_be16(clock_topo->m_clock_freq[i].m_freq_Mhz); > + rc = xrt_md_set_prop(dev, dtb, ep_name, NULL, XRT_MD_PROP_CLK_FREQ, > + &freq, sizeof(freq)); > + if (rc) > + break; > + > + rc = xrt_md_set_prop(dev, dtb, ep_name, NULL, XRT_MD_PROP_CLK_CNT, > + counter_name, strlen(counter_name) + 1); > + if (rc) > + break; Failing in a loop, why isn't there some cleanup of the *set_prop() calls ? > + } > + > + vfree(clock_topo); > + > + return rc; > +} > + > +int xrt_xclbin_get_metadata(struct device *dev, const struct axlf *xclbin, char **dtb) > +{ > + char *md = NULL, *newmd = NULL; > + u64 len; *dtb = NULL; > + int rc = xrt_xclbin_get_section(xclbin, PARTITION_METADATA, > + (void **)&md, &len); > + > + if (rc) > + goto done; > + > + /* Sanity check the dtb section. */ > + if (xrt_md_size(dev, md) > len) { > + rc = -EINVAL; > + goto done; > + } > + > + newmd = xrt_md_dup(dev, md); > + if (!newmd) { > + rc = -EFAULT; > + goto done; > + } > + /* Convert various needed xclbin sections into dtb. */ > + rc = xrt_xclbin_add_clock_metadata(dev, xclbin, newmd); newmd is only valid here, but the above error handling jump here. change this to if (!rc) *dtb = newmd else vfree(newmd) done: vfree(md) return rc; > + > +done: > + if (rc == 0) > + *dtb = newmd; > + else > + vfree(newmd); > + vfree(md); > + return rc; > +} > +EXPORT_SYMBOL_GPL(xrt_xclbin_get_metadata); > diff --git a/include/uapi/linux/xrt/xclbin.h b/include/uapi/linux/xrt/xclbin.h > new file mode 100644 > index 000000000000..53f140123ef1 > --- /dev/null > +++ b/include/uapi/linux/xrt/xclbin.h > @@ -0,0 +1,408 @@ > +/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */ > +/* > + * Xilinx FPGA compiled binary container format > + * > + * Copyright (C) 2015-2021, Xilinx Inc > + */ > + > +#ifndef _XCLBIN_H_ > +#define _XCLBIN_H_ > + > +#ifdef _WIN32 WIN32 ? Only 1 other header has this ifdef > + #include <cstdint> > + #include <algorithm> c++ is being assumed for windows > + #include "windows/uuid.h" thank you for not including windows.h ;) > +#else > + #if defined(__KERNEL__) > + #include <linux/types.h> > + #include <linux/uuid.h> > + #include <linux/version.h> > + #elif defined(__cplusplus) > + #include <cstdlib> > + #include <cstdint> > + #include <algorithm> > + #include <uuid/uuid.h> > + #else > + #include <stdlib.h> > + #include <stdint.h> > + #include <uuid/uuid.h> > + #endif > +#endif > + Review these includes, some could be convenience includes. ex/ linux/version.h with no obvious use of version macros. struct axlf_header { + uint64_t m_length; /* Total size of the xclbin file */ .. snip .. + union { + char m_next_axlf[16]; /* Name of next xclbin file */ + /* in the daisy chain */ + uuid_t uuid; /* uuid of this xclbin*/ + }; As mentioned in an earlier patch, if uuid_t is larger than 16 bytes, axlf_header breaks. while it is convenient to have this type here, it would be better this access was handled in another way. Maybe a host specific function. I also do not see a pragma pack, usually this is set of 1 so the compiler does not shuffle elements, increase size etc. > +#ifdef __cplusplus > +extern "C" { > +#endif > + > +/** > + * DOC: Container format for Xilinx FPGA images > + * The container stores bitstreams, metadata and firmware images. > + * xclbin/xsabin is ELF-like binary container format. It is structured is an ELF-like file format. It is a structured > + * series of sections. There is a file header followed by several section > + * headers which is followed by sections. A section header points to an > + * actual section. There is an optional signature at the end. The > + * following figure illustrates a typical xclbin: > + * > + * +---------------------+ > + * | | > + * | HEADER | > + * +---------------------+ > + * | SECTION HEADER | > + * | | > + * +---------------------+ > + * | ... | > + * | | > + * +---------------------+ > + * | SECTION HEADER | > + * | | > + * +---------------------+ > + * | SECTION | > + * | | > + * +---------------------+ > + * | ... | > + * | | > + * +---------------------+ > + * | SECTION | > + * | | > + * +---------------------+ > + * | SIGNATURE | > + * | (OPTIONAL) | > + * +---------------------+ This ascii art is a mixture of tabs and spaces, for someone with tab = 2 spaces, this will look messed up. convert the tabs to spaces > + */ > + > +enum XCLBIN_MODE { > + XCLBIN_FLAT, generally all enums used in a file format should be initialized. This likely should be XCLBIN_FLAT = 0, > + XCLBIN_PR, > + XCLBIN_TANDEM_STAGE2, > + XCLBIN_TANDEM_STAGE2_WITH_PR, > + XCLBIN_HW_EMU, > + XCLBIN_SW_EMU, > + XCLBIN_MODE_MAX > +}; > + > +enum axlf_section_kind { > + BITSTREAM = 0, > + CLEARING_BITSTREAM, > + EMBEDDED_METADATA, > + FIRMWARE, > + DEBUG_DATA, > + SCHED_FIRMWARE, > + MEM_TOPOLOGY, > + CONNECTIVITY, > + IP_LAYOUT, > + DEBUG_IP_LAYOUT, > + DESIGN_CHECK_POINT, > + CLOCK_FREQ_TOPOLOGY, > + MCS, > + BMC, > + BUILD_METADATA, > + KEYVALUE_METADATA, > + USER_METADATA, > + DNA_CERTIFICATE, > + PDI, > + BITSTREAM_PARTIAL_PDI, > + PARTITION_METADATA, > + EMULATION_DATA, > + SYSTEM_METADATA, > + SOFT_KERNEL, > + ASK_FLASH, > + AIE_METADATA, > + ASK_GROUP_TOPOLOGY, > + ASK_GROUP_CONNECTIVITY > +}; > + > +enum MEM_TYPE { > + MEM_DDR3, > + MEM_DDR4, > + MEM_DRAM, > + MEM_STREAMING, > + MEM_PREALLOCATED_GLOB, > + MEM_ARE, > + MEM_HBM, > + MEM_BRAM, > + MEM_URAM, > + MEM_STREAMING_CONNECTION > +}; > + > +enum IP_TYPE { > + IP_MB = 0, > + IP_KERNEL, > + IP_DNASC, > + IP_DDR4_CONTROLLER, > + IP_MEM_DDR4, > + IP_MEM_HBM > +}; > + > +struct axlf_section_header { > + uint32_t m_sectionKind; /* Section type */ > + char m_sectionName[16]; /* Examples: "stage2", "clear1", */ > + /* "clear2", "ocl1", "ocl2, */ > + /* "ublaze", "sched" */ > + uint64_t m_sectionOffset; /* File offset of section data */ > + uint64_t m_sectionSize; /* Size of section data */ > +}; > + > +struct axlf_header { > + uint64_t m_length; /* Total size of the xclbin file */ > + uint64_t m_timeStamp; /* Number of seconds since epoch */ > + /* when xclbin was created */ > + uint64_t m_featureRomTimeStamp; /* TimeSinceEpoch of the featureRom */ > + uint16_t m_versionPatch; /* Patch Version */ > + uint8_t m_versionMajor; /* Major Version - Version: 2.1.0*/ i did not see the version checked earlier, which one is expected ? > + uint8_t m_versionMinor; /* Minor Version */ > + uint32_t m_mode; /* XCLBIN_MODE */ > + union { > + struct { > + uint64_t m_platformId; /* 64 bit platform ID: */ > + /* vendor-device-subvendor-subdev */ > + uint64_t m_featureId; /* 64 bit feature id */ > + } rom; > + unsigned char rom_uuid[16]; /* feature ROM UUID for which */ > + /* this xclbin was generated */ > + }; > + unsigned char m_platformVBNV[64]; /* e.g. */ what is VBNV? > + /* xilinx:xil-accel-rd-ku115:4ddr-xpr:3.4: null terminated */ > + union { > + char m_next_axlf[16]; /* Name of next xclbin file */ > + /* in the daisy chain */ > + uuid_t uuid; /* uuid of this xclbin*/ > + }; > + char m_debug_bin[16]; /* Name of binary with debug */ > + /* information */ > + uint32_t m_numSections; /* Number of section headers */ > +}; > + > +struct axlf { > + char m_magic[8]; /* Should be "xclbin2\0" */ > + int32_t m_signature_length; /* Length of the signature. */ > + /* -1 indicates no signature */ > + unsigned char reserved[28]; /* Note: Initialized to 0xFFs */ > + > + unsigned char m_keyBlock[256]; /* Signature for validation */ > + /* of binary */ > + uint64_t m_uniqueId; /* axlf's uniqueId, use it to */ > + /* skip redownload etc */ > + struct axlf_header m_header; /* Inline header */ > + struct axlf_section_header m_sections[1]; /* One or more section */ > + /* headers follow */ > +}; > + > +/* bitstream information */ > +struct xlnx_bitstream { > + uint8_t m_freq[8]; > + char bits[1]; > +}; > + > +/**** MEMORY TOPOLOGY SECTION ****/ > +struct mem_data { > + uint8_t m_type; /* enum corresponding to mem_type. */ > + uint8_t m_used; /* if 0 this bank is not present */ > + union { > + uint64_t m_size; /* if mem_type DDR, then size in KB; */ > + uint64_t route_id; /* if streaming then "route_id" */ > + }; > + union { > + uint64_t m_base_address;/* if DDR then the base address; */ > + uint64_t flow_id; /* if streaming then "flow id" */ > + }; > + unsigned char m_tag[16]; /* DDR: BANK0,1,2,3, has to be null */ > + /* terminated; if streaming then stream0, 1 etc */ > +}; > + > +struct mem_topology { > + int32_t m_count; /* Number of mem_data */ > + struct mem_data m_mem_data[1]; /* Should be sorted on mem_type */ > +}; > + > +/**** CONNECTIVITY SECTION ****/ > +/* Connectivity of each argument of Kernel. It will be in terms of argument This section does not make sense. Likely you mean some algorithm kernel, rather than the linux kernel. > + * index associated. For associating kernel instances with arguments and > + * banks, start at the connectivity section. Using the m_ip_layout_index > + * access the ip_data.m_name. Now we can associate this kernel instance > + * with its original kernel name and get the connectivity as well. This > + * enables us to form related groups of kernel instances. > + */ > + > +struct connection { > + int32_t arg_index; /* From 0 to n, may not be contiguous as scalars */ > + /* skipped */ > + int32_t m_ip_layout_index; /* index into the ip_layout section. */ > + /* ip_layout.m_ip_data[index].m_type == IP_KERNEL */ > + int32_t mem_data_index; /* index of the m_mem_data . Flag error is */ > + /* m_used false. */ > +}; > + > +struct connectivity { > + int32_t m_count; > + struct connection m_connection[1]; > +}; > + > +/**** IP_LAYOUT SECTION ****/ > + > +/* IP Kernel */ > +#define IP_INT_ENABLE_MASK 0x0001 > +#define IP_INTERRUPT_ID_MASK 0x00FE > +#define IP_INTERRUPT_ID_SHIFT 0x1 > + > +enum IP_CONTROL { > + AP_CTRL_HS = 0, > + AP_CTRL_CHAIN = 1, > + AP_CTRL_NONE = 2, > + AP_CTRL_ME = 3, > + ACCEL_ADAPTER = 4 assigning beyond the first is not necessary unless there are dups or gaps > +}; > + > +#define IP_CONTROL_MASK 0xFF00 > +#define IP_CONTROL_SHIFT 0x8 > + > +/* IPs on AXI lite - their types, names, and base addresses.*/ > +struct ip_data { > + uint32_t m_type; /* map to IP_TYPE enum */ > + union { > + uint32_t properties; /* Default: 32-bits to indicate ip */ > + /* specific property. */ > + /* m_type: IP_KERNEL > + * m_int_enable : Bit - 0x0000_0001; > + * m_interrupt_id : Bits - 0x0000_00FE; > + * m_ip_control : Bits = 0x0000_FF00; > + */ > + struct { /* m_type: IP_MEM_* */ > + uint16_t m_index; > + uint8_t m_pc_index; > + uint8_t unused; > + } indices; > + }; > + uint64_t m_base_address; > + uint8_t m_name[64]; /* eg Kernel name corresponding to KERNEL */ > + /* instance, can embed CU name in future. */ > +}; > + > +struct ip_layout { > + int32_t m_count; > + struct ip_data m_ip_data[1]; /* All the ip_data needs to be sorted */ > + /* by m_base_address. */ general doing the bla[1] for c++ ? Tom > +}; > + > +/*** Debug IP section layout ****/ > +enum DEBUG_IP_TYPE { > + UNDEFINED = 0, > + LAPC, > + ILA, > + AXI_MM_MONITOR, > + AXI_TRACE_FUNNEL, > + AXI_MONITOR_FIFO_LITE, > + AXI_MONITOR_FIFO_FULL, > + ACCEL_MONITOR, > + AXI_STREAM_MONITOR, > + AXI_STREAM_PROTOCOL_CHECKER, > + TRACE_S2MM, > + AXI_DMA, > + TRACE_S2MM_FULL > +}; > + > +struct debug_ip_data { > + uint8_t m_type; /* type of enum DEBUG_IP_TYPE */ > + uint8_t m_index_lowbyte; > + uint8_t m_properties; > + uint8_t m_major; > + uint8_t m_minor; > + uint8_t m_index_highbyte; > + uint8_t m_reserved[2]; > + uint64_t m_base_address; > + char m_name[128]; > +}; > + > +struct debug_ip_layout { > + uint16_t m_count; > + struct debug_ip_data m_debug_ip_data[1]; > +}; > + > +/* Supported clock frequency types */ > +enum CLOCK_TYPE { > + CT_UNUSED = 0, /* Initialized value */ > + CT_DATA = 1, /* Data clock */ > + CT_KERNEL = 2, /* Kernel clock */ > + CT_SYSTEM = 3 /* System Clock */ > +}; > + > +/* Clock Frequency Entry */ > +struct clock_freq { > + uint16_t m_freq_Mhz; /* Frequency in MHz */ > + uint8_t m_type; /* Clock type (enum CLOCK_TYPE) */ > + uint8_t m_unused[5]; /* Not used - padding */ > + char m_name[128]; /* Clock Name */ > +}; > + > +/* Clock frequency section */ > +struct clock_freq_topology { > + int16_t m_count; /* Number of entries */ > + struct clock_freq m_clock_freq[1]; /* Clock array */ > +}; > + > +/* Supported MCS file types */ > +enum MCS_TYPE { > + MCS_UNKNOWN = 0, /* Initialized value */ > + MCS_PRIMARY = 1, /* The primary mcs file data */ > + MCS_SECONDARY = 2, /* The secondary mcs file data */ > +}; > + > +/* One chunk of MCS data */ > +struct mcs_chunk { > + uint8_t m_type; /* MCS data type */ > + uint8_t m_unused[7]; /* padding */ > + uint64_t m_offset; /* data offset from the start of */ > + /* the section */ > + uint64_t m_size; /* data size */ > +}; > + > +/* MCS data section */ > +struct mcs { > + int8_t m_count; /* Number of chunks */ > + int8_t m_unused[7]; /* padding */ > + struct mcs_chunk m_chunk[1]; /* MCS chunks followed by data */ > +}; > + > +/* bmc data section */ > +struct bmc { > + uint64_t m_offset; /* data offset from the start of */ > + /* the section */ > + uint64_t m_size; /* data size (bytes) */ > + char m_image_name[64]; /* Name of the image */ > + /* (e.g., MSP432P401R) */ > + char m_device_name[64]; /* Device ID (e.g., VCU1525) */ > + char m_version[64]; > + char m_md5value[33]; /* MD5 Expected Value */ > + /* (e.g., 56027182079c0bd621761b7dab5a27ca)*/ > + char m_padding[7]; /* Padding */ > +}; > + > +/* soft kernel data section, used by classic driver */ > +struct soft_kernel { > + /** Prefix Syntax: > + * mpo - member, pointer, offset > + * This variable represents a zero terminated string > + * that is offseted from the beginning of the section. > + * The pointer to access the string is initialized as follows: > + * char * pCharString = (address_of_section) + (mpo value) > + */ > + uint32_t mpo_name; /* Name of the soft kernel */ > + uint32_t m_image_offset; /* Image offset */ > + uint32_t m_image_size; /* Image size */ > + uint32_t mpo_version; /* Version */ > + uint32_t mpo_md5_value; /* MD5 checksum */ > + uint32_t mpo_symbol_name; /* Symbol name */ > + uint32_t m_num_instances; /* Number of instances */ > + uint8_t padding[36]; /* Reserved for future use */ > + uint8_t reservedExt[16]; /* Reserved for future extended data */ > +}; > + > +enum CHECKSUM_TYPE { > + CST_UNKNOWN = 0, > + CST_SDBM = 1, > + CST_LAST > +}; > + > +#ifdef __cplusplus > +} > +#endif > + > +#endif
On Sun, Feb 21, 2021 at 09:12:37AM -0800, Tom Rix wrote: > > On 2/17/21 10:40 PM, Lizhi Hou wrote: > > Alveo FPGA firmware and partial reconfigure file are in xclbin format. > This code enumerates and extracts > > Add > > code to enumerate and extract sections from xclbin files. xclbin.h is cross > > platform and used across all platforms and OS > > > > Signed-off-by: Sonal Santan <sonal.santan@xilinx.com> > > Signed-off-by: Max Zhen <max.zhen@xilinx.com> > > Signed-off-by: Lizhi Hou <lizhih@xilinx.com> > > --- > > drivers/fpga/xrt/include/xclbin-helper.h | 52 +++ > > drivers/fpga/xrt/lib/xclbin.c | 394 ++++++++++++++++++++++ > > include/uapi/linux/xrt/xclbin.h | 408 +++++++++++++++++++++++ > > 3 files changed, 854 insertions(+) > > create mode 100644 drivers/fpga/xrt/include/xclbin-helper.h > > create mode 100644 drivers/fpga/xrt/lib/xclbin.c > > create mode 100644 include/uapi/linux/xrt/xclbin.h > > > > diff --git a/drivers/fpga/xrt/include/xclbin-helper.h b/drivers/fpga/xrt/include/xclbin-helper.h > > new file mode 100644 > > index 000000000000..68218efc9d0b > > --- /dev/null > > +++ b/drivers/fpga/xrt/include/xclbin-helper.h > > @@ -0,0 +1,52 @@ > > +/* SPDX-License-Identifier: GPL-2.0 */ > > +/* > > + * Header file for Xilinx Runtime (XRT) driver > > + * > > + * Copyright (C) 2020-2021 Xilinx, Inc. > > + * > > + * Authors: > > + * David Zhang <davidzha@xilinx.com> > > + * Sonal Santan <sonal.santan@xilinx.com> > > + */ > > + > > +#ifndef _XRT_XCLBIN_H > > +#define _XRT_XCLBIN_H > > The header guard should match the filename. > > > + > > +#include <linux/types.h> > > +#include <linux/device.h> > > +#include <linux/xrt/xclbin.h> > > + > > +#define ICAP_XCLBIN_V2 "xclbin2" > > +#define DMA_HWICAP_BITFILE_BUFFER_SIZE 1024 > > +#define MAX_XCLBIN_SIZE (1024 * 1024 * 1024) /* Assuming xclbin <= 1G, always */ > #defines should have a prefix, maybe XRT_ or XCLBIN_ > > + > > +enum axlf_section_kind; > > +struct axlf; > > + > > +/** > > + * Bitstream header information as defined by Xilinx tools. > > + * Please note that this struct definition is not owned by the driver. > > + */ > > +struct hw_icap_bit_header { > > File headers usually have fixed length fields like uint32_t > > Is this a structure the real header is converted into ? > > > + unsigned int header_length; /* Length of header in 32 bit words */ > > + unsigned int bitstream_length; /* Length of bitstream to read in bytes*/ > > + unsigned char *design_name; /* Design name get from bitstream */ > > + unsigned char *part_name; /* Part name read from bitstream */ > > + unsigned char *date; /* Date read from bitstream header */ > > + unsigned char *time; /* Bitstream creation time */ > > + unsigned int magic_length; /* Length of the magic numbers */ > > + unsigned char *version; /* Version string */ > > +}; > > + > > +const char *xrt_xclbin_kind_to_string(enum axlf_section_kind kind); > > Only add decl's that are using in multiple files. > > This is only defined in xclbin.c, why does it need to be in the header ? > > > +int xrt_xclbin_get_section(const struct axlf *xclbin, > > + enum axlf_section_kind kind, void **data, > > + uint64_t *len); > > +int xrt_xclbin_get_metadata(struct device *dev, const struct axlf *xclbin, char **dtb); > > +int xrt_xclbin_parse_bitstream_header(const unsigned char *data, > > + unsigned int size, > > + struct hw_icap_bit_header *header); > > +void xrt_xclbin_free_header(struct hw_icap_bit_header *header); > > +const char *xrt_clock_type2epname(enum CLOCK_TYPE type); > CLOCK_TYPE needs a prefix, something like XCLBIN_CLOCK_TYPE > > + > > +#endif /* _XRT_XCLBIN_H */ > > diff --git a/drivers/fpga/xrt/lib/xclbin.c b/drivers/fpga/xrt/lib/xclbin.c > > new file mode 100644 > > index 000000000000..47dc6ca25c1b > > --- /dev/null > > +++ b/drivers/fpga/xrt/lib/xclbin.c > > @@ -0,0 +1,394 @@ > > +// SPDX-License-Identifier: GPL-2.0 > > +/* > > + * Xilinx Alveo FPGA Driver XCLBIN parser > > + * > > + * Copyright (C) 2020-2021 Xilinx, Inc. > > + * > > + * Authors: David Zhang <davidzha@xilinx.com> > > + */ > > + > > +#include <asm/errno.h> > > +#include <linux/vmalloc.h> > > +#include <linux/device.h> > > +#include "xclbin-helper.h" > > +#include "metadata.h" > > + > What is XHI ? Maybe expand this, at the lease should comment > > +/* Used for parsing bitstream header */ > > +#define XHI_EVEN_MAGIC_BYTE 0x0f > > +#define XHI_ODD_MAGIC_BYTE 0xf0 > > + > > +/* Extra mode for IDLE */ > > +#define XHI_OP_IDLE -1 > > +#define XHI_BIT_HEADER_FAILURE -1 > > + > > +/* The imaginary module length register */ > > +#define XHI_MLR 15 > > + > > +static inline unsigned char xhi_data_and_inc(const unsigned char *d, int *i, int sz) > could move to the *.h > > +{_ > > + unsigned char data; > > + > > + if (*i >= sz) > > + return -1; > The return value of this funtion is not always checked, at the least add a dev_err here > > + > > + data = d[*i]; > > + (*i)++; > > + > > + return data; > > +} > > + > > +static const struct axlf_section_header * > > +xrt_xclbin_get_section_hdr(const struct axlf *xclbin, > > + enum axlf_section_kind kind) > > +{ > > + int i = 0; > > + > > + for (i = 0; i < xclbin->m_header.m_numSections; i++) { > > + if (xclbin->m_sections[i].m_sectionKind == kind) > > + return &xclbin->m_sections[i]; > > + } > > + > > + return NULL; > > +} > > + > > +static int > > +xrt_xclbin_check_section_hdr(const struct axlf_section_header *header, > > + u64 xclbin_len) > > +{ > > + int ret; > > + > > + ret = (header->m_sectionOffset + header->m_sectionSize) > xclbin_len ? -EINVAL : 0; > > Tristate is harder to read, consider replacing with if() > > int ret = 0 > > if () > > ret = Why not just: if (header->m_section_offset + header->m_section_size) return -EINVAL; return 0; Also please fix the camelCase throughout the entire patchset. > > > > + > > + return ret; > > +} > > + > > +static int xrt_xclbin_section_info(const struct axlf *xclbin, > > + enum axlf_section_kind kind, > > + u64 *offset, u64 *size) > > +{ > > + const struct axlf_section_header *mem_header = NULL; > > + u64 xclbin_len; > > + int err = 0; > > + > > + mem_header = xrt_xclbin_get_section_hdr(xclbin, kind); > > + if (!mem_header) > > + return -EINVAL; > > + > > + xclbin_len = xclbin->m_header.m_length; > > + if (xclbin_len > MAX_XCLBIN_SIZE) > > + return -EINVAL; > > This check can be added to the function call.. > > or the sanity checking added to the earier call to *get_section_hdr > > There a number of small functions that can be combined. > > > + > > + err = xrt_xclbin_check_section_hdr(mem_header, xclbin_len); > > + if (err) > > + return err; > > + > > + *offset = mem_header->m_sectionOffset; > > + *size = mem_header->m_sectionSize; > > + > > + return 0; > > +} > > + > > +/* caller should free the allocated memory for **data */ > > must free > > This comment also needs to be with the *.h decl > > > +int xrt_xclbin_get_section(const struct axlf *buf, > > + enum axlf_section_kind kind, > > + void **data, u64 *len) > > +{ > > + const struct axlf *xclbin = (const struct axlf *)buf; > > + void *section = NULL; > > + int err = 0; > > + u64 offset = 0; > > + u64 size = 0; > > + > > + err = xrt_xclbin_section_info(xclbin, kind, &offset, &size); > > + if (err) > > + return err; > > + > > + section = vmalloc(size); > > + if (!section) > > + return -ENOMEM; > > + > > + memcpy(section, ((const char *)xclbin) + offset, size); > > + > > + *data = section; > > a general comment > > for exported function checking the validity of the inputs in more important. > > here you assume **data is valid, really you should check. > > > + if (len) > > + *len = size; > len setting being optional, needs to be in the *.h comment > > + > > + return 0; > > +} > > +EXPORT_SYMBOL_GPL(xrt_xclbin_get_section); > > + > Instead of allocating new memory and making copies of bits of *data > > why not have the points reference data ? > > The size operations look like translating big endian data to little endian. > > This will break on a big endian host. > > > +/* parse bitstream header */ > > +int xrt_xclbin_parse_bitstream_header(const unsigned char *data, > > + unsigned int size, > > + struct hw_icap_bit_header *header) > > +{ > > + unsigned int index; > > + unsigned int len; > > + unsigned int tmp; > > + unsigned int i; > > + > > + memset(header, 0, sizeof(*header)); > > + /* Start Index at start of bitstream */ > > + index = 0; > > + > > + /* Initialize HeaderLength. If header returned early inidicates > > + * failure. > > This side effect should be documented in the *.h comment. > > Also the multi line comment is a bit weird, not sure if it is ok > > > + */ > > + header->header_length = XHI_BIT_HEADER_FAILURE; > > + > > + /* Get "Magic" length */ > > + header->magic_length = xhi_data_and_inc(data, &index, size); > > + header->magic_length = (header->magic_length << 8) | xhi_data_and_inc(data, &index, size); > > + > > + /* Read in "magic" */ > > + for (i = 0; i < header->magic_length - 1; i++) { > > + tmp = xhi_data_and_inc(data, &index, size); > > + if (i % 2 == 0 && tmp != XHI_EVEN_MAGIC_BYTE) if !(i % 2) ... > > + return -1; /* INVALID_FILE_HEADER_ERROR */ > > + > > + if (i % 2 == 1 && tmp != XHI_ODD_MAGIC_BYTE) > > + return -1; /* INVALID_FILE_HEADER_ERROR */ > > + } > > + > > + /* Read null end of magic data. */ > > + tmp = xhi_data_and_inc(data, &index, size); > > + > > + /* Read 0x01 (short) */ > > + tmp = xhi_data_and_inc(data, &index, size); > > + tmp = (tmp << 8) | xhi_data_and_inc(data, &index, size); > > + > > + /* Check the "0x01" half word */ > > + if (tmp != 0x01) > > + return -1; /* INVALID_FILE_HEADER_ERROR */ > > + > > + /* Read 'a' */ > > + tmp = xhi_data_and_inc(data, &index, size); > > + if (tmp != 'a') > > + return -1; /* INVALID_FILE_HEADER_ERROR */ > > + > > + /* Get Design Name length */ > > + len = xhi_data_and_inc(data, &index, size); > > + len = (len << 8) | xhi_data_and_inc(data, &index, size); > > + > > + /* allocate space for design name and final null character. */ > > + header->design_name = vmalloc(len); > > + if (!header->design_name) > > + return -ENOMEM; > > + > > + /* Read in Design Name */ > > + for (i = 0; i < len; i++) > > + header->design_name[i] = xhi_data_and_inc(data, &index, size); > > + > > + if (header->design_name[len - 1] != '\0') > > + return -1; > > + > > + header->version = strstr(header->design_name, "Version=") + strlen("Version="); > > + > > + /* Read 'b' */ > > + tmp = xhi_data_and_inc(data, &index, size); > > + if (tmp != 'b') > > + return -1; /* INVALID_FILE_HEADER_ERROR */ > > + > > + /* Get Part Name length */ > > + len = xhi_data_and_inc(data, &index, size); > > + len = (len << 8) | xhi_data_and_inc(data, &index, size); > > + > > + /* allocate space for part name and final null character. */ > > + header->part_name = vmalloc(len); > > + if (!header->part_name) > > + return -ENOMEM; > > + > > + /* Read in part name */ > > + for (i = 0; i < len; i++) > > + header->part_name[i] = xhi_data_and_inc(data, &index, size); > > + > > + if (header->part_name[len - 1] != '\0') > > + return -1; > > + > > + /* Read 'c' */ > > + tmp = xhi_data_and_inc(data, &index, size); > > + if (tmp != 'c') > > + return -1; /* INVALID_FILE_HEADER_ERROR */ > > + > > + /* Get date length */ > > + len = xhi_data_and_inc(data, &index, size); > > + len = (len << 8) | xhi_data_and_inc(data, &index, size); > > + > > + /* allocate space for date and final null character. */ > > + header->date = vmalloc(len); > > + if (!header->date) > > + return -ENOMEM; > > + > > + /* Read in date name */ > > + for (i = 0; i < len; i++) > > + header->date[i] = xhi_data_and_inc(data, &index, size); > > + > > + if (header->date[len - 1] != '\0') > > + return -1; > generally -EINVAL is more meaningful than -1 > > + > > + /* Read 'd' */ > > + tmp = xhi_data_and_inc(data, &index, size); > > + if (tmp != 'd') > > + return -1; /* INVALID_FILE_HEADER_ERROR */ > > + > > + /* Get time length */ > > + len = xhi_data_and_inc(data, &index, size); > > + len = (len << 8) | xhi_data_and_inc(data, &index, size); > > + > > + /* allocate space for time and final null character. */ > > + header->time = vmalloc(len); > > + if (!header->time) > > + return -ENOMEM; > > + > > + /* Read in time name */ > > + for (i = 0; i < len; i++) > > + header->time[i] = xhi_data_and_inc(data, &index, size); > > + > > + if (header->time[len - 1] != '\0') > > + return -1; > > + > > + /* Read 'e' */ > > + tmp = xhi_data_and_inc(data, &index, size); > > + if (tmp != 'e') > > + return -1; /* INVALID_FILE_HEADER_ERROR */ > > + > > + /* Get byte length of bitstream */ > > + header->bitstream_length = xhi_data_and_inc(data, &index, size); > > + header->bitstream_length = (header->bitstream_length << 8) | > > + xhi_data_and_inc(data, &index, size); > > + header->bitstream_length = (header->bitstream_length << 8) | > > + xhi_data_and_inc(data, &index, size); > > + header->bitstream_length = (header->bitstream_length << 8) | > > + xhi_data_and_inc(data, &index, size); > > generally a problem > > This is confusing, collect the bytes in a temp[] and construct the header->bitstream_length in on statement. > > This is a case where xhi_data_and_inc return is not checked and if it failed could blow up later. > > > + > > + header->header_length = index; > > index is not a good variable name if it going to be stored as a length. > > consider changing it to something like current_length. > > > + > > + return 0; > > +} > > +EXPORT_SYMBOL_GPL(xrt_xclbin_parse_bitstream_header); > > + > > +void xrt_xclbin_free_header(struct hw_icap_bit_header *header) > > +{ > > + vfree(header->design_name); > > + vfree(header->part_name); > > + vfree(header->date); > > + vfree(header->time); > missing header->version > > +} > > +EXPORT_SYMBOL_GPL(xrt_xclbin_free_header); > > + > > +struct xrt_clock_desc { > > + char *clock_ep_name; > > + u32 clock_xclbin_type; > > + char *clkfreq_ep_name; > > +} clock_desc[] = { > > + { > > + .clock_ep_name = XRT_MD_NODE_CLK_KERNEL1, > > + .clock_xclbin_type = CT_DATA, > > + .clkfreq_ep_name = XRT_MD_NODE_CLKFREQ_K1, > > + }, > > + { > > + .clock_ep_name = XRT_MD_NODE_CLK_KERNEL2, > > + .clock_xclbin_type = CT_KERNEL, > > + .clkfreq_ep_name = XRT_MD_NODE_CLKFREQ_K2, > > + }, > > + { > > + .clock_ep_name = XRT_MD_NODE_CLK_KERNEL3, > > + .clock_xclbin_type = CT_SYSTEM, > > + .clkfreq_ep_name = XRT_MD_NODE_CLKFREQ_HBM, > > + }, > > +}; > > + > > +const char *xrt_clock_type2epname(enum CLOCK_TYPE type) > > +{ > > + int i; > > + > > + for (i = 0; i < ARRAY_SIZE(clock_desc); i++) { > > + if (clock_desc[i].clock_xclbin_type == type) > > + return clock_desc[i].clock_ep_name; > > + } > > + return NULL; > > +} > > +EXPORT_SYMBOL_GPL(xrt_clock_type2epname); > > What is clock stuff doing in xclbin ? > > I think clock needs its own file > > > + > > +static const char *clock_type2clkfreq_name(u32 type) > > +{ > > + int i; > > + > > + for (i = 0; i < ARRAY_SIZE(clock_desc); i++) { > > + if (clock_desc[i].clock_xclbin_type == type) > > + return clock_desc[i].clkfreq_ep_name; > > + } > > + return NULL; > > +} > > + > > +static int xrt_xclbin_add_clock_metadata(struct device *dev, > > + const struct axlf *xclbin, > > + char *dtb) > > +{ > > + int i; > > + u16 freq; > > + struct clock_freq_topology *clock_topo; > > + int rc = xrt_xclbin_get_section(xclbin, CLOCK_FREQ_TOPOLOGY, > > + (void **)&clock_topo, NULL); > > + > > + if (rc) > > + return 0; > failing is ok ? > > + > > + for (i = 0; i < clock_topo->m_count; i++) { > > + u8 type = clock_topo->m_clock_freq[i].m_type; > > + const char *ep_name = xrt_clock_type2epname(type); > > + const char *counter_name = clock_type2clkfreq_name(type); > > + > > + if (!ep_name || !counter_name) > > + continue; > > + > > + freq = cpu_to_be16(clock_topo->m_clock_freq[i].m_freq_Mhz); > > + rc = xrt_md_set_prop(dev, dtb, ep_name, NULL, XRT_MD_PROP_CLK_FREQ, > > + &freq, sizeof(freq)); > > + if (rc) > > + break; > > + > > + rc = xrt_md_set_prop(dev, dtb, ep_name, NULL, XRT_MD_PROP_CLK_CNT, > > + counter_name, strlen(counter_name) + 1); > > + if (rc) > > + break; > Failing in a loop, why isn't there some cleanup of the *set_prop() calls ? > > + } > > + > > + vfree(clock_topo); > > + > > + return rc; > > +} > > + > > +int xrt_xclbin_get_metadata(struct device *dev, const struct axlf *xclbin, char **dtb) > > +{ > > + char *md = NULL, *newmd = NULL; > > + u64 len; > *dtb = NULL; > > + int rc = xrt_xclbin_get_section(xclbin, PARTITION_METADATA, > > + (void **)&md, &len); > > + > > + if (rc) > > + goto done; > > + > > + /* Sanity check the dtb section. */ > > + if (xrt_md_size(dev, md) > len) { > > + rc = -EINVAL; > > + goto done; > > + } > > + > > + newmd = xrt_md_dup(dev, md); > > + if (!newmd) { > > + rc = -EFAULT; > > + goto done; > > + } > > + /* Convert various needed xclbin sections into dtb. */ > > + rc = xrt_xclbin_add_clock_metadata(dev, xclbin, newmd); > > newmd is only valid here, but the above error handling jump here. change this to > > if (!rc) > > *dtb = newmd > > else > > vfree(newmd) > > done: > > vfree(md) > > return rc; > > > + > > +done: > > + if (rc == 0) > > + *dtb = newmd; > > + else > > + vfree(newmd); > > + vfree(md); > > + return rc; > > +} > > +EXPORT_SYMBOL_GPL(xrt_xclbin_get_metadata); > > diff --git a/include/uapi/linux/xrt/xclbin.h b/include/uapi/linux/xrt/xclbin.h > > new file mode 100644 > > index 000000000000..53f140123ef1 > > --- /dev/null > > +++ b/include/uapi/linux/xrt/xclbin.h > > @@ -0,0 +1,408 @@ > > +/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */ > > +/* > > + * Xilinx FPGA compiled binary container format > > + * > > + * Copyright (C) 2015-2021, Xilinx Inc > > + */ > > + > > +#ifndef _XCLBIN_H_ > > +#define _XCLBIN_H_ > > + > > +#ifdef _WIN32 > > WIN32 ? > > Only 1 other header has this ifdef > > > + #include <cstdint> > > + #include <algorithm> > c++ is being assumed for windows > > + #include "windows/uuid.h" > thank you for not including windows.h ;) > > +#else > > + #if defined(__KERNEL__) > > + #include <linux/types.h> > > + #include <linux/uuid.h> > > + #include <linux/version.h> > > + #elif defined(__cplusplus) > > + #include <cstdlib> > > + #include <cstdint> > > + #include <algorithm> > > + #include <uuid/uuid.h> > > + #else > > + #include <stdlib.h> > > + #include <stdint.h> > > + #include <uuid/uuid.h> > > + #endif > > +#endif Tbh, not a big fan of this ... > > + > > Review these includes, some could be convenience includes. > > ex/ linux/version.h with no obvious use of version macros. > > struct axlf_header { > + uint64_t m_length; /* Total size of the xclbin file */ > .. snip .. > + union { > + char m_next_axlf[16]; /* Name of next xclbin file */ > + /* in the daisy chain */ > + uuid_t uuid; /* uuid of this xclbin*/ > + }; > > As mentioned in an earlier patch, if uuid_t is larger than 16 bytes, axlf_header breaks. > while it is convenient to have this type here, it would be better this access was handled in another way. > Maybe a host specific function. > > I also do not see a pragma pack, usually this is set of 1 so the compiler does not shuffle elements, increase size etc. > > > +#ifdef __cplusplus > > +extern "C" { > > +#endif > > + > > +/** > > + * DOC: Container format for Xilinx FPGA images > > + * The container stores bitstreams, metadata and firmware images. > > + * xclbin/xsabin is ELF-like binary container format. It is structured > is an ELF-like file format. It is a structured > > + * series of sections. There is a file header followed by several section > > + * headers which is followed by sections. A section header points to an > > + * actual section. There is an optional signature at the end. The > > + * following figure illustrates a typical xclbin: > > + * > > + * +---------------------+ > > + * | | > > + * | HEADER | > > + * +---------------------+ > > + * | SECTION HEADER | > > + * | | > > + * +---------------------+ > > + * | ... | > > + * | | > > + * +---------------------+ > > + * | SECTION HEADER | > > + * | | > > + * +---------------------+ > > + * | SECTION | > > + * | | > > + * +---------------------+ > > + * | ... | > > + * | | > > + * +---------------------+ > > + * | SECTION | > > + * | | > > + * +---------------------+ > > + * | SIGNATURE | > > + * | (OPTIONAL) | > > + * +---------------------+ > > This ascii art is a mixture of tabs and spaces, for someone with tab = 2 spaces, this will look messed up. > > convert the tabs to spaces > > > + */ > > + > > +enum XCLBIN_MODE { > > + XCLBIN_FLAT, > > generally > > all enums used in a file format should be initialized. > > This likely should be > > XCLBIN_FLAT = 0, > > > + XCLBIN_PR, > > + XCLBIN_TANDEM_STAGE2, > > + XCLBIN_TANDEM_STAGE2_WITH_PR, > > + XCLBIN_HW_EMU, > > + XCLBIN_SW_EMU, > > + XCLBIN_MODE_MAX > > +}; > > + > > +enum axlf_section_kind { > > + BITSTREAM = 0, > > + CLEARING_BITSTREAM, > > + EMBEDDED_METADATA, > > + FIRMWARE, > > + DEBUG_DATA, > > + SCHED_FIRMWARE, > > + MEM_TOPOLOGY, > > + CONNECTIVITY, > > + IP_LAYOUT, > > + DEBUG_IP_LAYOUT, > > + DESIGN_CHECK_POINT, > > + CLOCK_FREQ_TOPOLOGY, > > + MCS, > > + BMC, > > + BUILD_METADATA, > > + KEYVALUE_METADATA, > > + USER_METADATA, > > + DNA_CERTIFICATE, > > + PDI, > > + BITSTREAM_PARTIAL_PDI, > > + PARTITION_METADATA, > > + EMULATION_DATA, > > + SYSTEM_METADATA, > > + SOFT_KERNEL, > > + ASK_FLASH, > > + AIE_METADATA, > > + ASK_GROUP_TOPOLOGY, > > + ASK_GROUP_CONNECTIVITY > > +}; > > + > > +enum MEM_TYPE { > > + MEM_DDR3, > > + MEM_DDR4, > > + MEM_DRAM, > > + MEM_STREAMING, > > + MEM_PREALLOCATED_GLOB, > > + MEM_ARE, > > + MEM_HBM, > > + MEM_BRAM, > > + MEM_URAM, > > + MEM_STREAMING_CONNECTION > > +}; > > + > > +enum IP_TYPE { > > + IP_MB = 0, > > + IP_KERNEL, > > + IP_DNASC, > > + IP_DDR4_CONTROLLER, > > + IP_MEM_DDR4, > > + IP_MEM_HBM > > +}; > > + > > +struct axlf_section_header { > > + uint32_t m_sectionKind; /* Section type */ > > + char m_sectionName[16]; /* Examples: "stage2", "clear1", */ > > + /* "clear2", "ocl1", "ocl2, */ > > + /* "ublaze", "sched" */ > > + uint64_t m_sectionOffset; /* File offset of section data */ > > + uint64_t m_sectionSize; /* Size of section data */ > > +}; > > + > > +struct axlf_header { > > + uint64_t m_length; /* Total size of the xclbin file */ > > + uint64_t m_timeStamp; /* Number of seconds since epoch */ > > + /* when xclbin was created */ > > + uint64_t m_featureRomTimeStamp; /* TimeSinceEpoch of the featureRom */ > > + uint16_t m_versionPatch; /* Patch Version */ > > + uint8_t m_versionMajor; /* Major Version - Version: 2.1.0*/ > i did not see the version checked earlier, which one is expected ? > > + uint8_t m_versionMinor; /* Minor Version */ > > + uint32_t m_mode; /* XCLBIN_MODE */ > > + union { > > + struct { > > + uint64_t m_platformId; /* 64 bit platform ID: */ > > + /* vendor-device-subvendor-subdev */ > > + uint64_t m_featureId; /* 64 bit feature id */ > > + } rom; > > + unsigned char rom_uuid[16]; /* feature ROM UUID for which */ > > + /* this xclbin was generated */ > > + }; > > + unsigned char m_platformVBNV[64]; /* e.g. */ > what is VBNV? > > + /* xilinx:xil-accel-rd-ku115:4ddr-xpr:3.4: null terminated */ > > + union { > > + char m_next_axlf[16]; /* Name of next xclbin file */ > > + /* in the daisy chain */ > > + uuid_t uuid; /* uuid of this xclbin*/ > > + }; > > + char m_debug_bin[16]; /* Name of binary with debug */ > > + /* information */ > > + uint32_t m_numSections; /* Number of section headers */ > > +}; > > + > > +struct axlf { > > + char m_magic[8]; /* Should be "xclbin2\0" */ > > + int32_t m_signature_length; /* Length of the signature. */ > > + /* -1 indicates no signature */ > > + unsigned char reserved[28]; /* Note: Initialized to 0xFFs */ > > + > > + unsigned char m_keyBlock[256]; /* Signature for validation */ > > + /* of binary */ > > + uint64_t m_uniqueId; /* axlf's uniqueId, use it to */ > > + /* skip redownload etc */ > > + struct axlf_header m_header; /* Inline header */ > > + struct axlf_section_header m_sections[1]; /* One or more section */ > > + /* headers follow */ > > +}; > > + > > +/* bitstream information */ > > +struct xlnx_bitstream { > > + uint8_t m_freq[8]; > > + char bits[1]; > > +}; > > + > > +/**** MEMORY TOPOLOGY SECTION ****/ > > +struct mem_data { > > + uint8_t m_type; /* enum corresponding to mem_type. */ > > + uint8_t m_used; /* if 0 this bank is not present */ > > + union { > > + uint64_t m_size; /* if mem_type DDR, then size in KB; */ > > + uint64_t route_id; /* if streaming then "route_id" */ > > + }; > > + union { > > + uint64_t m_base_address;/* if DDR then the base address; */ > > + uint64_t flow_id; /* if streaming then "flow id" */ > > + }; > > + unsigned char m_tag[16]; /* DDR: BANK0,1,2,3, has to be null */ > > + /* terminated; if streaming then stream0, 1 etc */ > > +}; > > + > > +struct mem_topology { > > + int32_t m_count; /* Number of mem_data */ > > + struct mem_data m_mem_data[1]; /* Should be sorted on mem_type */ > > +}; > > + > > +/**** CONNECTIVITY SECTION ****/ > > +/* Connectivity of each argument of Kernel. It will be in terms of argument > > This section does not make sense. > > Likely you mean some algorithm kernel, rather than the linux kernel. > > > + * index associated. For associating kernel instances with arguments and > > + * banks, start at the connectivity section. Using the m_ip_layout_index > > + * access the ip_data.m_name. Now we can associate this kernel instance > > + * with its original kernel name and get the connectivity as well. This > > + * enables us to form related groups of kernel instances. > > + */ > > + > > +struct connection { > > + int32_t arg_index; /* From 0 to n, may not be contiguous as scalars */ > > + /* skipped */ > > + int32_t m_ip_layout_index; /* index into the ip_layout section. */ > > + /* ip_layout.m_ip_data[index].m_type == IP_KERNEL */ > > + int32_t mem_data_index; /* index of the m_mem_data . Flag error is */ > > + /* m_used false. */ > > +}; > > + > > +struct connectivity { > > + int32_t m_count; > > + struct connection m_connection[1]; > > +}; > > + > > +/**** IP_LAYOUT SECTION ****/ > > + > > +/* IP Kernel */ > > +#define IP_INT_ENABLE_MASK 0x0001 > > +#define IP_INTERRUPT_ID_MASK 0x00FE > > +#define IP_INTERRUPT_ID_SHIFT 0x1 > > + > > +enum IP_CONTROL { > > + AP_CTRL_HS = 0, > > + AP_CTRL_CHAIN = 1, > > + AP_CTRL_NONE = 2, > > + AP_CTRL_ME = 3, > > + ACCEL_ADAPTER = 4 > assigning beyond the first is not necessary unless there are dups or gaps > > +}; > > + > > +#define IP_CONTROL_MASK 0xFF00 > > +#define IP_CONTROL_SHIFT 0x8 > > + > > +/* IPs on AXI lite - their types, names, and base addresses.*/ > > +struct ip_data { > > + uint32_t m_type; /* map to IP_TYPE enum */ > > + union { > > + uint32_t properties; /* Default: 32-bits to indicate ip */ > > + /* specific property. */ > > + /* m_type: IP_KERNEL > > + * m_int_enable : Bit - 0x0000_0001; > > + * m_interrupt_id : Bits - 0x0000_00FE; > > + * m_ip_control : Bits = 0x0000_FF00; > > + */ > > + struct { /* m_type: IP_MEM_* */ > > + uint16_t m_index; > > + uint8_t m_pc_index; > > + uint8_t unused; > > + } indices; > > + }; > > + uint64_t m_base_address; > > + uint8_t m_name[64]; /* eg Kernel name corresponding to KERNEL */ > > + /* instance, can embed CU name in future. */ > > +}; > > + > > +struct ip_layout { > > + int32_t m_count; > > + struct ip_data m_ip_data[1]; /* All the ip_data needs to be sorted */ > > + /* by m_base_address. */ > > general > > doing the bla[1] for c++ ? > > Tom > > > +}; > > + > > +/*** Debug IP section layout ****/ > > +enum DEBUG_IP_TYPE { > > + UNDEFINED = 0, > > + LAPC, > > + ILA, > > + AXI_MM_MONITOR, > > + AXI_TRACE_FUNNEL, > > + AXI_MONITOR_FIFO_LITE, > > + AXI_MONITOR_FIFO_FULL, > > + ACCEL_MONITOR, > > + AXI_STREAM_MONITOR, > > + AXI_STREAM_PROTOCOL_CHECKER, > > + TRACE_S2MM, > > + AXI_DMA, > > + TRACE_S2MM_FULL > > +}; > > + > > +struct debug_ip_data { > > + uint8_t m_type; /* type of enum DEBUG_IP_TYPE */ > > + uint8_t m_index_lowbyte; > > + uint8_t m_properties; > > + uint8_t m_major; > > + uint8_t m_minor; > > + uint8_t m_index_highbyte; > > + uint8_t m_reserved[2]; > > + uint64_t m_base_address; > > + char m_name[128]; > > +}; > > + > > +struct debug_ip_layout { > > + uint16_t m_count; > > + struct debug_ip_data m_debug_ip_data[1]; > > +}; > > + > > +/* Supported clock frequency types */ > > +enum CLOCK_TYPE { > > + CT_UNUSED = 0, /* Initialized value */ > > + CT_DATA = 1, /* Data clock */ > > + CT_KERNEL = 2, /* Kernel clock */ > > + CT_SYSTEM = 3 /* System Clock */ > > +}; > > + > > +/* Clock Frequency Entry */ > > +struct clock_freq { > > + uint16_t m_freq_Mhz; /* Frequency in MHz */ > > + uint8_t m_type; /* Clock type (enum CLOCK_TYPE) */ > > + uint8_t m_unused[5]; /* Not used - padding */ > > + char m_name[128]; /* Clock Name */ > > +}; > > + > > +/* Clock frequency section */ > > +struct clock_freq_topology { > > + int16_t m_count; /* Number of entries */ > > + struct clock_freq m_clock_freq[1]; /* Clock array */ > > +}; > > + > > +/* Supported MCS file types */ > > +enum MCS_TYPE { > > + MCS_UNKNOWN = 0, /* Initialized value */ > > + MCS_PRIMARY = 1, /* The primary mcs file data */ > > + MCS_SECONDARY = 2, /* The secondary mcs file data */ > > +}; > > + > > +/* One chunk of MCS data */ > > +struct mcs_chunk { > > + uint8_t m_type; /* MCS data type */ just call them type, unused, offset. Drop the m_* > > + uint8_t m_unused[7]; /* padding */ > > + uint64_t m_offset; /* data offset from the start of */ > > + /* the section */ > > + uint64_t m_size; /* data size */ > > +}; > > + > > +/* MCS data section */ > > +struct mcs { > > + int8_t m_count; /* Number of chunks */ > > + int8_t m_unused[7]; /* padding */ > > + struct mcs_chunk m_chunk[1]; /* MCS chunks followed by data */ > > +}; > > + > > +/* bmc data section */ > > +struct bmc { > > + uint64_t m_offset; /* data offset from the start of */ > > + /* the section */ > > + uint64_t m_size; /* data size (bytes) */ > > + char m_image_name[64]; /* Name of the image */ > > + /* (e.g., MSP432P401R) */ > > + char m_device_name[64]; /* Device ID (e.g., VCU1525) */ > > + char m_version[64]; > > + char m_md5value[33]; /* MD5 Expected Value */ > > + /* (e.g., 56027182079c0bd621761b7dab5a27ca)*/ > > + char m_padding[7]; /* Padding */ > > +}; > > + > > +/* soft kernel data section, used by classic driver */ > > +struct soft_kernel { > > + /** Prefix Syntax: > > + * mpo - member, pointer, offset > > + * This variable represents a zero terminated string > > + * that is offseted from the beginning of the section. > > + * The pointer to access the string is initialized as follows: > > + * char * pCharString = (address_of_section) + (mpo value) > > + */ > > + uint32_t mpo_name; /* Name of the soft kernel */ > > + uint32_t m_image_offset; /* Image offset */ > > + uint32_t m_image_size; /* Image size */ > > + uint32_t mpo_version; /* Version */ > > + uint32_t mpo_md5_value; /* MD5 checksum */ > > + uint32_t mpo_symbol_name; /* Symbol name */ > > + uint32_t m_num_instances; /* Number of instances */ > > + uint8_t padding[36]; /* Reserved for future use */ > > + uint8_t reservedExt[16]; /* Reserved for future extended data */ > > +}; > > + > > +enum CHECKSUM_TYPE { > > + CST_UNKNOWN = 0, > > + CST_SDBM = 1, > > + CST_LAST > > +}; > > + > > +#ifdef __cplusplus > > +} > > +#endif > > + > > +#endif > I'll take a closer look, these were just random things I bumped into. - Moritz
On Sun, Feb 21, 2021 at 06:57:31AM -0800, Tom Rix wrote: > As I am looking through the files, I have this comment. > > fpga/ is currently a single directory, while files could be organized in subdirectories like > > dfl/pci.c > > instead have the possible subdir name as a prefix to the filename. > > dfl-pci.c > > For consistency, > > xrt/metadata/metadata.c > > should be > > xrt-metadata.c Agreed. Keep the prefix. > > Likewise the build infra needs to integrated within the existing files fpga/Kconfig,Makefile > > This is a bigish refactor, so let's get a second opinion. In what sense? You mean adding a subdirectory? Maybe something like this drivers/fpga - dfl/ - xilinx/ - intel/ - lattice/ - xrt/ ... would generally make sense. We didn't have enough drivers to prioritize that yet, but we can look into it. > > Moritz ? > > On 2/17/21 10:40 PM, Lizhi Hou wrote: > > Update fpga Kconfig/Makefile and add Kconfig/Makefile for new drivers. > Expand the comment, there are several new configs that could use an explanation > > > > Signed-off-by: Sonal Santan <sonal.santan@xilinx.com> > > Signed-off-by: Max Zhen <max.zhen@xilinx.com> > > Signed-off-by: Lizhi Hou <lizhih@xilinx.com> > > --- > > MAINTAINERS | 11 +++++++++++ > > drivers/Makefile | 1 + > > drivers/fpga/Kconfig | 2 ++ > > drivers/fpga/Makefile | 4 ++++ > > drivers/fpga/xrt/Kconfig | 8 ++++++++ > > drivers/fpga/xrt/lib/Kconfig | 16 ++++++++++++++++ > > drivers/fpga/xrt/lib/Makefile | 30 ++++++++++++++++++++++++++++++ > > drivers/fpga/xrt/metadata/Kconfig | 12 ++++++++++++ > > drivers/fpga/xrt/metadata/Makefile | 16 ++++++++++++++++ > > drivers/fpga/xrt/mgmt/Kconfig | 15 +++++++++++++++ > > drivers/fpga/xrt/mgmt/Makefile | 19 +++++++++++++++++++ > > 11 files changed, 134 insertions(+) > > create mode 100644 drivers/fpga/xrt/Kconfig > > create mode 100644 drivers/fpga/xrt/lib/Kconfig > > create mode 100644 drivers/fpga/xrt/lib/Makefile > > create mode 100644 drivers/fpga/xrt/metadata/Kconfig > > create mode 100644 drivers/fpga/xrt/metadata/Makefile > > create mode 100644 drivers/fpga/xrt/mgmt/Kconfig > > create mode 100644 drivers/fpga/xrt/mgmt/Makefile > > > > diff --git a/MAINTAINERS b/MAINTAINERS > > index d3e847f7f3dc..e6e147c2454c 100644 > > --- a/MAINTAINERS > > +++ b/MAINTAINERS > > @@ -6973,6 +6973,17 @@ F: Documentation/fpga/ > > F: drivers/fpga/ > > F: include/linux/fpga/ > > > > +FPGA XRT DRIVERS > > +M: Lizhi Hou <lizhi.hou@xilinx.com> > > +R: Max Zhen <max.zhen@xilinx.com> > > +R: Sonal Santan <sonal.santan@xilinx.com> > > +L: linux-fpga@vger.kernel.org > > +S: Maintained > > +W: https://github.com/Xilinx/XRT > > +F: Documentation/fpga/xrt.rst > > +F: drivers/fpga/xrt/ > > +F: include/uapi/linux/xrt/ > > + > > FPU EMULATOR > > M: Bill Metzenthen <billm@melbpc.org.au> > > S: Maintained > > diff --git a/drivers/Makefile b/drivers/Makefile > > index fd11b9ac4cc3..e03912af8e48 100644 > > --- a/drivers/Makefile > > +++ b/drivers/Makefile > > @@ -178,6 +178,7 @@ obj-$(CONFIG_STM) += hwtracing/stm/ > > obj-$(CONFIG_ANDROID) += android/ > > obj-$(CONFIG_NVMEM) += nvmem/ > > obj-$(CONFIG_FPGA) += fpga/ > > +obj-y += fpga/xrt/metadata/ > > This is wrong. > > Move metadata building to fpga/ Makefile and pick an appropriate config, not just 'obj-y' > > > obj-$(CONFIG_FSI) += fsi/ > > obj-$(CONFIG_TEE) += tee/ > > obj-$(CONFIG_MULTIPLEXER) += mux/ > > diff --git a/drivers/fpga/Kconfig b/drivers/fpga/Kconfig > > index 5645226ca3ce..aeca635b1f25 100644 > > --- a/drivers/fpga/Kconfig > > +++ b/drivers/fpga/Kconfig > > @@ -216,4 +216,6 @@ config FPGA_MGR_ZYNQMP_FPGA > > to configure the programmable logic(PL) through PS > > on ZynqMP SoC. > > > > +source "drivers/fpga/xrt/Kconfig" > > + > > endif # FPGA > > diff --git a/drivers/fpga/Makefile b/drivers/fpga/Makefile > > index d8e21dfc6778..2b4453ff7c52 100644 > > --- a/drivers/fpga/Makefile > > +++ b/drivers/fpga/Makefile > > @@ -46,3 +46,7 @@ dfl-afu-objs += dfl-afu-error.o > > > > # Drivers for FPGAs which implement DFL > > obj-$(CONFIG_FPGA_DFL_PCI) += dfl-pci.o > > + > > +# XRT drivers for Alveo > > +obj-$(CONFIG_FPGA_XRT_LIB) += xrt/lib/ > > +obj-$(CONFIG_FPGA_XRT_XMGMT) += xrt/mgmt/ > > I don't see how mgmnt would work without lib. If that is so > > these configs could collapse to CONFIG_FPGA_XRT > > > diff --git a/drivers/fpga/xrt/Kconfig b/drivers/fpga/xrt/Kconfig > > new file mode 100644 > > index 000000000000..0e2c59589ddd > > --- /dev/null > > +++ b/drivers/fpga/xrt/Kconfig > > @@ -0,0 +1,8 @@ > > +# SPDX-License-Identifier: GPL-2.0-only > > +# > > +# Xilinx Alveo FPGA device configuration > > +# > > + > > +source "drivers/fpga/xrt/metadata/Kconfig" > > +source "drivers/fpga/xrt/lib/Kconfig" > > +source "drivers/fpga/xrt/mgmt/Kconfig" > > diff --git a/drivers/fpga/xrt/lib/Kconfig b/drivers/fpga/xrt/lib/Kconfig > > new file mode 100644 > > index 000000000000..eed5cb73f5e2 > > --- /dev/null > > +++ b/drivers/fpga/xrt/lib/Kconfig > > @@ -0,0 +1,16 @@ > > +# SPDX-License-Identifier: GPL-2.0-only > > +# > > +# XRT Alveo FPGA device configuration > > +# > > + > > +config FPGA_XRT_LIB > > + tristate "XRT Alveo Driver Library" > > + depends on HWMON && PCI && HAS_IOMEM > > + select FPGA_XRT_METADATA > > + help > > + Select this option to enable Xilinx XRT Alveo driver library. This > > + library is core infrastructure of XRT Alveo FPGA drivers which > > + provides functions for working with device nodes, iteration and > > + lookup of platform devices, common interfaces for platform devices, > > + plumbing of function call and ioctls between platform devices and > > + parent partitions. > > diff --git a/drivers/fpga/xrt/lib/Makefile b/drivers/fpga/xrt/lib/Makefile > > new file mode 100644 > > index 000000000000..5641231b2a36 > > --- /dev/null > > +++ b/drivers/fpga/xrt/lib/Makefile > > @@ -0,0 +1,30 @@ > > +# SPDX-License-Identifier: GPL-2.0 > > +# > > +# Copyright (C) 2020-2021 Xilinx, Inc. All rights reserved. > > +# > > +# Authors: Sonal.Santan@xilinx.com > > +# > > + > > +FULL_XRT_PATH=$(srctree)/$(src)/.. > > +FULL_DTC_PATH=$(srctree)/scripts/dtc/libfdt > > + > > +obj-$(CONFIG_FPGA_XRT_LIB) += xrt-lib.o > > + > > +xrt-lib-objs := \ > > + main.o \ > > + xroot.o \ > > + xclbin.o \ > > + subdev.o \ > > + cdev.o \ > > + group.o \ > > + xleaf/vsec.o \ > > + xleaf/axigate.o \ > > + xleaf/devctl.o \ > > + xleaf/icap.o \ > > + xleaf/clock.o \ > > + xleaf/clkfreq.o \ > > + xleaf/ucs.o \ > > + xleaf/calib.o \ > > + > > +ccflags-y := -I$(FULL_XRT_PATH)/include \ > > + -I$(FULL_DTC_PATH) > > diff --git a/drivers/fpga/xrt/metadata/Kconfig b/drivers/fpga/xrt/metadata/Kconfig > > new file mode 100644 > > index 000000000000..5012c9c6584d > > --- /dev/null > > +++ b/drivers/fpga/xrt/metadata/Kconfig > > @@ -0,0 +1,12 @@ > > +# SPDX-License-Identifier: GPL-2.0-only > > +# > > +# XRT Alveo FPGA device configuration > > +# > > + > > +config FPGA_XRT_METADATA > > + bool "XRT Alveo Driver Metadata Parser" > > + select LIBFDT > > + help > > + This option provides helper functions to parse Xilinx Alveo FPGA > > + firmware metadata. The metadata is in device tree format and XRT > and the XRT > > + driver uses it to discover HW subsystems behind PCIe BAR. > the HW > > diff --git a/drivers/fpga/xrt/metadata/Makefile b/drivers/fpga/xrt/metadata/Makefile > > new file mode 100644 > > index 000000000000..14f65ef1595c > > --- /dev/null > > +++ b/drivers/fpga/xrt/metadata/Makefile > > @@ -0,0 +1,16 @@ > > +# SPDX-License-Identifier: GPL-2.0 > > +# > > +# Copyright (C) 2020-2021 Xilinx, Inc. All rights reserved. > > +# > > +# Authors: Sonal.Santan@xilinx.com > > +# > > + > > +FULL_XRT_PATH=$(srctree)/$(src)/.. > > +FULL_DTC_PATH=$(srctree)/scripts/dtc/libfdt > > + > > +obj-$(CONFIG_FPGA_XRT_METADATA) += xrt-md.o > > + > > +xrt-md-objs := metadata.o > > + > > +ccflags-y := -I$(FULL_XRT_PATH)/include \ > > + -I$(FULL_DTC_PATH) > > diff --git a/drivers/fpga/xrt/mgmt/Kconfig b/drivers/fpga/xrt/mgmt/Kconfig > > new file mode 100644 > > index 000000000000..2b2a2c34685c > > --- /dev/null > > +++ b/drivers/fpga/xrt/mgmt/Kconfig > > @@ -0,0 +1,15 @@ > > +# SPDX-License-Identifier: GPL-2.0-only > > +# > > +# Xilinx XRT FPGA device configuration > > +# > > + > > +config FPGA_XRT_XMGMT > > + tristate "Xilinx Alveo Management Driver" > > + depends on HWMON && PCI && FPGA_XRT_LIB > > FPGA_XRT_LIB also depends on HWMON and PCI, so this could be minimized. > > Tom > > > + select FPGA_XRT_METADATA > > + select FPGA_BRIDGE > > + select FPGA_REGION > > + help > > + Select this option to enable XRT PCIe driver for Xilinx Alveo FPGA. > > + This driver provides interfaces for userspace application to access > > + Alveo FPGA device. > > diff --git a/drivers/fpga/xrt/mgmt/Makefile b/drivers/fpga/xrt/mgmt/Makefile > > new file mode 100644 > > index 000000000000..8051708c361c > > --- /dev/null > > +++ b/drivers/fpga/xrt/mgmt/Makefile > > @@ -0,0 +1,19 @@ > > +# SPDX-License-Identifier: GPL-2.0 > > +# > > +# Copyright (C) 2020-2021 Xilinx, Inc. All rights reserved. > > +# > > +# Authors: Sonal.Santan@xilinx.com > > +# > > + > > +FULL_XRT_PATH=$(srctree)/$(src)/.. > > +FULL_DTC_PATH=$(srctree)/scripts/dtc/libfdt > > + > > +obj-$(CONFIG_FPGA_XRT_XMGMT) += xmgmt.o > > + > > +xmgmt-objs := root.o \ > > + main.o \ > > + fmgr-drv.o \ > > + main-region.o > > + > > +ccflags-y := -I$(FULL_XRT_PATH)/include \ > > + -I$(FULL_DTC_PATH) > - Moritz
On Wed, Feb 17, 2021 at 10:40:13PM -0800, Lizhi Hou wrote: > Add ICAP driver. ICAP is a hardware function discovered by walking > firmware metadata. A platform device node will be created for it. > FPGA bitstream is written to hardware through ICAP. > > Signed-off-by: Sonal Santan <sonal.santan@xilinx.com> > Signed-off-by: Max Zhen <max.zhen@xilinx.com> > Signed-off-by: Lizhi Hou <lizhih@xilinx.com> > --- > drivers/fpga/xrt/include/xleaf/icap.h | 29 +++ > drivers/fpga/xrt/lib/xleaf/icap.c | 317 ++++++++++++++++++++++++++ > 2 files changed, 346 insertions(+) > create mode 100644 drivers/fpga/xrt/include/xleaf/icap.h > create mode 100644 drivers/fpga/xrt/lib/xleaf/icap.c > > diff --git a/drivers/fpga/xrt/include/xleaf/icap.h b/drivers/fpga/xrt/include/xleaf/icap.h > new file mode 100644 > index 000000000000..a14fc0ffa78f > --- /dev/null > +++ b/drivers/fpga/xrt/include/xleaf/icap.h > @@ -0,0 +1,29 @@ > +/* SPDX-License-Identifier: GPL-2.0 */ > +/* > + * Header file for XRT ICAP Leaf Driver > + * > + * Copyright (C) 2020-2021 Xilinx, Inc. > + * > + * Authors: > + * Lizhi Hou <Lizhi.Hou@xilinx.com> > + */ > + > +#ifndef _XRT_ICAP_H_ > +#define _XRT_ICAP_H_ > + > +#include "xleaf.h" > + > +/* > + * ICAP driver IOCTL calls. > + */ > +enum xrt_icap_ioctl_cmd { > + XRT_ICAP_WRITE = XRT_XLEAF_CUSTOM_BASE, /* See comments in xleaf.h */ > + XRT_ICAP_IDCODE, > +}; > + > +struct xrt_icap_ioctl_wr { > + void *xiiw_bit_data; > + u32 xiiw_data_len; > +}; > + > +#endif /* _XRT_ICAP_H_ */ > diff --git a/drivers/fpga/xrt/lib/xleaf/icap.c b/drivers/fpga/xrt/lib/xleaf/icap.c > new file mode 100644 > index 000000000000..0500a97bdef9 > --- /dev/null > +++ b/drivers/fpga/xrt/lib/xleaf/icap.c > @@ -0,0 +1,317 @@ > +// SPDX-License-Identifier: GPL-2.0 > +/* > + * Xilinx Alveo FPGA ICAP Driver > + * > + * Copyright (C) 2020-2021 Xilinx, Inc. > + * > + * Authors: > + * Lizhi Hou<Lizhi.Hou@xilinx.com> > + * Sonal Santan <sonals@xilinx.com> > + * Max Zhen <maxz@xilinx.com> > + */ > + > +#include <linux/mod_devicetable.h> > +#include <linux/platform_device.h> > +#include <linux/delay.h> > +#include <linux/device.h> > +#include <linux/io.h> > +#include "metadata.h" > +#include "xleaf.h" > +#include "xleaf/icap.h" > +#include "xclbin-helper.h" > + > +#define XRT_ICAP "xrt_icap" > + > +#define ICAP_ERR(icap, fmt, arg...) \ > + xrt_err((icap)->pdev, fmt "\n", ##arg) > +#define ICAP_WARN(icap, fmt, arg...) \ > + xrt_warn((icap)->pdev, fmt "\n", ##arg) > +#define ICAP_INFO(icap, fmt, arg...) \ > + xrt_info((icap)->pdev, fmt "\n", ##arg) > +#define ICAP_DBG(icap, fmt, arg...) \ > + xrt_dbg((icap)->pdev, fmt "\n", ##arg) Do we really need two layers of indirection here? What's wrong with dev_{info,dbg,...} ? > + > +/* > + * AXI-HWICAP IP register layout > + */ > +struct icap_reg { > + u32 ir_rsvd1[7]; > + u32 ir_gier; > + u32 ir_isr; > + u32 ir_rsvd2; > + u32 ir_ier; > + u32 ir_rsvd3[53]; > + u32 ir_wf; > + u32 ir_rf; > + u32 ir_sz; > + u32 ir_cr; > + u32 ir_sr; > + u32 ir_wfv; > + u32 ir_rfo; > + u32 ir_asr; > +} __packed; Can we make those #define and just use writel/readl() ? If you want more abstraction, use regmap.... > + > +struct icap { > + struct platform_device *pdev; > + struct icap_reg *icap_regs; > + struct mutex icap_lock; /* icap dev lock */ > + > + unsigned int idcode; > +}; > + > +static inline u32 reg_rd(void __iomem *reg) > +{ > + if (!reg) > + return -1; > + > + return ioread32(reg); > +} > + > +static inline void reg_wr(void __iomem *reg, u32 val) > +{ > + if (!reg) > + return; > + > + iowrite32(val, reg); > +} > + > +static int wait_for_done(struct icap *icap) > +{ > + u32 w; > + int i = 0; > + > + WARN_ON(!mutex_is_locked(&icap->icap_lock)); > + for (i = 0; i < 10; i++) { > + udelay(5); > + w = reg_rd(&icap->icap_regs->ir_sr); > + ICAP_INFO(icap, "XHWICAP_SR: %x", w); > + if (w & 0x5) > + return 0; > + } > + > + ICAP_ERR(icap, "bitstream download timeout"); > + return -ETIMEDOUT; > +} > + > +static int icap_write(struct icap *icap, const u32 *word_buf, int size) > +{ > + int i; > + u32 value = 0; > + > + for (i = 0; i < size; i++) { > + value = be32_to_cpu(word_buf[i]); > + reg_wr(&icap->icap_regs->ir_wf, value); > + } > + > + reg_wr(&icap->icap_regs->ir_cr, 0x1); > + > + for (i = 0; i < 20; i++) { > + value = reg_rd(&icap->icap_regs->ir_cr); > + if ((value & 0x1) == 0) > + return 0; > + ndelay(50); > + } > + > + ICAP_ERR(icap, "writing %d dwords timeout", size); > + return -EIO; > +} > + > +static int bitstream_helper(struct icap *icap, const u32 *word_buffer, > + u32 word_count) > +{ > + u32 remain_word; > + u32 word_written = 0; > + int wr_fifo_vacancy = 0; > + int err = 0; > + > + WARN_ON(!mutex_is_locked(&icap->icap_lock)); > + for (remain_word = word_count; remain_word > 0; > + remain_word -= word_written, word_buffer += word_written) { > + wr_fifo_vacancy = reg_rd(&icap->icap_regs->ir_wfv); > + if (wr_fifo_vacancy <= 0) { > + ICAP_ERR(icap, "no vacancy: %d", wr_fifo_vacancy); > + err = -EIO; > + break; > + } > + word_written = (wr_fifo_vacancy < remain_word) ? > + wr_fifo_vacancy : remain_word; > + if (icap_write(icap, word_buffer, word_written) != 0) { > + ICAP_ERR(icap, "write failed remain %d, written %d", > + remain_word, word_written); > + err = -EIO; > + break; > + } > + } > + > + return err; > +} > + > +static int icap_download(struct icap *icap, const char *buffer, > + unsigned long length) > +{ > + u32 num_chars_read = DMA_HWICAP_BITFILE_BUFFER_SIZE; > + u32 byte_read; > + int err = 0; > + > + mutex_lock(&icap->icap_lock); > + for (byte_read = 0; byte_read < length; byte_read += num_chars_read) { > + num_chars_read = length - byte_read; > + if (num_chars_read > DMA_HWICAP_BITFILE_BUFFER_SIZE) > + num_chars_read = DMA_HWICAP_BITFILE_BUFFER_SIZE; > + > + err = bitstream_helper(icap, (u32 *)buffer, num_chars_read / sizeof(u32)); > + if (err) > + goto failed; > + buffer += num_chars_read; > + } > + > + err = wait_for_done(icap); > + > +failed: > + mutex_unlock(&icap->icap_lock); > + > + return err; > +} > + > +/* > + * Run the following sequence of canned commands to obtain IDCODE of the FPGA > + */ > +static void icap_probe_chip(struct icap *icap) > +{ > + u32 w; > + > + w = reg_rd(&icap->icap_regs->ir_sr); > + w = reg_rd(&icap->icap_regs->ir_sr); > + reg_wr(&icap->icap_regs->ir_gier, 0x0); > + w = reg_rd(&icap->icap_regs->ir_wfv); > + reg_wr(&icap->icap_regs->ir_wf, 0xffffffff); > + reg_wr(&icap->icap_regs->ir_wf, 0xaa995566); > + reg_wr(&icap->icap_regs->ir_wf, 0x20000000); > + reg_wr(&icap->icap_regs->ir_wf, 0x20000000); > + reg_wr(&icap->icap_regs->ir_wf, 0x28018001); > + reg_wr(&icap->icap_regs->ir_wf, 0x20000000); > + reg_wr(&icap->icap_regs->ir_wf, 0x20000000); > + w = reg_rd(&icap->icap_regs->ir_cr); > + reg_wr(&icap->icap_regs->ir_cr, 0x1); > + w = reg_rd(&icap->icap_regs->ir_cr); > + w = reg_rd(&icap->icap_regs->ir_cr); > + w = reg_rd(&icap->icap_regs->ir_sr); > + w = reg_rd(&icap->icap_regs->ir_cr); > + w = reg_rd(&icap->icap_regs->ir_sr); > + reg_wr(&icap->icap_regs->ir_sz, 0x1); > + w = reg_rd(&icap->icap_regs->ir_cr); > + reg_wr(&icap->icap_regs->ir_cr, 0x2); > + w = reg_rd(&icap->icap_regs->ir_rfo); > + icap->idcode = reg_rd(&icap->icap_regs->ir_rf); > + w = reg_rd(&icap->icap_regs->ir_cr); > + (void)w; ?! > +} > + > +static int > +xrt_icap_leaf_ioctl(struct platform_device *pdev, u32 cmd, void *arg) > +{ > + struct xrt_icap_ioctl_wr *wr_arg = arg; > + struct icap *icap; > + int ret = 0; > + > + icap = platform_get_drvdata(pdev); > + > + switch (cmd) { > + case XRT_XLEAF_EVENT: > + /* Does not handle any event. */ > + break; > + case XRT_ICAP_WRITE: > + ret = icap_download(icap, wr_arg->xiiw_bit_data, > + wr_arg->xiiw_data_len); > + break; > + case XRT_ICAP_IDCODE: > + *(u64 *)arg = icap->idcode; > + break; > + default: > + ICAP_ERR(icap, "unknown command %d", cmd); > + return -EINVAL; > + } > + > + return ret; > +} > + > +static int xrt_icap_remove(struct platform_device *pdev) > +{ > + struct icap *icap; > + > + icap = platform_get_drvdata(pdev); > + > + platform_set_drvdata(pdev, NULL); > + devm_kfree(&pdev->dev, icap); > + > + return 0; > +} > + > +static int xrt_icap_probe(struct platform_device *pdev) > +{ > + struct icap *icap; > + int ret = 0; > + struct resource *res; > + > + icap = devm_kzalloc(&pdev->dev, sizeof(*icap), GFP_KERNEL); > + if (!icap) > + return -ENOMEM; > + > + icap->pdev = pdev; > + platform_set_drvdata(pdev, icap); > + mutex_init(&icap->icap_lock); > + > + xrt_info(pdev, "probing"); > + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); > + if (res) { > + icap->icap_regs = ioremap(res->start, res->end - res->start + 1); > + if (!icap->icap_regs) { > + xrt_err(pdev, "map base failed %pR", res); > + ret = -EIO; > + goto failed; > + } > + } > + > + icap_probe_chip(icap); > +failed: > + return ret; > +} > + > +static struct xrt_subdev_endpoints xrt_icap_endpoints[] = { > + { > + .xse_names = (struct xrt_subdev_ep_names[]) { > + { .ep_name = XRT_MD_NODE_FPGA_CONFIG }, > + { NULL }, > + }, > + .xse_min_ep = 1, > + }, > + { 0 }, > +}; > + > +static struct xrt_subdev_drvdata xrt_icap_data = { > + .xsd_dev_ops = { > + .xsd_ioctl = xrt_icap_leaf_ioctl, > + }, > +}; > + > +static const struct platform_device_id xrt_icap_table[] = { > + { XRT_ICAP, (kernel_ulong_t)&xrt_icap_data }, > + { }, > +}; > + > +static struct platform_driver xrt_icap_driver = { > + .driver = { > + .name = XRT_ICAP, > + }, > + .probe = xrt_icap_probe, > + .remove = xrt_icap_remove, > + .id_table = xrt_icap_table, > +}; > + > +void icap_leaf_init_fini(bool init) > +{ > + if (init) > + xleaf_register_driver(XRT_SUBDEV_ICAP, &xrt_icap_driver, xrt_icap_endpoints); > + else > + xleaf_unregister_driver(XRT_SUBDEV_ICAP); > +} > -- > 2.18.4 > - Moritz
On Wed, Feb 17, 2021 at 10:40:18PM -0800, Lizhi Hou wrote: > Add partition isolation platform driver. partition isolation is > a hardware function discovered by walking firmware metadata. > A platform device node will be created for it. Partition isolation > function isolate the different fpga regions > > Signed-off-by: Sonal Santan <sonal.santan@xilinx.com> > Signed-off-by: Max Zhen <max.zhen@xilinx.com> > Signed-off-by: Lizhi Hou <lizhih@xilinx.com> > --- > drivers/fpga/xrt/include/xleaf/axigate.h | 25 ++ > drivers/fpga/xrt/lib/xleaf/axigate.c | 298 +++++++++++++++++++++++ > 2 files changed, 323 insertions(+) > create mode 100644 drivers/fpga/xrt/include/xleaf/axigate.h > create mode 100644 drivers/fpga/xrt/lib/xleaf/axigate.c > > diff --git a/drivers/fpga/xrt/include/xleaf/axigate.h b/drivers/fpga/xrt/include/xleaf/axigate.h > new file mode 100644 > index 000000000000..2cef71e13b30 > --- /dev/null > +++ b/drivers/fpga/xrt/include/xleaf/axigate.h > @@ -0,0 +1,25 @@ > +/* SPDX-License-Identifier: GPL-2.0 */ > +/* > + * Header file for XRT Axigate Leaf Driver > + * > + * Copyright (C) 2020-2021 Xilinx, Inc. > + * > + * Authors: > + * Lizhi Hou <Lizhi.Hou@xilinx.com> > + */ > + > +#ifndef _XRT_AXIGATE_H_ > +#define _XRT_AXIGATE_H_ > + > +#include "xleaf.h" > +#include "metadata.h" > + > +/* > + * AXIGATE driver IOCTL calls. > + */ > +enum xrt_axigate_ioctl_cmd { > + XRT_AXIGATE_FREEZE = XRT_XLEAF_CUSTOM_BASE, /* See comments in xleaf.h */ > + XRT_AXIGATE_FREE, > +}; > + > +#endif /* _XRT_AXIGATE_H_ */ > diff --git a/drivers/fpga/xrt/lib/xleaf/axigate.c b/drivers/fpga/xrt/lib/xleaf/axigate.c > new file mode 100644 > index 000000000000..382969f9925f > --- /dev/null > +++ b/drivers/fpga/xrt/lib/xleaf/axigate.c > @@ -0,0 +1,298 @@ > +// SPDX-License-Identifier: GPL-2.0 > +/* > + * Xilinx Alveo FPGA AXI Gate Driver > + * > + * Copyright (C) 2020-2021 Xilinx, Inc. > + * > + * Authors: > + * Lizhi Hou<Lizhi.Hou@xilinx.com> > + */ > + > +#include <linux/mod_devicetable.h> > +#include <linux/platform_device.h> > +#include <linux/delay.h> > +#include <linux/device.h> > +#include <linux/io.h> > +#include "metadata.h" > +#include "xleaf.h" > +#include "xleaf/axigate.h" > + > +#define XRT_AXIGATE "xrt_axigate" > + > +struct axigate_regs { > + u32 iag_wr; > + u32 iag_rvsd; > + u32 iag_rd; > +} __packed; Just make them #defines, even more so if there are only 3 of them. > + > +struct xrt_axigate { > + struct platform_device *pdev; > + void *base; > + struct mutex gate_lock; /* gate dev lock */ > + > + void *evt_hdl; > + const char *ep_name; > + > + bool gate_freezed; > +}; > + > +/* the ep names are in the order of hardware layers */ > +static const char * const xrt_axigate_epnames[] = { > + XRT_MD_NODE_GATE_PLP, > + XRT_MD_NODE_GATE_ULP, > + NULL > +}; > + > +#define reg_rd(g, r) \ > + ioread32((void *)(g)->base + offsetof(struct axigate_regs, r)) > +#define reg_wr(g, v, r) \ > + iowrite32(v, (void *)(g)->base + offsetof(struct axigate_regs, r)) > + > +static inline void freeze_gate(struct xrt_axigate *gate) > +{ > + reg_wr(gate, 0, iag_wr); > + ndelay(500); > + reg_rd(gate, iag_rd); > +} > + > +static inline void free_gate(struct xrt_axigate *gate) > +{ > + reg_wr(gate, 0x2, iag_wr); > + ndelay(500); Magic constants? > + (void)reg_rd(gate, iag_rd); At the very least add a comment on why? Is this for PCI synchronization reasons? > + reg_wr(gate, 0x3, iag_wr); > + ndelay(500); Magic constants? > + reg_rd(gate, iag_rd); Does it nead a (void) or not? Be consistent, again, why do we read here at all? > +} > + > +static int xrt_axigate_epname_idx(struct platform_device *pdev) > +{ > + int i; > + int ret; > + struct resource *res; Nope. Indents: struct resource *res; int, i, ret; > + > + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); > + if (!res) { > + xrt_err(pdev, "Empty Resource!"); > + return -EINVAL; > + } > + > + for (i = 0; xrt_axigate_epnames[i]; i++) { > + ret = strncmp(xrt_axigate_epnames[i], res->name, > + strlen(xrt_axigate_epnames[i]) + 1); > + if (!ret) > + break; > + } > + > + ret = (xrt_axigate_epnames[i]) ? i : -EINVAL; Why not just: if (xrt_axigate_epnames[i]) return i; return -EINVAL; > + return ret; > +} > + > +static void xrt_axigate_freeze(struct platform_device *pdev) > +{ > + struct xrt_axigate *gate; > + u32 freeze = 0; Indents. Fix everywhere. > + > + gate = platform_get_drvdata(pdev); > + > + mutex_lock(&gate->gate_lock); > + freeze = reg_rd(gate, iag_rd); > + if (freeze) { /* gate is opened */ > + xleaf_broadcast_event(pdev, XRT_EVENT_PRE_GATE_CLOSE, false); > + freeze_gate(gate); > + } > + > + gate->gate_freezed = true; s/freezed/frozen > + mutex_unlock(&gate->gate_lock); > + > + xrt_info(pdev, "freeze gate %s", gate->ep_name); debug? > +} > + > +static void xrt_axigate_free(struct platform_device *pdev) > +{ > + struct xrt_axigate *gate; > + u32 freeze; > + > + gate = platform_get_drvdata(pdev); > + > + mutex_lock(&gate->gate_lock); > + freeze = reg_rd(gate, iag_rd); > + if (!freeze) { /* gate is closed */ > + free_gate(gate); > + xleaf_broadcast_event(pdev, XRT_EVENT_POST_GATE_OPEN, true); > + /* xrt_axigate_free() could be called in event cb, thus > + * we can not wait for the completes > + */ > + } > + > + gate->gate_freezed = false; > + mutex_unlock(&gate->gate_lock); > + > + xrt_info(pdev, "free gate %s", gate->ep_name); > +} > + > +static void xrt_axigate_event_cb(struct platform_device *pdev, void *arg) > +{ > + struct platform_device *leaf; > + struct xrt_event *evt = (struct xrt_event *)arg; > + enum xrt_events e = evt->xe_evt; > + enum xrt_subdev_id id = evt->xe_subdev.xevt_subdev_id; > + int instance = evt->xe_subdev.xevt_subdev_instance; > + struct xrt_axigate *gate = platform_get_drvdata(pdev); > + struct resource *res; Reverse x-mas tree; xxxxxxxxxx xxxxxxxxx xxxxxxxx xxxxxx > + > + switch (e) { > + case XRT_EVENT_POST_CREATION: > + break; > + default: > + return; > + } > + > + if (id != XRT_SUBDEV_AXIGATE) > + return; > + > + leaf = xleaf_get_leaf_by_id(pdev, id, instance); > + if (!leaf) > + return; > + > + res = platform_get_resource(leaf, IORESOURCE_MEM, 0); > + if (!res || !strncmp(res->name, gate->ep_name, strlen(res->name) + 1)) { > + (void)xleaf_put_leaf(pdev, leaf); > + return; > + } > + > + /* > + * higher level axigate instance created, > + * make sure the gate is openned. This covers 1RP flow which > + * has plp gate as well. > + */ > + if (xrt_axigate_epname_idx(leaf) > xrt_axigate_epname_idx(pdev)) > + xrt_axigate_free(pdev); > + else > + xleaf_ioctl(leaf, XRT_AXIGATE_FREE, NULL); > + > + (void)xleaf_put_leaf(pdev, leaf); > +} > + > +static int > +xrt_axigate_leaf_ioctl(struct platform_device *pdev, u32 cmd, void *arg) > +{ > + switch (cmd) { > + case XRT_XLEAF_EVENT: > + xrt_axigate_event_cb(pdev, arg); > + break; > + case XRT_AXIGATE_FREEZE: > + xrt_axigate_freeze(pdev); > + break; > + case XRT_AXIGATE_FREE: > + xrt_axigate_free(pdev); > + break; > + default: > + xrt_err(pdev, "unsupported cmd %d", cmd); > + return -EINVAL; > + } > + > + return 0; > +} > + > +static int xrt_axigate_remove(struct platform_device *pdev) > +{ > + struct xrt_axigate *gate; > + > + gate = platform_get_drvdata(pdev); > + > + if (gate->base) > + iounmap(gate->base); > + > + platform_set_drvdata(pdev, NULL); > + devm_kfree(&pdev->dev, gate); No! The point of using devres is so cleanup happens on removal. While you're at it, if you move the ioremap to a devres version, this function can basically go away entirely. > + > + return 0; > +} > + > +static int xrt_axigate_probe(struct platform_device *pdev) > +{ > + struct xrt_axigate *gate; > + struct resource *res; > + int ret; > + > + gate = devm_kzalloc(&pdev->dev, sizeof(*gate), GFP_KERNEL); > + if (!gate) > + return -ENOMEM; > + > + gate->pdev = pdev; > + platform_set_drvdata(pdev, gate); > + > + xrt_info(pdev, "probing..."); > + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); > + if (!res) { > + xrt_err(pdev, "Empty resource 0"); > + ret = -EINVAL; > + goto failed; > + } > + > + gate->base = ioremap(res->start, res->end - res->start + 1); > + if (!gate->base) { > + xrt_err(pdev, "map base iomem failed"); > + ret = -EFAULT; > + goto failed; > + } > + > + gate->ep_name = res->name; > + > + mutex_init(&gate->gate_lock); > + > + return 0; > + > +failed: > + xrt_axigate_remove(pdev); > + return ret; > +} > + > +static struct xrt_subdev_endpoints xrt_axigate_endpoints[] = { > + { > + .xse_names = (struct xrt_subdev_ep_names[]) { > + { .ep_name = "ep_pr_isolate_ulp_00" }, > + { NULL }, > + }, > + .xse_min_ep = 1, > + }, > + { > + .xse_names = (struct xrt_subdev_ep_names[]) { > + { .ep_name = "ep_pr_isolate_plp_00" }, > + { NULL }, > + }, > + .xse_min_ep = 1, > + }, > + { 0 }, > +}; > + > +static struct xrt_subdev_drvdata xrt_axigate_data = { > + .xsd_dev_ops = { > + .xsd_ioctl = xrt_axigate_leaf_ioctl, > + }, > +}; > + > +static const struct platform_device_id xrt_axigate_table[] = { > + { XRT_AXIGATE, (kernel_ulong_t)&xrt_axigate_data }, > + { }, > +}; > + > +static struct platform_driver xrt_axigate_driver = { > + .driver = { > + .name = XRT_AXIGATE, > + }, > + .probe = xrt_axigate_probe, > + .remove = xrt_axigate_remove, > + .id_table = xrt_axigate_table, > +}; > + > +void axigate_leaf_init_fini(bool init) > +{ > + if (init) { > + xleaf_register_driver(XRT_SUBDEV_AXIGATE, > + &xrt_axigate_driver, xrt_axigate_endpoints); > + } else { > + xleaf_unregister_driver(XRT_SUBDEV_AXIGATE); > + } > +} This thing is duplicated in every file, maybe a macro would be an idea. > -- > 2.18.4 > - Moritz
Lizhi, On Wed, Feb 17, 2021 at 10:40:01PM -0800, Lizhi Hou wrote: > Hello, > > This is V3 of patch series which adds management physical function driver for Xilinx > Alveo PCIe accelerator cards, https://www.xilinx.com/products/boards-and-kits/alveo.html > This driver is part of Xilinx Runtime (XRT) open source stack. > > XILINX ALVEO PLATFORM ARCHITECTURE > > Alveo PCIe FPGA based platforms have a static *shell* partition and a partial > re-configurable *user* partition. The shell partition is automatically loaded from > flash when host is booted and PCIe is enumerated by BIOS. Shell cannot be changed > till the next cold reboot. The shell exposes two PCIe physical functions: > > 1. management physical function > 2. user physical function > > The patch series includes Documentation/xrt.rst which describes Alveo platform, > XRT driver architecture and deployment model in more detail. > > Users compile their high level design in C/C++/OpenCL or RTL into FPGA image using > Vitis https://www.xilinx.com/products/design-tools/vitis/vitis-platform.html > tools. The compiled image is packaged as xclbin which contains partial bitstream > for the user partition and necessary metadata. Users can dynamically swap the image > running on the user partition in order to switch between different workloads by > loading different xclbins. > > XRT DRIVERS FOR XILINX ALVEO > > XRT Linux kernel driver *xmgmt* binds to management physical function of Alveo > platform. The modular driver framework is organized into several platform drivers > which primarily handle the following functionality: > > 1. Loading firmware container also called xsabin at driver attach time > 2. Loading of user compiled xclbin with FPGA Manager integration > 3. Clock scaling of image running on user partition > 4. In-band sensors: temp, voltage, power, etc. > 5. Device reset and rescan > > The platform drivers are packaged into *xrt-lib* helper module with well > defined interfaces. The module provides a pseudo-bus implementation for the > platform drivers. More details on the driver model can be found in > Documentation/xrt.rst. > > User physical function driver is not included in this patch series. > > LIBFDT REQUIREMENT > > XRT driver infrastructure uses Device Tree as a metadata format to discover > HW subsystems in the Alveo PCIe device. The Device Tree schema used by XRT > is documented in Documentation/xrt.rst. Unlike previous V1 and V2 version > of patch series, V3 version does not require export of libfdt symbols. > > TESTING AND VALIDATION > > xmgmt driver can be tested with full XRT open source stack which includes user > space libraries, board utilities and (out of tree) first generation user physical > function driver xocl. XRT open source runtime stack is available at > https://github.com/Xilinx/XRT > > Complete documentation for XRT open source stack including sections on Alveo/XRT > security and platform architecture can be found here: > > https://xilinx.github.io/XRT/master/html/index.html > https://xilinx.github.io/XRT/master/html/security.html > https://xilinx.github.io/XRT/master/html/platforms_partitions.html > > Changes since v2: > - Streamlined the driver framework into *xleaf*, *group* and *xroot* > - Updated documentation to show the driver model with examples > - Addressed kernel test robot errors > - Added a selftest for basic driver framework > - Documented device tree schema > - Removed need to export libfdt symbols > > Changes since v1: > - Updated the driver to use fpga_region and fpga_bridge for FPGA > programming > - Dropped platform drivers not related to PR programming to focus on XRT > core framework > - Updated Documentation/fpga/xrt.rst with information on XRT core framework > - Addressed checkpatch issues > - Dropped xrt- prefix from some header files > > For reference V1 version of patch series can be found here: > > https://lore.kernel.org/lkml/20201217075046.28553-1-sonals@xilinx.com/ > https://lore.kernel.org/lkml/20201217075046.28553-2-sonals@xilinx.com/ > https://lore.kernel.org/lkml/20201217075046.28553-3-sonals@xilinx.com/ > https://lore.kernel.org/lkml/20201217075046.28553-4-sonals@xilinx.com/ > https://lore.kernel.org/lkml/20201217075046.28553-5-sonals@xilinx.com/ > https://lore.kernel.org/lkml/20201217075046.28553-6-sonals@xilinx.com/ > https://lore.kernel.org/lkml/20201217075046.28553-7-sonals@xilinx.com/ > > Lizhi Hou (18): > Documentation: fpga: Add a document describing XRT Alveo drivers > fpga: xrt: driver metadata helper functions > fpga: xrt: xclbin file helper functions > fpga: xrt: xrt-lib platform driver manager > fpga: xrt: group platform driver > fpga: xrt: platform driver infrastructure > fpga: xrt: management physical function driver (root) > fpga: xrt: main platform driver for management function device > fpga: xrt: fpga-mgr and region implementation for xclbin download > fpga: xrt: VSEC platform driver > fpga: xrt: UCS platform driver > fpga: xrt: ICAP platform driver > fpga: xrt: devctl platform driver > fpga: xrt: clock platform driver > fpga: xrt: clock frequence counter platform driver > fpga: xrt: DDR calibration platform driver > fpga: xrt: partition isolation platform driver > fpga: xrt: Kconfig and Makefile updates for XRT drivers > > Documentation/fpga/index.rst | 1 + > Documentation/fpga/xrt.rst | 842 ++++++++++++++++++++++ > MAINTAINERS | 11 + > drivers/Makefile | 1 + > drivers/fpga/Kconfig | 2 + > drivers/fpga/Makefile | 4 + > drivers/fpga/xrt/Kconfig | 8 + > drivers/fpga/xrt/include/events.h | 48 ++ > drivers/fpga/xrt/include/group.h | 27 + > drivers/fpga/xrt/include/metadata.h | 229 ++++++ > drivers/fpga/xrt/include/subdev_id.h | 43 ++ > drivers/fpga/xrt/include/xclbin-helper.h | 52 ++ > drivers/fpga/xrt/include/xleaf.h | 276 +++++++ > drivers/fpga/xrt/include/xleaf/axigate.h | 25 + > drivers/fpga/xrt/include/xleaf/calib.h | 30 + > drivers/fpga/xrt/include/xleaf/clkfreq.h | 23 + > drivers/fpga/xrt/include/xleaf/clock.h | 31 + > drivers/fpga/xrt/include/xleaf/devctl.h | 43 ++ > drivers/fpga/xrt/include/xleaf/icap.h | 29 + > drivers/fpga/xrt/include/xleaf/ucs.h | 24 + > drivers/fpga/xrt/include/xmgmt-main.h | 37 + > drivers/fpga/xrt/include/xroot.h | 114 +++ > drivers/fpga/xrt/lib/Kconfig | 16 + > drivers/fpga/xrt/lib/Makefile | 30 + > drivers/fpga/xrt/lib/cdev.c | 231 ++++++ > drivers/fpga/xrt/lib/group.c | 265 +++++++ > drivers/fpga/xrt/lib/main.c | 274 +++++++ > drivers/fpga/xrt/lib/main.h | 17 + > drivers/fpga/xrt/lib/subdev.c | 871 +++++++++++++++++++++++ > drivers/fpga/xrt/lib/subdev_pool.h | 53 ++ > drivers/fpga/xrt/lib/xclbin.c | 394 ++++++++++ > drivers/fpga/xrt/lib/xleaf/axigate.c | 298 ++++++++ > drivers/fpga/xrt/lib/xleaf/calib.c | 226 ++++++ > drivers/fpga/xrt/lib/xleaf/clkfreq.c | 221 ++++++ > drivers/fpga/xrt/lib/xleaf/clock.c | 648 +++++++++++++++++ > drivers/fpga/xrt/lib/xleaf/devctl.c | 206 ++++++ > drivers/fpga/xrt/lib/xleaf/icap.c | 317 +++++++++ > drivers/fpga/xrt/lib/xleaf/ucs.c | 235 ++++++ > drivers/fpga/xrt/lib/xleaf/vsec.c | 359 ++++++++++ > drivers/fpga/xrt/lib/xroot.c | 598 ++++++++++++++++ > drivers/fpga/xrt/metadata/Kconfig | 12 + > drivers/fpga/xrt/metadata/Makefile | 16 + > drivers/fpga/xrt/metadata/metadata.c | 524 ++++++++++++++ > drivers/fpga/xrt/mgmt/Kconfig | 15 + > drivers/fpga/xrt/mgmt/Makefile | 19 + > drivers/fpga/xrt/mgmt/fmgr-drv.c | 187 +++++ > drivers/fpga/xrt/mgmt/fmgr.h | 28 + > drivers/fpga/xrt/mgmt/main-impl.h | 37 + > drivers/fpga/xrt/mgmt/main-region.c | 471 ++++++++++++ > drivers/fpga/xrt/mgmt/main.c | 693 ++++++++++++++++++ > drivers/fpga/xrt/mgmt/root.c | 342 +++++++++ > include/uapi/linux/xrt/xclbin.h | 408 +++++++++++ > include/uapi/linux/xrt/xmgmt-ioctl.h | 46 ++ > 53 files changed, 9957 insertions(+) > create mode 100644 Documentation/fpga/xrt.rst > create mode 100644 drivers/fpga/xrt/Kconfig > create mode 100644 drivers/fpga/xrt/include/events.h > create mode 100644 drivers/fpga/xrt/include/group.h > create mode 100644 drivers/fpga/xrt/include/metadata.h > create mode 100644 drivers/fpga/xrt/include/subdev_id.h > create mode 100644 drivers/fpga/xrt/include/xclbin-helper.h > create mode 100644 drivers/fpga/xrt/include/xleaf.h > create mode 100644 drivers/fpga/xrt/include/xleaf/axigate.h > create mode 100644 drivers/fpga/xrt/include/xleaf/calib.h > create mode 100644 drivers/fpga/xrt/include/xleaf/clkfreq.h > create mode 100644 drivers/fpga/xrt/include/xleaf/clock.h > create mode 100644 drivers/fpga/xrt/include/xleaf/devctl.h > create mode 100644 drivers/fpga/xrt/include/xleaf/icap.h > create mode 100644 drivers/fpga/xrt/include/xleaf/ucs.h > create mode 100644 drivers/fpga/xrt/include/xmgmt-main.h > create mode 100644 drivers/fpga/xrt/include/xroot.h > create mode 100644 drivers/fpga/xrt/lib/Kconfig > create mode 100644 drivers/fpga/xrt/lib/Makefile > create mode 100644 drivers/fpga/xrt/lib/cdev.c > create mode 100644 drivers/fpga/xrt/lib/group.c > create mode 100644 drivers/fpga/xrt/lib/main.c > create mode 100644 drivers/fpga/xrt/lib/main.h > create mode 100644 drivers/fpga/xrt/lib/subdev.c > create mode 100644 drivers/fpga/xrt/lib/subdev_pool.h > create mode 100644 drivers/fpga/xrt/lib/xclbin.c > create mode 100644 drivers/fpga/xrt/lib/xleaf/axigate.c > create mode 100644 drivers/fpga/xrt/lib/xleaf/calib.c > create mode 100644 drivers/fpga/xrt/lib/xleaf/clkfreq.c > create mode 100644 drivers/fpga/xrt/lib/xleaf/clock.c > create mode 100644 drivers/fpga/xrt/lib/xleaf/devctl.c > create mode 100644 drivers/fpga/xrt/lib/xleaf/icap.c > create mode 100644 drivers/fpga/xrt/lib/xleaf/ucs.c > create mode 100644 drivers/fpga/xrt/lib/xleaf/vsec.c > create mode 100644 drivers/fpga/xrt/lib/xroot.c > create mode 100644 drivers/fpga/xrt/metadata/Kconfig > create mode 100644 drivers/fpga/xrt/metadata/Makefile > create mode 100644 drivers/fpga/xrt/metadata/metadata.c > create mode 100644 drivers/fpga/xrt/mgmt/Kconfig > create mode 100644 drivers/fpga/xrt/mgmt/Makefile > create mode 100644 drivers/fpga/xrt/mgmt/fmgr-drv.c > create mode 100644 drivers/fpga/xrt/mgmt/fmgr.h > create mode 100644 drivers/fpga/xrt/mgmt/main-impl.h > create mode 100644 drivers/fpga/xrt/mgmt/main-region.c > create mode 100644 drivers/fpga/xrt/mgmt/main.c > create mode 100644 drivers/fpga/xrt/mgmt/root.c > create mode 100644 include/uapi/linux/xrt/xclbin.h > create mode 100644 include/uapi/linux/xrt/xmgmt-ioctl.h > > -- > 2.18.4 > Please fix the indents all across this patchset. Doesn't checkpatch with --strict complain about this? Also more generally this looks like it should be a bus. Look at DFL for reference. - Moritz
On 2/17/21 10:40 PM, Lizhi Hou wrote: > group driver that manages life cycle of a bunch of leaf driver instances > and bridges them with root. > > Signed-off-by: Sonal Santan <sonal.santan@xilinx.com> > Signed-off-by: Max Zhen <max.zhen@xilinx.com> > Signed-off-by: Lizhi Hou <lizhih@xilinx.com> > --- > drivers/fpga/xrt/include/group.h | 27 ++++ > drivers/fpga/xrt/lib/group.c | 265 +++++++++++++++++++++++++++++++ > 2 files changed, 292 insertions(+) > create mode 100644 drivers/fpga/xrt/include/group.h > create mode 100644 drivers/fpga/xrt/lib/group.c > > diff --git a/drivers/fpga/xrt/include/group.h b/drivers/fpga/xrt/include/group.h > new file mode 100644 > index 000000000000..1874cdd5120d > --- /dev/null > +++ b/drivers/fpga/xrt/include/group.h > @@ -0,0 +1,27 @@ > +/* SPDX-License-Identifier: GPL-2.0 */ > +/* > + * Header file for Xilinx Runtime (XRT) driver A bit too generic, please add a description or remove. > + * > + * Copyright (C) 2020-2021 Xilinx, Inc. > + * > + * Authors: > + * Cheng Zhen <maxz@xilinx.com> > + */ > + > +#ifndef _XRT_GROUP_H_ > +#define _XRT_GROUP_H_ > + > +#include "xleaf.h" This is patch 6, consider comments on patch 4. > + > +/* > + * Group driver IOCTL calls. Are these really ioctl calls? Seems more like messages between nodes in a tree. Consider changing to better jagon, maybe ioctl -> msg > + */ > +enum xrt_group_ioctl_cmd { > + XRT_GROUP_GET_LEAF = XRT_XLEAF_CUSTOM_BASE, /* See comments in xleaf.h */ XRT_LEAF_CUSTOM_BASE is a #define, while these are enums. To be consistent, the XRT_LEAF_CUSTOM_BASE should be an enum in xleaf, you can initialize it to 64 there. > + XRT_GROUP_PUT_LEAF, > + XRT_GROUP_INIT_CHILDREN, > + XRT_GROUP_FINI_CHILDREN, > + XRT_GROUP_TRIGGER_EVENT, > +}; > + > +#endif /* _XRT_GROUP_H_ */ > diff --git a/drivers/fpga/xrt/lib/group.c b/drivers/fpga/xrt/lib/group.c > new file mode 100644 > index 000000000000..6ba56eea479b > --- /dev/null > +++ b/drivers/fpga/xrt/lib/group.c > @@ -0,0 +1,265 @@ > +// SPDX-License-Identifier: GPL-2.0 > +/* > + * Xilinx Alveo FPGA Group Driver > + * > + * Copyright (C) 2020-2021 Xilinx, Inc. > + * > + * Authors: > + * Cheng Zhen <maxz@xilinx.com> > + */ > + > +#include <linux/mod_devicetable.h> > +#include <linux/platform_device.h> > +#include "xleaf.h" > +#include "subdev_pool.h" > +#include "group.h" > +#include "metadata.h" > +#include "main.h" > + > +#define XRT_GRP "xrt_group" > + > +struct xrt_group { > + struct platform_device *pdev; > + struct xrt_subdev_pool leaves; > + bool leaves_created; > + struct mutex lock; /* lock for group */ > +}; > + > +static int xrt_grp_root_cb(struct device *dev, void *parg, > + u32 cmd, void *arg) could 'cmd' be some enum type ? > +{ > + int rc; > + struct platform_device *pdev = > + container_of(dev, struct platform_device, dev); > + struct xrt_group *xg = (struct xrt_group *)parg; > + > + switch (cmd) { > + case XRT_ROOT_GET_LEAF_HOLDERS: { > + struct xrt_root_ioctl_get_holders *holders = > + (struct xrt_root_ioctl_get_holders *)arg; > + rc = xrt_subdev_pool_get_holders(&xg->leaves, > + holders->xpigh_pdev, > + holders->xpigh_holder_buf, > + holders->xpigh_holder_buf_len); > + break; > + } > + default: > + /* Forward parent call to root. */ > + rc = xrt_subdev_root_request(pdev, cmd, arg); > + break; > + } > + > + return rc; > +} > + > +static int xrt_grp_create_leaves(struct xrt_group *xg) > +{ > + struct xrt_subdev_platdata *pdata = DEV_PDATA(xg->pdev); > + enum xrt_subdev_id did; > + struct xrt_subdev_endpoints *eps = NULL; > + int ep_count = 0, i, ret = 0, failed = 0; > + unsigned long mlen; > + char *dtb, *grp_dtb = NULL; > + const char *ep_name; > + > + mutex_lock(&xg->lock); > + > + if (xg->leaves_created) { > + mutex_unlock(&xg->lock); This happens should be programming error, so print out some error message > + return -EEXIST; > + } > + > + xrt_info(xg->pdev, "bringing up leaves..."); > + > + /* Create all leaves based on dtb. */ > + if (!pdata) > + goto bail; move to above the lock and fail with something like -EINVAL > + > + mlen = xrt_md_size(DEV(xg->pdev), pdata->xsp_dtb); > + if (mlen == XRT_MD_INVALID_LENGTH) { > + xrt_err(xg->pdev, "invalid dtb, len %ld", mlen); > + goto bail; > + } > + > + grp_dtb = vmalloc(mlen); > + if (!grp_dtb) > + goto bail; failed is only set in the loop. This is an unreported -ENOMEM > + > + memcpy(grp_dtb, pdata->xsp_dtb, mlen); > + for (did = 0; did < XRT_SUBDEV_NUM;) { why isn't the did incremented ? > + eps = eps ? eps + 1 : xrt_drv_get_endpoints(did); this assumes the enpoints are in an array and accessed serially. this is fragile. convert to using just the xrt_drv_get_endpoints() call > + if (!eps || !eps->xse_names) { > + did++; > + eps = NULL; > + continue; > + } > + ret = xrt_md_create(DEV(xg->pdev), &dtb); > + if (ret) { > + xrt_err(xg->pdev, "create md failed, drv %s", > + xrt_drv_name(did)); > + failed++; failed but no cleanup of earier successes > + continue; > + } > + for (i = 0; eps->xse_names[i].ep_name || this assumes that xse_names[] always has a guard. why not use xse_min_ep ? > + eps->xse_names[i].regmap_name; i++) { > + ep_name = (char *)eps->xse_names[i].ep_name; > + if (!ep_name) { > + xrt_md_get_compatible_endpoint(DEV(xg->pdev), > + grp_dtb, > + eps->xse_names[i].regmap_name, > + &ep_name); > + } > + if (!ep_name) > + continue; > + > + ret = xrt_md_copy_endpoint(DEV(xg->pdev), > + dtb, grp_dtb, ep_name, > + (char *)eps->xse_names[i].regmap_name, > + NULL); > + if (ret) > + continue; > + xrt_md_del_endpoint(DEV(xg->pdev), grp_dtb, ep_name, > + (char *)eps->xse_names[i].regmap_name); > + ep_count++; > + } > + if (ep_count >= eps->xse_min_ep) { This only happens if all additions are successful. > + ret = xrt_subdev_pool_add(&xg->leaves, did, > + xrt_grp_root_cb, xg, dtb); > + eps = NULL; > + if (ret < 0) { > + failed++; > + xrt_err(xg->pdev, "failed to create %s: %d", > + xrt_drv_name(did), ret); > + } > + } else if (ep_count > 0) { > + xrt_md_copy_all_endpoints(DEV(xg->pdev), grp_dtb, dtb); > + } > + vfree(dtb); > + ep_count = 0; > + } > + > + xg->leaves_created = true; This is true even if some failed ? > + > +bail: > + vfree(grp_dtb); > + mutex_unlock(&xg->lock); > + > + return failed == 0 ? 0 : -ECHILD; > +} > + > +static void xrt_grp_remove_leaves(struct xrt_group *xg) > +{ > + mutex_lock(&xg->lock); > + > + if (!xg->leaves_created) { > + mutex_unlock(&xg->lock); > + return; > + } > + > + xrt_info(xg->pdev, "tearing down leaves..."); > + xrt_subdev_pool_fini(&xg->leaves); partial failure above and the subdev_pool is not created ? > + xg->leaves_created = false; > + > + mutex_unlock(&xg->lock); > +} > + > +static int xrt_grp_probe(struct platform_device *pdev) > +{ > + struct xrt_group *xg; > + > + xrt_info(pdev, "probing..."); > + > + xg = devm_kzalloc(&pdev->dev, sizeof(*xg), GFP_KERNEL); > + if (!xg) > + return -ENOMEM; > + > + xg->pdev = pdev; > + mutex_init(&xg->lock); > + xrt_subdev_pool_init(DEV(pdev), &xg->leaves); > + platform_set_drvdata(pdev, xg); > + > + return 0; > +} > + > +static int xrt_grp_remove(struct platform_device *pdev) > +{ > + struct xrt_group *xg = platform_get_drvdata(pdev); > + > + xrt_info(pdev, "leaving..."); > + xrt_grp_remove_leaves(xg); lock ? Tom > + return 0; > +} > + > +static int xrt_grp_ioctl(struct platform_device *pdev, u32 cmd, void *arg) > +{ > + int rc = 0; > + struct xrt_group *xg = platform_get_drvdata(pdev); > + > + switch (cmd) { > + case XRT_XLEAF_EVENT: > + /* Simply forward to every child. */ > + xrt_subdev_pool_handle_event(&xg->leaves, > + (struct xrt_event *)arg); > + break; > + case XRT_GROUP_GET_LEAF: { > + struct xrt_root_ioctl_get_leaf *get_leaf = > + (struct xrt_root_ioctl_get_leaf *)arg; > + > + rc = xrt_subdev_pool_get(&xg->leaves, get_leaf->xpigl_match_cb, > + get_leaf->xpigl_match_arg, > + DEV(get_leaf->xpigl_pdev), > + &get_leaf->xpigl_leaf); > + break; > + } > + case XRT_GROUP_PUT_LEAF: { > + struct xrt_root_ioctl_put_leaf *put_leaf = > + (struct xrt_root_ioctl_put_leaf *)arg; > + > + rc = xrt_subdev_pool_put(&xg->leaves, put_leaf->xpipl_leaf, > + DEV(put_leaf->xpipl_pdev)); > + break; > + } > + case XRT_GROUP_INIT_CHILDREN: > + rc = xrt_grp_create_leaves(xg); > + break; > + case XRT_GROUP_FINI_CHILDREN: > + xrt_grp_remove_leaves(xg); > + break; > + case XRT_GROUP_TRIGGER_EVENT: > + xrt_subdev_pool_trigger_event(&xg->leaves, (enum xrt_events)(uintptr_t)arg); > + break; > + default: > + xrt_err(pdev, "unknown IOCTL cmd %d", cmd); > + rc = -EINVAL; > + break; > + } > + return rc; > +} > + > +static struct xrt_subdev_drvdata xrt_grp_data = { > + .xsd_dev_ops = { > + .xsd_ioctl = xrt_grp_ioctl, > + }, > +}; > + > +static const struct platform_device_id xrt_grp_id_table[] = { > + { XRT_GRP, (kernel_ulong_t)&xrt_grp_data }, > + { }, > +}; > + > +static struct platform_driver xrt_group_driver = { > + .driver = { > + .name = XRT_GRP, > + }, > + .probe = xrt_grp_probe, > + .remove = xrt_grp_remove, > + .id_table = xrt_grp_id_table, > +}; > + > +void group_leaf_init_fini(bool init) > +{ > + if (init) > + xleaf_register_driver(XRT_SUBDEV_GRP, &xrt_group_driver, NULL); > + else > + xleaf_unregister_driver(XRT_SUBDEV_GRP); > +}
On 2/17/21 10:40 PM, Lizhi Hou wrote: > infrastructure code providing APIs for managing leaf driver instance > groups, facilitating inter-leaf driver calls and root calls, managing leaf > driver device nodes. > > Signed-off-by: Sonal Santan <sonal.santan@xilinx.com> > Signed-off-by: Max Zhen <max.zhen@xilinx.com> > Signed-off-by: Lizhi Hou <lizhih@xilinx.com> > --- > drivers/fpga/xrt/include/events.h | 48 ++ > drivers/fpga/xrt/include/subdev_id.h | 43 ++ > drivers/fpga/xrt/include/xleaf.h | 276 +++++++++ > drivers/fpga/xrt/lib/cdev.c | 231 +++++++ > drivers/fpga/xrt/lib/subdev.c | 871 +++++++++++++++++++++++++++ > drivers/fpga/xrt/lib/subdev_pool.h | 53 ++ > drivers/fpga/xrt/lib/xroot.c | 598 ++++++++++++++++++ > 7 files changed, 2120 insertions(+) > create mode 100644 drivers/fpga/xrt/include/events.h > create mode 100644 drivers/fpga/xrt/include/subdev_id.h > create mode 100644 drivers/fpga/xrt/include/xleaf.h > create mode 100644 drivers/fpga/xrt/lib/cdev.c > create mode 100644 drivers/fpga/xrt/lib/subdev.c > create mode 100644 drivers/fpga/xrt/lib/subdev_pool.h > create mode 100644 drivers/fpga/xrt/lib/xroot.c > > diff --git a/drivers/fpga/xrt/include/events.h b/drivers/fpga/xrt/include/events.h > new file mode 100644 > index 000000000000..2a9aae8bceb4 > --- /dev/null > +++ b/drivers/fpga/xrt/include/events.h > @@ -0,0 +1,48 @@ > +/* SPDX-License-Identifier: GPL-2.0 */ > +/* > + * Header file for Xilinx Runtime (XRT) driver general problem with generic, low information comments > + * > + * Copyright (C) 2020-2021 Xilinx, Inc. > + * > + * Authors: > + * Cheng Zhen <maxz@xilinx.com> > + */ > + > +#ifndef _XRT_EVENTS_H_ > +#define _XRT_EVENTS_H_ > + > +#include <linux/platform_device.h> why is platform_device.h needed ? > +#include "subdev_id.h" > + > +/* > + * Event notification. > + */ > +enum xrt_events { > + XRT_EVENT_TEST = 0, /* for testing */ > + /* > + * Events related to specific subdev > + * Callback arg: struct xrt_event_arg_subdev > + */ > + XRT_EVENT_POST_CREATION, > + XRT_EVENT_PRE_REMOVAL, > + /* > + * Events related to change of the whole board > + * Callback arg: <none> > + */ > + XRT_EVENT_PRE_HOT_RESET, > + XRT_EVENT_POST_HOT_RESET, > + XRT_EVENT_PRE_GATE_CLOSE, > + XRT_EVENT_POST_GATE_OPEN, > +}; > + > +struct xrt_event_arg_subdev { > + enum xrt_subdev_id xevt_subdev_id; > + int xevt_subdev_instance; > +}; > + > +struct xrt_event { > + enum xrt_events xe_evt; > + struct xrt_event_arg_subdev xe_subdev; > +}; > + > +#endif /* _XRT_EVENTS_H_ */ > diff --git a/drivers/fpga/xrt/include/subdev_id.h b/drivers/fpga/xrt/include/subdev_id.h > new file mode 100644 > index 000000000000..6205a9f26196 > --- /dev/null > +++ b/drivers/fpga/xrt/include/subdev_id.h > @@ -0,0 +1,43 @@ > +/* SPDX-License-Identifier: GPL-2.0 */ > +/* > + * Header file for Xilinx Runtime (XRT) driver > + * > + * Copyright (C) 2020-2021 Xilinx, Inc. > + * > + * Authors: > + * Cheng Zhen <maxz@xilinx.com> > + */ > + > +#ifndef _XRT_SUBDEV_ID_H_ > +#define _XRT_SUBDEV_ID_H_ > + > +/* > + * Every subdev driver should have an ID for others to refer to it. driver has an ID > + * There can be unlimited number of instances of a subdev driver. A unlimited? change to 'multiple' > + * <subdev_id, subdev_instance> tuple should be a unique identification of tuple is a unique > + * a specific instance of a subdev driver. > + * NOTE: PLEASE do not change the order of IDs. Sub devices in the same > + * group are initialized by this order. why does the order matter? the enums are all initialized > + */ > +enum xrt_subdev_id { > + XRT_SUBDEV_GRP = 0, > + XRT_SUBDEV_VSEC = 1, > + XRT_SUBDEV_VSEC_GOLDEN = 2, > + XRT_SUBDEV_DEVCTL = 3, > + XRT_SUBDEV_AXIGATE = 4, > + XRT_SUBDEV_ICAP = 5, > + XRT_SUBDEV_TEST = 6, > + XRT_SUBDEV_MGMT_MAIN = 7, > + XRT_SUBDEV_QSPI = 8, > + XRT_SUBDEV_MAILBOX = 9, > + XRT_SUBDEV_CMC = 10, > + XRT_SUBDEV_CALIB = 11, > + XRT_SUBDEV_CLKFREQ = 12, > + XRT_SUBDEV_CLOCK = 13, > + XRT_SUBDEV_SRSR = 14, > + XRT_SUBDEV_UCS = 15, > + XRT_SUBDEV_NUM = 16, /* Total number of subdevs. */ > + XRT_ROOT = -1, /* Special ID for root driver. */ > +}; > + > +#endif /* _XRT_SUBDEV_ID_H_ */ > diff --git a/drivers/fpga/xrt/include/xleaf.h b/drivers/fpga/xrt/include/xleaf.h > new file mode 100644 > index 000000000000..10215a75d474 > --- /dev/null > +++ b/drivers/fpga/xrt/include/xleaf.h > @@ -0,0 +1,276 @@ > +/* SPDX-License-Identifier: GPL-2.0 */ > +/* > + * Header file for Xilinx Runtime (XRT) driver > + * > + * Copyright (C) 2020-2021 Xilinx, Inc. > + * > + * Authors: > + * Cheng Zhen <maxz@xilinx.com> > + * Sonal Santan <sonal.santan@xilinx.com> > + */ > + > +#ifndef _XRT_XLEAF_H_ > +#define _XRT_XLEAF_H_ > + > +#include <linux/mod_devicetable.h> not needed > +#include <linux/platform_device.h> > +#include <linux/fs.h> > +#include <linux/cdev.h> > +#include <linux/pci.h> not needed check if includes are actually needed. > +#include <linux/libfdt_env.h> > +#include "libfdt.h" > +#include "subdev_id.h" > +#include "xroot.h" > +#include "events.h" > + > +/* All subdev drivers should use below common routines to print out msg. */ > +#define DEV(pdev) (&(pdev)->dev) > +#define DEV_PDATA(pdev) \ > + ((struct xrt_subdev_platdata *)dev_get_platdata(DEV(pdev))) > +#define DEV_DRVDATA(pdev) \ > + ((struct xrt_subdev_drvdata *) \ > + platform_get_device_id(pdev)->driver_data) > +#define FMT_PRT(prt_fn, pdev, fmt, args...) \ > + ({typeof(pdev) (_pdev) = (pdev); \ > + prt_fn(DEV(_pdev), "%s %s: " fmt, \ > + DEV_PDATA(_pdev)->xsp_root_name, __func__, ##args); }) > +#define xrt_err(pdev, fmt, args...) FMT_PRT(dev_err, pdev, fmt, ##args) > +#define xrt_warn(pdev, fmt, args...) FMT_PRT(dev_warn, pdev, fmt, ##args) > +#define xrt_info(pdev, fmt, args...) FMT_PRT(dev_info, pdev, fmt, ##args) > +#define xrt_dbg(pdev, fmt, args...) FMT_PRT(dev_dbg, pdev, fmt, ##args) > + > +/* Starting IOCTL for common IOCTLs implemented by all leaves. */ > +#define XRT_XLEAF_COMMON_BASE 0 > +/* Starting IOCTL for leaves' specific IOCTLs. */ > +#define XRT_XLEAF_CUSTOM_BASE 64 > +enum xrt_xleaf_common_ioctl_cmd { > + XRT_XLEAF_EVENT = XRT_XLEAF_COMMON_BASE, > +}; > + > +/* > + * If populated by subdev driver, infra will handle the mechanics of > + * char device (un)registration. > + */ > +enum xrt_subdev_file_mode { > + /* Infra create cdev, default file name */ > + XRT_SUBDEV_FILE_DEFAULT = 0, > + /* Infra create cdev, need to encode inst num in file name */ > + XRT_SUBDEV_FILE_MULTI_INST, > + /* No auto creation of cdev by infra, leaf handles it by itself */ > + XRT_SUBDEV_FILE_NO_AUTO, > +}; > + > +struct xrt_subdev_file_ops { > + const struct file_operations xsf_ops; > + dev_t xsf_dev_t; > + const char *xsf_dev_name; > + enum xrt_subdev_file_mode xsf_mode; > +}; > + > +/* > + * Subdev driver callbacks populated by subdev driver. > + */ > +struct xrt_subdev_drv_ops { > + /* > + * Per driver instance callback. The pdev points to the instance. > + * If defined these are called by other leaf drivers. If defined, > + * Note that root driver may call into xsd_ioctl of a group driver. > + */ > + int (*xsd_ioctl)(struct platform_device *pdev, u32 cmd, void *arg); > +}; > + > +/* > + * Defined and populated by subdev driver, exported as driver_data in > + * struct platform_device_id. > + */ > +struct xrt_subdev_drvdata { > + struct xrt_subdev_file_ops xsd_file_ops; > + struct xrt_subdev_drv_ops xsd_dev_ops; > +}; > + > +/* > + * Partially initialized by the parent driver, then, passed in as subdev driver's > + * platform data when creating subdev driver instance by calling platform > + * device register API (platform_device_register_data() or the likes). > + * > + * Once device register API returns, platform driver framework makes a copy of > + * this buffer and maintains its life cycle. The content of the buffer is > + * completely owned by subdev driver. > + * > + * Thus, parent driver should be very careful when it touches this buffer > + * again once it's handed over to subdev driver. And the data structure > + * should not contain pointers pointing to buffers that is managed by > + * other or parent drivers since it could have been freed before platform > + * data buffer is freed by platform driver framework. This sounds complicated and risky, why have two copies ? > + */ > +struct xrt_subdev_platdata { > + /* > + * Per driver instance callback. The pdev points to the instance. > + * Should always be defined for subdev driver to get service from root. > + */ > + xrt_subdev_root_cb_t xsp_root_cb; > + void *xsp_root_cb_arg; > + > + /* Something to associate w/ root for msg printing. */ > + const char *xsp_root_name; > + > + /* > + * Char dev support for this subdev instance. > + * Initialized by subdev driver. > + */ > + struct cdev xsp_cdev; > + struct device *xsp_sysdev; > + struct mutex xsp_devnode_lock; /* devnode lock */ > + struct completion xsp_devnode_comp; > + int xsp_devnode_ref; > + bool xsp_devnode_online; > + bool xsp_devnode_excl; > + > + /* > + * Subdev driver specific init data. The buffer should be embedded > + * in this data structure buffer after dtb, so that it can be freed > + * together with platform data. > + */ > + loff_t xsp_priv_off; /* Offset into this platform data buffer. */ > + size_t xsp_priv_len; > + > + /* > + * Populated by parent driver to describe the device tree for > + * the subdev driver to handle. Should always be last one since it's > + * of variable length. > + */ > + char xsp_dtb[sizeof(struct fdt_header)]; could be xsp_dtb[1] and save including the fdt headers just to get a size that doesn't matter. > +}; > + > +/* > + * this struct define the endpoints belong to the same subdevice > + */ > +struct xrt_subdev_ep_names { > + const char *ep_name; > + const char *regmap_name; > +}; > + > +struct xrt_subdev_endpoints { > + struct xrt_subdev_ep_names *xse_names; > + /* minimum number of endpoints to support the subdevice */ > + u32 xse_min_ep; see earlier comment about needed a null entry and checking for it. a 'size' element would be better here. > +}; > + > +struct subdev_match_arg { > + enum xrt_subdev_id id; > + int instance; > +}; > + > +bool xleaf_has_endpoint(struct platform_device *pdev, const char *endpoint_name); > +struct platform_device *xleaf_get_leaf(struct platform_device *pdev, > + xrt_subdev_match_t cb, void *arg); > + > +static inline bool subdev_match(enum xrt_subdev_id id, struct platform_device *pdev, void *arg) > +{ > + const struct subdev_match_arg *a = (struct subdev_match_arg *)arg; > + bool ret = (id == a->id && (pdev->id == a->instance || PLATFORM_DEVID_NONE == a->instance)); This statement is too complicated, turn this into an if-else > + > + return ret; > +} > + > +static inline bool xrt_subdev_match_epname(enum xrt_subdev_id id, > + struct platform_device *pdev, void *arg) > +{ > + return xleaf_has_endpoint(pdev, arg); This function is used only once. Just inline the function to the caller and remove this function. > +} > + > +static inline struct platform_device * > +xleaf_get_leaf_by_id(struct platform_device *pdev, > + enum xrt_subdev_id id, int instance) > +{ > + struct subdev_match_arg arg = { id, instance }; > + > + return xleaf_get_leaf(pdev, subdev_match, &arg); > +} > + > +static inline struct platform_device * > +xleaf_get_leaf_by_epname(struct platform_device *pdev, const char *name) > +{ > + return xleaf_get_leaf(pdev, xrt_subdev_match_epname, (void *)name); > +} > + > +static inline int xleaf_ioctl(struct platform_device *tgt, u32 cmd, void *arg) > +{ > + struct xrt_subdev_drvdata *drvdata = DEV_DRVDATA(tgt); > + > + return (*drvdata->xsd_dev_ops.xsd_ioctl)(tgt, cmd, arg); > +} > + > +int xleaf_put_leaf(struct platform_device *pdev, > + struct platform_device *leaf); > +int xleaf_create_group(struct platform_device *pdev, char *dtb); > +int xleaf_destroy_group(struct platform_device *pdev, int instance); > +int xleaf_wait_for_group_bringup(struct platform_device *pdev); > +void xleaf_hot_reset(struct platform_device *pdev); > +int xleaf_broadcast_event(struct platform_device *pdev, > + enum xrt_events evt, bool async); > +void xleaf_get_barres(struct platform_device *pdev, > + struct resource **res, uint bar_idx); > +void xleaf_get_root_id(struct platform_device *pdev, > + unsigned short *vendor, unsigned short *device, > + unsigned short *subvendor, unsigned short *subdevice); > +struct device *xleaf_register_hwmon(struct platform_device *pdev, > + const char *name, void *drvdata, > + const struct attribute_group **grps); > +void xleaf_unregister_hwmon(struct platform_device *pdev, struct device *hwmon); could better organize these decl's alphabetically. Also not intermix inlines and decls. > + > +/* > + * Character device helper APIs for use by leaf drivers > + */ > +static inline bool xleaf_devnode_enabled(struct xrt_subdev_drvdata *drvdata) > +{ > + return drvdata && drvdata->xsd_file_ops.xsf_ops.open; > +} > + > +int xleaf_devnode_create(struct platform_device *pdev, > + const char *file_name, const char *inst_name); > +int xleaf_devnode_destroy(struct platform_device *pdev); > + > +struct platform_device *xleaf_devnode_open_excl(struct inode *inode); > +struct platform_device *xleaf_devnode_open(struct inode *inode); > +void xleaf_devnode_close(struct inode *inode); > + > +/* Helpers. */ > +static inline void xrt_memcpy_fromio(void *buf, void __iomem *iomem, u32 size) > +{ Replace with mmio_insl/outsl > + int i; > + > + WARN_ON(size & 0x3); > + for (i = 0; i < size / 4; i++) > + ((u32 *)buf)[i] = ioread32((char *)(iomem) + sizeof(u32) * i); > +} > + > +static inline void xrt_memcpy_toio(void __iomem *iomem, void *buf, u32 size) > +{ > + int i; > + > + WARN_ON(size & 0x3); > + for (i = 0; i < size / 4; i++) > + iowrite32(((u32 *)buf)[i], ((char *)(iomem) + sizeof(u32) * i)); > +} > + > +int xleaf_register_driver(enum xrt_subdev_id id, struct platform_driver *drv, > + struct xrt_subdev_endpoints *eps); > +void xleaf_unregister_driver(enum xrt_subdev_id id); > + > +/* Module's init/fini routines for leaf driver in xrt-lib module */ > +void group_leaf_init_fini(bool init); > +void vsec_leaf_init_fini(bool init); > +void vsec_golden_leaf_init_fini(bool init); > +void devctl_leaf_init_fini(bool init); > +void axigate_leaf_init_fini(bool init); > +void icap_leaf_init_fini(bool init); > +void calib_leaf_init_fini(bool init); > +void qspi_leaf_init_fini(bool init); > +void mailbox_leaf_init_fini(bool init); > +void cmc_leaf_init_fini(bool init); > +void clkfreq_leaf_init_fini(bool init); > +void clock_leaf_init_fini(bool init); > +void ucs_leaf_init_fini(bool init); Shouldn't these be in the specific leaf drv ? > + > +#endif /* _XRT_LEAF_H_ */ > diff --git a/drivers/fpga/xrt/lib/cdev.c b/drivers/fpga/xrt/lib/cdev.c > new file mode 100644 > index 000000000000..7f104ab3d527 > --- /dev/null > +++ b/drivers/fpga/xrt/lib/cdev.c > @@ -0,0 +1,231 @@ > +// SPDX-License-Identifier: GPL-2.0 > +/* > + * Xilinx Alveo FPGA device node helper functions. > + * > + * Copyright (C) 2020-2021 Xilinx, Inc. > + * > + * Authors: > + * Cheng Zhen <maxz@xilinx.com> > + */ > + > +#include "xleaf.h" > + > +extern struct class *xrt_class; > + > +#define XRT_CDEV_DIR "xfpga" 'xfpga' is not very unique, maybe 'xrt' ? > +#define INODE2PDATA(inode) \ > + container_of((inode)->i_cdev, struct xrt_subdev_platdata, xsp_cdev) > +#define INODE2PDEV(inode) \ > + to_platform_device(kobj_to_dev((inode)->i_cdev->kobj.parent)) > +#define CDEV_NAME(sysdev) (strchr((sysdev)->kobj.name, '!') + 1) > + > +/* Allow it to be accessed from cdev. */ > +static void xleaf_devnode_allowed(struct platform_device *pdev) > +{ > + struct xrt_subdev_platdata *pdata = DEV_PDATA(pdev); > + > + /* Allow new opens. */ > + mutex_lock(&pdata->xsp_devnode_lock); > + pdata->xsp_devnode_online = true; > + mutex_unlock(&pdata->xsp_devnode_lock); > +} > + > +/* Turn off access from cdev and wait for all existing user to go away. */ > +static int xleaf_devnode_disallowed(struct platform_device *pdev) > +{ > + int ret = 0; > + struct xrt_subdev_platdata *pdata = DEV_PDATA(pdev); > + > + mutex_lock(&pdata->xsp_devnode_lock); > + > + /* Prevent new opens. */ > + pdata->xsp_devnode_online = false; > + /* Wait for existing user to close. */ > + while (!ret && pdata->xsp_devnode_ref) { > + int rc; > + > + mutex_unlock(&pdata->xsp_devnode_lock); > + rc = wait_for_completion_killable(&pdata->xsp_devnode_comp); > + mutex_lock(&pdata->xsp_devnode_lock); > + > + if (rc == -ERESTARTSYS) { > + /* Restore online state. */ > + pdata->xsp_devnode_online = true; > + xrt_err(pdev, "%s is in use, ref=%d", > + CDEV_NAME(pdata->xsp_sysdev), > + pdata->xsp_devnode_ref); > + ret = -EBUSY; > + } > + } > + > + mutex_unlock(&pdata->xsp_devnode_lock); > + > + return ret; > +} > + > +static struct platform_device * > +__xleaf_devnode_open(struct inode *inode, bool excl) > +{ > + struct xrt_subdev_platdata *pdata = INODE2PDATA(inode); > + struct platform_device *pdev = INODE2PDEV(inode); > + bool opened = false; > + > + mutex_lock(&pdata->xsp_devnode_lock); > + > + if (pdata->xsp_devnode_online) { > + if (excl && pdata->xsp_devnode_ref) { > + xrt_err(pdev, "%s has already been opened exclusively", > + CDEV_NAME(pdata->xsp_sysdev)); > + } else if (!excl && pdata->xsp_devnode_excl) { > + xrt_err(pdev, "%s has been opened exclusively", > + CDEV_NAME(pdata->xsp_sysdev)); > + } else { > + pdata->xsp_devnode_ref++; > + pdata->xsp_devnode_excl = excl; > + opened = true; > + xrt_info(pdev, "opened %s, ref=%d", > + CDEV_NAME(pdata->xsp_sysdev), > + pdata->xsp_devnode_ref); > + } > + } else { > + xrt_err(pdev, "%s is offline", CDEV_NAME(pdata->xsp_sysdev)); > + } > + > + mutex_unlock(&pdata->xsp_devnode_lock); > + > + pdev = opened ? pdev : NULL; > + return pdev; > +} > + > +struct platform_device * > +xleaf_devnode_open_excl(struct inode *inode) > +{ > + return __xleaf_devnode_open(inode, true); > +} > + > +struct platform_device * > +xleaf_devnode_open(struct inode *inode) > +{ > + return __xleaf_devnode_open(inode, false); > +} > +EXPORT_SYMBOL_GPL(xleaf_devnode_open); generally exported systems should have their decl's in include/linux/fpga/ These are in drivers/fpga/xrt/include/xleaf.h as exported, they should have a better than average prefix. maybe 'xrt_fpga_' > + > +void xleaf_devnode_close(struct inode *inode) > +{ > + struct xrt_subdev_platdata *pdata = INODE2PDATA(inode); > + struct platform_device *pdev = INODE2PDEV(inode); > + bool notify = false; > + > + mutex_lock(&pdata->xsp_devnode_lock); > + > + pdata->xsp_devnode_ref--; check before dec ? or at least warn if ref is already 0 > + if (pdata->xsp_devnode_ref == 0) { > + pdata->xsp_devnode_excl = false; > + notify = true; > + } > + if (notify) { > + xrt_info(pdev, "closed %s, ref=%d", > + CDEV_NAME(pdata->xsp_sysdev), pdata->xsp_devnode_ref); > + } else { > + xrt_info(pdev, "closed %s, notifying waiter", > + CDEV_NAME(pdata->xsp_sysdev)); > + } > + > + mutex_unlock(&pdata->xsp_devnode_lock); > + > + if (notify) > + complete(&pdata->xsp_devnode_comp); > +} > +EXPORT_SYMBOL_GPL(xleaf_devnode_close); > + > +static inline enum xrt_subdev_file_mode > +devnode_mode(struct xrt_subdev_drvdata *drvdata) > +{ > + return drvdata->xsd_file_ops.xsf_mode; > +} > + > +int xleaf_devnode_create(struct platform_device *pdev, const char *file_name, > + const char *inst_name) > +{ > + struct xrt_subdev_drvdata *drvdata = DEV_DRVDATA(pdev); > + struct xrt_subdev_file_ops *fops = &drvdata->xsd_file_ops; > + struct xrt_subdev_platdata *pdata = DEV_PDATA(pdev); > + struct cdev *cdevp; > + struct device *sysdev; > + int ret = 0; > + char fname[256]; will a /dev/xfpga* created for ever leaf device ? do they all really need /dev/ support ? > + > + mutex_init(&pdata->xsp_devnode_lock); > + init_completion(&pdata->xsp_devnode_comp); > + > + cdevp = &DEV_PDATA(pdev)->xsp_cdev; no cdev_alloc ? > + cdev_init(cdevp, &fops->xsf_ops); > + cdevp->owner = fops->xsf_ops.owner; > + cdevp->dev = MKDEV(MAJOR(fops->xsf_dev_t), pdev->id); > + > + /* > + * Set pdev as parent of cdev so that when pdev (and its platform > + * data) will not be freed when cdev is not freed. > + */ > + cdev_set_parent(cdevp, &DEV(pdev)->kobj); > + > + ret = cdev_add(cdevp, cdevp->dev, 1); > + if (ret) { > + xrt_err(pdev, "failed to add cdev: %d", ret); > + goto failed; > + } > + if (!file_name) > + file_name = pdev->name; > + if (!inst_name) { > + if (devnode_mode(drvdata) == XRT_SUBDEV_FILE_MULTI_INST) { > + snprintf(fname, sizeof(fname), "%s/%s/%s.%u", > + XRT_CDEV_DIR, DEV_PDATA(pdev)->xsp_root_name, > + file_name, pdev->id); > + } else { > + snprintf(fname, sizeof(fname), "%s/%s/%s", > + XRT_CDEV_DIR, DEV_PDATA(pdev)->xsp_root_name, > + file_name); > + } > + } else { > + snprintf(fname, sizeof(fname), "%s/%s/%s.%s", XRT_CDEV_DIR, > + DEV_PDATA(pdev)->xsp_root_name, file_name, inst_name); > + } > + sysdev = device_create(xrt_class, NULL, cdevp->dev, NULL, "%s", fname); > + if (IS_ERR(sysdev)) { > + ret = PTR_ERR(sysdev); > + xrt_err(pdev, "failed to create device node: %d", ret); > + goto failed; this calls device_destroy, but the create call failed, so is this needed ? > + } > + pdata->xsp_sysdev = sysdev; > + > + xleaf_devnode_allowed(pdev); > + > + xrt_info(pdev, "created (%d, %d): /dev/%s", > + MAJOR(cdevp->dev), pdev->id, fname); > + return 0; > + > +failed: > + device_destroy(xrt_class, cdevp->dev); > + cdev_del(cdevp); > + cdevp->owner = NULL; > + return ret; > +} > + > +int xleaf_devnode_destroy(struct platform_device *pdev) > +{ > + struct xrt_subdev_platdata *pdata = DEV_PDATA(pdev); > + struct cdev *cdevp = &pdata->xsp_cdev; > + dev_t dev = cdevp->dev; > + int rc; > + > + rc = xleaf_devnode_disallowed(pdev); > + if (rc) > + return rc; This return is not checked by xrt_subdev_destroy > + > + xrt_info(pdev, "removed (%d, %d): /dev/%s/%s", MAJOR(dev), MINOR(dev), > + XRT_CDEV_DIR, CDEV_NAME(pdata->xsp_sysdev)); > + device_destroy(xrt_class, cdevp->dev); > + pdata->xsp_sysdev = NULL; > + cdev_del(cdevp); > + return 0; > +} > diff --git a/drivers/fpga/xrt/lib/subdev.c b/drivers/fpga/xrt/lib/subdev.c > new file mode 100644 > index 000000000000..73552c549bdb > --- /dev/null > +++ b/drivers/fpga/xrt/lib/subdev.c > @@ -0,0 +1,871 @@ > +// SPDX-License-Identifier: GPL-2.0 > +/* > + * Xilinx Alveo FPGA device helper functions > + * > + * Copyright (C) 2020-2021 Xilinx, Inc. > + * > + * Authors: > + * Cheng Zhen <maxz@xilinx.com> > + */ > + > +#include <linux/platform_device.h> > +#include <linux/pci.h> > +#include <linux/vmalloc.h> > +#include "xleaf.h" > +#include "subdev_pool.h" > +#include "main.h" > +#include "metadata.h" > + > +#define DEV_IS_PCI(dev) ((dev)->bus == &pci_bus_type) > +static inline struct device *find_root(struct platform_device *pdev) > +{ > + struct device *d = DEV(pdev); > + > + while (!DEV_IS_PCI(d)) > + d = d->parent; Shouldn't the root have no parent ? Could then check if d->parent == NULL instead of bus type > + return d; > +} > + > +/* > + * It represents a holder of a subdev. One holder can repeatedly hold a subdev > + * as long as there is a unhold corresponding to a hold. > + */ > +struct xrt_subdev_holder { > + struct list_head xsh_holder_list; > + struct device *xsh_holder; > + int xsh_count; > + struct kref xsh_kref; general, i see this in struct xrt_subdev guessing 'xsh' is xrt subdev holder. why is this prefix needed for the elements ? consider removing it. > +}; > + > +/* > + * It represents a specific instance of platform driver for a subdev, which > + * provides services to its clients (another subdev driver or root driver). > + */ > +struct xrt_subdev { > + struct list_head xs_dev_list; > + struct list_head xs_holder_list; > + enum xrt_subdev_id xs_id; /* type of subdev */ > + struct platform_device *xs_pdev; /* a particular subdev inst */ > + struct completion xs_holder_comp; > +}; > + > +static struct xrt_subdev *xrt_subdev_alloc(void) > +{ > + struct xrt_subdev *sdev = vzalloc(sizeof(*sdev)); similar kzalloc as another patch. > + > + if (!sdev) > + return NULL; > + > + INIT_LIST_HEAD(&sdev->xs_dev_list); > + INIT_LIST_HEAD(&sdev->xs_holder_list); > + init_completion(&sdev->xs_holder_comp); > + return sdev; > +} > + > +static void xrt_subdev_free(struct xrt_subdev *sdev) > +{ > + vfree(sdev); > +} > + > +int xrt_subdev_root_request(struct platform_device *self, u32 cmd, void *arg) > +{ > + struct device *dev = DEV(self); > + struct xrt_subdev_platdata *pdata = DEV_PDATA(self); > + > + return (*pdata->xsp_root_cb)(dev->parent, pdata->xsp_root_cb_arg, cmd, arg); xrt_subdev_create does not check if pcb is valid. is a null is passed in, it will crash. there should at least be a warn or -INVALID returned there > +} > + > +/* > + * Subdev common sysfs nodes. > + */ > +static ssize_t holders_show(struct device *dev, struct device_attribute *attr, char *buf) > +{ > + ssize_t len; > + struct platform_device *pdev = to_platform_device(dev); > + struct xrt_root_ioctl_get_holders holders = { pdev, buf, 1024 }; is 1024 a guess ? > + > + len = xrt_subdev_root_request(pdev, XRT_ROOT_GET_LEAF_HOLDERS, &holders); take a closer look at xrt_subdev_get_holders() it stops after it goes past len. > + if (len >= holders.xpigh_holder_buf_len) > + return len; > + buf[len] = '\n'; > + return len + 1; > +} > +static DEVICE_ATTR_RO(holders); > + > +static struct attribute *xrt_subdev_attrs[] = { > + &dev_attr_holders.attr, > + NULL, > +}; > + > +static ssize_t metadata_output(struct file *filp, struct kobject *kobj, > + struct bin_attribute *attr, char *buf, loff_t off, size_t count) > +{ > + struct device *dev = kobj_to_dev(kobj); > + struct platform_device *pdev = to_platform_device(dev); > + struct xrt_subdev_platdata *pdata = DEV_PDATA(pdev); > + unsigned char *blob; > + unsigned long size; > + ssize_t ret = 0; > + > + blob = pdata->xsp_dtb; > + size = xrt_md_size(dev, blob); > + if (size == XRT_MD_INVALID_LENGTH) { > + ret = -EINVAL; > + goto failed; > + } > + > + if (off >= size) > + goto failed; silently failed because ret = 0 ? > + > + if (off + count > size) > + count = size - off; truncating is ok ? > + memcpy(buf, blob + off, count); > + > + ret = count; > +failed: > + return ret; > +} > + > +static struct bin_attribute meta_data_attr = { > + .attr = { > + .name = "metadata", > + .mode = 0400 > + }, > + .read = metadata_output, > + .size = 0 > +}; > + > +static struct bin_attribute *xrt_subdev_bin_attrs[] = { > + &meta_data_attr, is giving the average user access to the meta data a good idea ? this seems like a developer only need. > + NULL, > +}; > + > +static const struct attribute_group xrt_subdev_attrgroup = { > + .attrs = xrt_subdev_attrs, > + .bin_attrs = xrt_subdev_bin_attrs, > +}; > + > +/* > + * Given the device metadata, parse it to get IO ranges and construct > + * resource array. > + */ > +static int > +xrt_subdev_getres(struct device *parent, enum xrt_subdev_id id, > + char *dtb, struct resource **res, int *res_num) > +{ > + struct xrt_subdev_platdata *pdata; > + struct resource *pci_res = NULL; > + const u64 *bar_range; > + const u32 *bar_idx; > + char *ep_name = NULL, *regmap = NULL; > + uint bar; > + int count1 = 0, count2 = 0, ret; > + > + if (!dtb) > + return -EINVAL; > + > + pdata = DEV_PDATA(to_platform_device(parent)); > + > + /* go through metadata and count endpoints in it */ > + for (xrt_md_get_next_endpoint(parent, dtb, NULL, NULL, &ep_name, ®map); ep_name; Ugly. Can you preprocess the dtb into a list of end points ? > + xrt_md_get_next_endpoint(parent, dtb, ep_name, regmap, &ep_name, ®map)) { > + ret = xrt_md_get_prop(parent, dtb, ep_name, regmap, > + XRT_MD_PROP_IO_OFFSET, (const void **)&bar_range, NULL); > + if (!ret) > + count1++; > + } > + if (!count1) > + return 0; > + > + /* allocate resource array for all endpoints been found in metadata */ > + *res = vzalloc(sizeof(**res) * count1); > + > + /* go through all endpoints again and get IO range for each endpoint */ > + for (xrt_md_get_next_endpoint(parent, dtb, NULL, NULL, &ep_name, ®map); ep_name; > + xrt_md_get_next_endpoint(parent, dtb, ep_name, regmap, &ep_name, ®map)) { > + ret = xrt_md_get_prop(parent, dtb, ep_name, regmap, > + XRT_MD_PROP_IO_OFFSET, (const void **)&bar_range, NULL); > + if (ret) > + continue; > + xrt_md_get_prop(parent, dtb, ep_name, regmap, > + XRT_MD_PROP_BAR_IDX, (const void **)&bar_idx, NULL); bar can fail, but bar idx can not. should add an assert here > + bar = bar_idx ? be32_to_cpu(*bar_idx) : 0; > + xleaf_get_barres(to_platform_device(parent), &pci_res, bar); > + (*res)[count2].start = pci_res->start + > + be64_to_cpu(bar_range[0]); > + (*res)[count2].end = pci_res->start + > + be64_to_cpu(bar_range[0]) + > + be64_to_cpu(bar_range[1]) - 1; > + (*res)[count2].flags = IORESOURCE_MEM; any irqs need handling? > + /* check if there is conflicted resource */ > + ret = request_resource(pci_res, *res + count2); > + if (ret) { > + dev_err(parent, "Conflict resource %pR\n", *res + count2); > + vfree(*res); > + *res_num = 0; > + *res = NULL; > + return ret; > + } > + release_resource(*res + count2); > + > + (*res)[count2].parent = pci_res; > + > + xrt_md_find_endpoint(parent, pdata->xsp_dtb, ep_name, > + regmap, &(*res)[count2].name); > + > + count2++; > + } > + > + WARN_ON(count1 != count2); > + *res_num = count2; > + > + return 0; > +} > + > +static inline enum xrt_subdev_file_mode > +xleaf_devnode_mode(struct xrt_subdev_drvdata *drvdata) > +{ > + return drvdata->xsd_file_ops.xsf_mode; > +} > + > +static bool xrt_subdev_cdev_auto_creation(struct platform_device *pdev) > +{ > + struct xrt_subdev_drvdata *drvdata = DEV_DRVDATA(pdev); > + > + if (!drvdata) > + return false; > + > + return xleaf_devnode_enabled(drvdata) && > + (xleaf_devnode_mode(drvdata) == XRT_SUBDEV_FILE_DEFAULT || > + (xleaf_devnode_mode(drvdata) == XRT_SUBDEV_FILE_MULTI_INST)); This is complicated to check, split into checking the call and then checking its side effects. > +} > + > +static struct xrt_subdev * > +xrt_subdev_create(struct device *parent, enum xrt_subdev_id id, > + xrt_subdev_root_cb_t pcb, void *pcb_arg, char *dtb) > +{ > + struct xrt_subdev *sdev = NULL; > + struct platform_device *pdev = NULL; > + struct xrt_subdev_platdata *pdata = NULL; > + unsigned long dtb_len = 0; > + size_t pdata_sz; > + int inst = PLATFORM_DEVID_NONE; > + struct resource *res = NULL; > + int res_num = 0; > + > + sdev = xrt_subdev_alloc(); > + if (!sdev) { > + dev_err(parent, "failed to alloc subdev for ID %d", id); > + goto fail; > + } > + sdev->xs_id = id; > + > + if (dtb) { > + xrt_md_pack(parent, dtb); > + dtb_len = xrt_md_size(parent, dtb); > + if (dtb_len == XRT_MD_INVALID_LENGTH) { > + dev_err(parent, "invalid metadata len %ld", dtb_len); > + goto fail; > + } > + } > + pdata_sz = sizeof(struct xrt_subdev_platdata) + dtb_len - 1; -1 ? if dtb_len == 0, pdata_sz be too small. > + > + /* Prepare platform data passed to subdev. */ > + pdata = vzalloc(pdata_sz); > + if (!pdata) > + goto fail; > + > + pdata->xsp_root_cb = pcb; > + pdata->xsp_root_cb_arg = pcb_arg; > + memcpy(pdata->xsp_dtb, dtb, dtb_len); > + if (id == XRT_SUBDEV_GRP) { > + /* Group can only be created by root driver. */ > + pdata->xsp_root_name = dev_name(parent); > + } else { > + struct platform_device *grp = to_platform_device(parent); > + /* Leaf can only be created by group driver. */ > + WARN_ON(strcmp(xrt_drv_name(XRT_SUBDEV_GRP), platform_get_device_id(grp)->name)); > + pdata->xsp_root_name = DEV_PDATA(grp)->xsp_root_name; > + } > + > + /* Obtain dev instance number. */ > + inst = xrt_drv_get_instance(id); > + if (inst < 0) { > + dev_err(parent, "failed to obtain instance: %d", inst); > + goto fail; > + } > + > + /* Create subdev. */ > + if (id == XRT_SUBDEV_GRP) { > + pdev = platform_device_register_data(parent, xrt_drv_name(XRT_SUBDEV_GRP), > + inst, pdata, pdata_sz); > + } else { > + int rc = xrt_subdev_getres(parent, id, dtb, &res, &res_num); > + > + if (rc) { > + dev_err(parent, "failed to get resource for %s.%d: %d", > + xrt_drv_name(id), inst, rc); > + goto fail; > + } > + pdev = platform_device_register_resndata(parent, xrt_drv_name(id), > + inst, res, res_num, pdata, pdata_sz); > + vfree(res); > + } a small optimization platform_device_register_data is a wrapper to platform_device_register_resndata. with initial values for res, res_num, just one call need to be made. > + if (IS_ERR(pdev)) { > + dev_err(parent, "failed to create subdev for %s inst %d: %ld", > + xrt_drv_name(id), inst, PTR_ERR(pdev)); > + goto fail; > + } > + sdev->xs_pdev = pdev; > + > + if (device_attach(DEV(pdev)) != 1) { > + xrt_err(pdev, "failed to attach"); > + goto fail; > + } > + > + if (sysfs_create_group(&DEV(pdev)->kobj, &xrt_subdev_attrgroup)) > + xrt_err(pdev, "failed to create sysfs group"); no failure ? > + > + /* > + * Create sysfs sym link under root for leaves > + * under random groups for easy access to them. > + */ > + if (id != XRT_SUBDEV_GRP) { > + if (sysfs_create_link(&find_root(pdev)->kobj, > + &DEV(pdev)->kobj, dev_name(DEV(pdev)))) { > + xrt_err(pdev, "failed to create sysfs link"); > + } > + } > + > + /* All done, ready to handle req thru cdev. */ > + if (xrt_subdev_cdev_auto_creation(pdev)) > + xleaf_devnode_create(pdev, DEV_DRVDATA(pdev)->xsd_file_ops.xsf_dev_name, NULL); > + > + vfree(pdata); > + return sdev; > + > +fail: Instead of adding checks in the error handling block, add more specific labels and gotos. I think i have noticed this before, so apply this advice generally. > + vfree(pdata); > + if (sdev && !IS_ERR_OR_NULL(sdev->xs_pdev)) > + platform_device_unregister(sdev->xs_pdev); > + if (inst >= 0) > + xrt_drv_put_instance(id, inst); > + xrt_subdev_free(sdev); > + return NULL; > +} > + > +static void xrt_subdev_destroy(struct xrt_subdev *sdev) > +{ > + struct platform_device *pdev = sdev->xs_pdev; > + int inst = pdev->id; > + struct device *dev = DEV(pdev); > + > + /* Take down the device node */ > + if (xrt_subdev_cdev_auto_creation(pdev)) > + xleaf_devnode_destroy(pdev); > + if (sdev->xs_id != XRT_SUBDEV_GRP) > + sysfs_remove_link(&find_root(pdev)->kobj, dev_name(dev)); > + sysfs_remove_group(&dev->kobj, &xrt_subdev_attrgroup); > + platform_device_unregister(pdev); > + xrt_drv_put_instance(sdev->xs_id, inst); > + xrt_subdev_free(sdev); > +} > + > +struct platform_device * > +xleaf_get_leaf(struct platform_device *pdev, xrt_subdev_match_t match_cb, void *match_arg) > +{ > + int rc; > + struct xrt_root_ioctl_get_leaf get_leaf = { > + pdev, match_cb, match_arg, }; > + > + rc = xrt_subdev_root_request(pdev, XRT_ROOT_GET_LEAF, &get_leaf); > + if (rc) > + return NULL; > + return get_leaf.xpigl_leaf; > +} > +EXPORT_SYMBOL_GPL(xleaf_get_leaf); > + > +bool xleaf_has_endpoint(struct platform_device *pdev, const char *endpoint_name) > +{ > + struct resource *res; > + int i; whitespace > + > + for (i = 0, res = platform_get_resource(pdev, IORESOURCE_MEM, 0); > + res; > + res = platform_get_resource(pdev, IORESOURCE_MEM, ++i)) { Do not inc i inside the call, do it at the bottom of the loop > + if (!strncmp(res->name, endpoint_name, strlen(res->name) + 1)) shouldn't you also check the strlen matches ? > + return true; > + } > + > + return false; > +} > +EXPORT_SYMBOL_GPL(xleaf_has_endpoint); > + > +int xleaf_put_leaf(struct platform_device *pdev, struct platform_device *leaf) > +{ > + struct xrt_root_ioctl_put_leaf put_leaf = { pdev, leaf }; > + > + return xrt_subdev_root_request(pdev, XRT_ROOT_PUT_LEAF, &put_leaf); > +} > +EXPORT_SYMBOL_GPL(xleaf_put_leaf); > + > +int xleaf_create_group(struct platform_device *pdev, char *dtb) > +{ > + return xrt_subdev_root_request(pdev, XRT_ROOT_CREATE_GROUP, dtb); > +} > +EXPORT_SYMBOL_GPL(xleaf_create_group); > + > +int xleaf_destroy_group(struct platform_device *pdev, int instance) > +{ > + return xrt_subdev_root_request(pdev, XRT_ROOT_REMOVE_GROUP, (void *)(uintptr_t)instance); Instead of these clunky casts, why not make the type of the args void * and leave it to the handler to cast. this would unify the signature of these functions somewhat. > +} > +EXPORT_SYMBOL_GPL(xleaf_destroy_group); > + > +int xleaf_wait_for_group_bringup(struct platform_device *pdev) > +{ > + return xrt_subdev_root_request(pdev, XRT_ROOT_WAIT_GROUP_BRINGUP, NULL); > +} > +EXPORT_SYMBOL_GPL(xleaf_wait_for_group_bringup); > + > +static ssize_t > +xrt_subdev_get_holders(struct xrt_subdev *sdev, char *buf, size_t len) > +{ > + const struct list_head *ptr; > + struct xrt_subdev_holder *h; > + ssize_t n = 0; > + > + list_for_each(ptr, &sdev->xs_holder_list) { > + h = list_entry(ptr, struct xrt_subdev_holder, xsh_holder_list); > + n += snprintf(buf + n, len - n, "%s:%d ", > + dev_name(h->xsh_holder), kref_read(&h->xsh_kref)); > + if (n >= (len - 1)) This is the overrun i mentioned above. > + break; > + } > + return n; > +} > + > +void xrt_subdev_pool_init(struct device *dev, struct xrt_subdev_pool *spool) > +{ > + INIT_LIST_HEAD(&spool->xsp_dev_list); > + spool->xsp_owner = dev; > + mutex_init(&spool->xsp_lock); > + spool->xsp_closing = false; > +} > + > +static void xrt_subdev_free_holder(struct xrt_subdev_holder *holder) > +{ > + list_del(&holder->xsh_holder_list); > + vfree(holder); > +} > + > +static void xrt_subdev_pool_wait_for_holders(struct xrt_subdev_pool *spool, struct xrt_subdev *sdev) > +{ > + const struct list_head *ptr, *next; > + char holders[128]; > + struct xrt_subdev_holder *holder; > + struct mutex *lk = &spool->xsp_lock; > + > + WARN_ON(!mutex_is_locked(lk)); > + > + while (!list_empty(&sdev->xs_holder_list)) { > + int rc; > + > + /* It's most likely a bug if we ever enters this loop. */ > + xrt_subdev_get_holders(sdev, holders, sizeof(holders)); will overrun, error not reported. > + xrt_err(sdev->xs_pdev, "awaits holders: %s", holders); > + mutex_unlock(lk); > + rc = wait_for_completion_killable(&sdev->xs_holder_comp); > + mutex_lock(lk); > + if (rc == -ERESTARTSYS) { > + xrt_err(sdev->xs_pdev, "give up on waiting for holders, clean up now"); > + list_for_each_safe(ptr, next, &sdev->xs_holder_list) { > + holder = list_entry(ptr, struct xrt_subdev_holder, xsh_holder_list); > + xrt_subdev_free_holder(holder); > + } > + } > + } > +} > + > +void xrt_subdev_pool_fini(struct xrt_subdev_pool *spool) > +{ > + struct list_head *dl = &spool->xsp_dev_list; > + struct mutex *lk = &spool->xsp_lock; > + > + mutex_lock(lk); > + i am wondering about the locking here. xsp_closing is only set to true in this function. the unlocking then relocking in the loop is strange, why do you need to do this ? > + if (spool->xsp_closing) { > + mutex_unlock(lk); > + return; > + } > + > + spool->xsp_closing = true; > + /* Remove subdev in the reverse order of added. */ > + while (!list_empty(dl)) { > + struct xrt_subdev *sdev = list_first_entry(dl, struct xrt_subdev, xs_dev_list); > + > + xrt_subdev_pool_wait_for_holders(spool, sdev); > + list_del(&sdev->xs_dev_list); > + mutex_unlock(lk); > + xrt_subdev_destroy(sdev); > + mutex_lock(lk); > + } > + > + mutex_unlock(lk); > +} > + > +static struct xrt_subdev_holder *xrt_subdev_find_holder(struct xrt_subdev *sdev, > + struct device *holder_dev) > +{ > + struct list_head *hl = &sdev->xs_holder_list; > + struct xrt_subdev_holder *holder; > + const struct list_head *ptr; > + > + list_for_each(ptr, hl) { > + holder = list_entry(ptr, struct xrt_subdev_holder, xsh_holder_list); > + if (holder->xsh_holder == holder_dev) > + return holder; > + } > + return NULL; > +} > + > +static int xrt_subdev_hold(struct xrt_subdev *sdev, struct device *holder_dev) > +{ > + struct xrt_subdev_holder *holder = xrt_subdev_find_holder(sdev, holder_dev); > + struct list_head *hl = &sdev->xs_holder_list; > + > + if (!holder) { > + holder = vzalloc(sizeof(*holder)); > + if (!holder) > + return -ENOMEM; > + holder->xsh_holder = holder_dev; > + kref_init(&holder->xsh_kref); > + list_add_tail(&holder->xsh_holder_list, hl); > + } else { > + kref_get(&holder->xsh_kref); > + } > + > + return 0; > +} > + > +static void xrt_subdev_free_holder_kref(struct kref *kref) > +{ > + struct xrt_subdev_holder *holder = container_of(kref, struct xrt_subdev_holder, xsh_kref); > + > + xrt_subdev_free_holder(holder); > +} > + > +static int > +xrt_subdev_release(struct xrt_subdev *sdev, struct device *holder_dev) > +{ > + struct xrt_subdev_holder *holder = xrt_subdev_find_holder(sdev, holder_dev); > + struct list_head *hl = &sdev->xs_holder_list; > + > + if (!holder) { > + dev_err(holder_dev, "can't release, %s did not hold %s", > + dev_name(holder_dev), dev_name(DEV(sdev->xs_pdev))); > + return -EINVAL; > + } > + kref_put(&holder->xsh_kref, xrt_subdev_free_holder_kref); > + > + /* kref_put above may remove holder from list. */ > + if (list_empty(hl)) > + complete(&sdev->xs_holder_comp); > + return 0; > +} > + > +int xrt_subdev_pool_add(struct xrt_subdev_pool *spool, enum xrt_subdev_id id, > + xrt_subdev_root_cb_t pcb, void *pcb_arg, char *dtb) > +{ > + struct mutex *lk = &spool->xsp_lock; > + struct list_head *dl = &spool->xsp_dev_list; > + struct xrt_subdev *sdev; > + int ret = 0; > + > + sdev = xrt_subdev_create(spool->xsp_owner, id, pcb, pcb_arg, dtb); > + if (sdev) { > + mutex_lock(lk); > + if (spool->xsp_closing) { > + /* No new subdev when pool is going away. */ > + xrt_err(sdev->xs_pdev, "pool is closing"); > + ret = -ENODEV; > + } else { > + list_add(&sdev->xs_dev_list, dl); > + } > + mutex_unlock(lk); > + if (ret) > + xrt_subdev_destroy(sdev); > + } else { > + ret = -EINVAL; > + } > + > + ret = ret ? ret : sdev->xs_pdev->id; > + return ret; > +} > + > +int xrt_subdev_pool_del(struct xrt_subdev_pool *spool, enum xrt_subdev_id id, int instance) > +{ > + const struct list_head *ptr; > + struct mutex *lk = &spool->xsp_lock; > + struct list_head *dl = &spool->xsp_dev_list; > + struct xrt_subdev *sdev; > + int ret = -ENOENT; > + > + mutex_lock(lk); > + list_for_each(ptr, dl) { > + sdev = list_entry(ptr, struct xrt_subdev, xs_dev_list); > + if (sdev->xs_id != id || sdev->xs_pdev->id != instance) > + continue; > + xrt_subdev_pool_wait_for_holders(spool, sdev); > + list_del(&sdev->xs_dev_list); > + ret = 0; > + break; > + } > + mutex_unlock(lk); > + if (ret) > + return ret; > + > + xrt_subdev_destroy(sdev); > + return 0; > +} > + > +static int xrt_subdev_pool_get_impl(struct xrt_subdev_pool *spool, xrt_subdev_match_t match, > + void *arg, struct device *holder_dev, struct xrt_subdev **sdevp) > +{ > + const struct list_head *ptr; > + struct mutex *lk = &spool->xsp_lock; > + struct list_head *dl = &spool->xsp_dev_list; > + struct xrt_subdev *sdev = NULL; > + int ret = -ENOENT; > + > + mutex_lock(lk); > + > + if (match == XRT_SUBDEV_MATCH_PREV) { > + struct platform_device *pdev = (struct platform_device *)arg; > + struct xrt_subdev *d = NULL; > + > + if (!pdev) { > + sdev = list_empty(dl) ? NULL : > + list_last_entry(dl, struct xrt_subdev, xs_dev_list); > + } else { > + list_for_each(ptr, dl) { > + d = list_entry(ptr, struct xrt_subdev, xs_dev_list); > + if (d->xs_pdev != pdev) > + continue; > + if (!list_is_first(ptr, dl)) > + sdev = list_prev_entry(d, xs_dev_list); > + break; > + } > + } > + } else if (match == XRT_SUBDEV_MATCH_NEXT) { > + struct platform_device *pdev = (struct platform_device *)arg; > + struct xrt_subdev *d = NULL; > + > + if (!pdev) { > + sdev = list_first_entry_or_null(dl, struct xrt_subdev, xs_dev_list); > + } else { > + list_for_each(ptr, dl) { > + d = list_entry(ptr, struct xrt_subdev, xs_dev_list); > + if (d->xs_pdev != pdev) > + continue; > + if (!list_is_last(ptr, dl)) > + sdev = list_next_entry(d, xs_dev_list); > + break; > + } > + } > + } else { > + list_for_each(ptr, dl) { > + struct xrt_subdev *d = NULL; > + > + d = list_entry(ptr, struct xrt_subdev, xs_dev_list); > + if (d && !match(d->xs_id, d->xs_pdev, arg)) > + continue; > + sdev = d; > + break; > + } > + } 3 similar blocks of code This looks like it could be refactored into this else case and minor changes for match_next/prev > + > + if (sdev) > + ret = xrt_subdev_hold(sdev, holder_dev); > + > + mutex_unlock(lk); > + > + if (!ret) > + *sdevp = sdev; > + return ret; > +} > + > +int xrt_subdev_pool_get(struct xrt_subdev_pool *spool, xrt_subdev_match_t match, void *arg, > + struct device *holder_dev, struct platform_device **pdevp) > +{ > + int rc; > + struct xrt_subdev *sdev; > + > + rc = xrt_subdev_pool_get_impl(spool, match, arg, holder_dev, &sdev); > + if (rc) { > + if (rc != -ENOENT) > + dev_err(holder_dev, "failed to hold device: %d", rc); > + return rc; > + } > + > + if (!DEV_IS_PCI(holder_dev)) { ! root_dev() > + xrt_dbg(to_platform_device(holder_dev), "%s <<==== %s", > + dev_name(holder_dev), dev_name(DEV(sdev->xs_pdev))); > + } > + > + *pdevp = sdev->xs_pdev; > + return 0; > +} > + > +static int xrt_subdev_pool_put_impl(struct xrt_subdev_pool *spool, struct platform_device *pdev, > + struct device *holder_dev) > +{ > + const struct list_head *ptr; > + struct mutex *lk = &spool->xsp_lock; > + struct list_head *dl = &spool->xsp_dev_list; > + struct xrt_subdev *sdev; > + int ret = -ENOENT; > + > + mutex_lock(lk); > + list_for_each(ptr, dl) { > + sdev = list_entry(ptr, struct xrt_subdev, xs_dev_list); > + if (sdev->xs_pdev != pdev) > + continue; Could this and similar looping be avoided by storing sdev in pdev ? > + ret = xrt_subdev_release(sdev, holder_dev); > + break; > + } > + mutex_unlock(lk); > + > + return ret; > +} > + > +int xrt_subdev_pool_put(struct xrt_subdev_pool *spool, struct platform_device *pdev, > + struct device *holder_dev) > +{ > + int ret = xrt_subdev_pool_put_impl(spool, pdev, holder_dev); > + > + if (ret) > + return ret; > + > + if (!DEV_IS_PCI(holder_dev)) { ! root_dev() or similar. If you really need to use DEV_IS_PCI, do it only once so when you need to change something you don not have to find all the calls to DEV_IS_PCI. > + xrt_dbg(to_platform_device(holder_dev), "%s <<==X== %s", > + dev_name(holder_dev), dev_name(DEV(pdev))); > + } > + return 0; > +} > + > +void xrt_subdev_pool_trigger_event(struct xrt_subdev_pool *spool, enum xrt_events e) > +{ > + struct platform_device *tgt = NULL; > + struct xrt_subdev *sdev = NULL; > + struct xrt_event evt; > + > + while (!xrt_subdev_pool_get_impl(spool, XRT_SUBDEV_MATCH_NEXT, > + tgt, spool->xsp_owner, &sdev)) { > + tgt = sdev->xs_pdev; > + evt.xe_evt = e; > + evt.xe_subdev.xevt_subdev_id = sdev->xs_id; > + evt.xe_subdev.xevt_subdev_instance = tgt->id; > + xrt_subdev_root_request(tgt, XRT_ROOT_EVENT, &evt); > + xrt_subdev_pool_put_impl(spool, tgt, spool->xsp_owner); > + } > +} > + > +void xrt_subdev_pool_handle_event(struct xrt_subdev_pool *spool, struct xrt_event *evt) > +{ > + struct platform_device *tgt = NULL; > + struct xrt_subdev *sdev = NULL; > + > + while (!xrt_subdev_pool_get_impl(spool, XRT_SUBDEV_MATCH_NEXT, > + tgt, spool->xsp_owner, &sdev)) { > + tgt = sdev->xs_pdev; > + xleaf_ioctl(tgt, XRT_XLEAF_EVENT, evt); > + xrt_subdev_pool_put_impl(spool, tgt, spool->xsp_owner); > + } > +} > + > +ssize_t xrt_subdev_pool_get_holders(struct xrt_subdev_pool *spool, > + struct platform_device *pdev, char *buf, size_t len) > +{ > + const struct list_head *ptr; > + struct mutex *lk = &spool->xsp_lock; > + struct list_head *dl = &spool->xsp_dev_list; > + struct xrt_subdev *sdev; > + ssize_t ret = 0; > + > + mutex_lock(lk); > + list_for_each(ptr, dl) { > + sdev = list_entry(ptr, struct xrt_subdev, xs_dev_list); > + if (sdev->xs_pdev != pdev) > + continue; > + ret = xrt_subdev_get_holders(sdev, buf, len); > + break; > + } > + mutex_unlock(lk); > + > + return ret; > +} > +EXPORT_SYMBOL_GPL(xrt_subdev_pool_get_holders); > + > +int xleaf_broadcast_event(struct platform_device *pdev, enum xrt_events evt, bool async) > +{ > + struct xrt_event e = { evt, }; > + u32 cmd = async ? XRT_ROOT_EVENT_ASYNC : XRT_ROOT_EVENT; > + > + WARN_ON(evt == XRT_EVENT_POST_CREATION || evt == XRT_EVENT_PRE_REMOVAL); > + return xrt_subdev_root_request(pdev, cmd, &e); > +} > +EXPORT_SYMBOL_GPL(xleaf_broadcast_event); > + > +void xleaf_hot_reset(struct platform_device *pdev) > +{ > + xrt_subdev_root_request(pdev, XRT_ROOT_HOT_RESET, NULL); > +} > +EXPORT_SYMBOL_GPL(xleaf_hot_reset); > + > +void xleaf_get_barres(struct platform_device *pdev, struct resource **res, uint bar_idx) > +{ > + struct xrt_root_ioctl_get_res arg = { 0 }; > + > + if (bar_idx > PCI_STD_RESOURCE_END) { > + xrt_err(pdev, "Invalid bar idx %d", bar_idx); > + *res = NULL; > + return; > + } > + > + xrt_subdev_root_request(pdev, XRT_ROOT_GET_RESOURCE, &arg); > + > + *res = &arg.xpigr_res[bar_idx]; is this correct ? do all res need to be found to return a single one ? > +} > + > +void xleaf_get_root_id(struct platform_device *pdev, unsigned short *vendor, unsigned short *device, > + unsigned short *subvendor, unsigned short *subdevice) > +{ > + struct xrt_root_ioctl_get_id id = { 0 }; > + > + xrt_subdev_root_request(pdev, XRT_ROOT_GET_ID, (void *)&id); > + if (vendor) > + *vendor = id.xpigi_vendor_id; > + if (device) > + *device = id.xpigi_device_id; > + if (subvendor) > + *subvendor = id.xpigi_sub_vendor_id; > + if (subdevice) > + *subdevice = id.xpigi_sub_device_id; not setting anything because user passed in all nulls would make this function a noop. > +} > + > +struct device *xleaf_register_hwmon(struct platform_device *pdev, const char *name, void *drvdata, > + const struct attribute_group **grps) > +{ > + struct xrt_root_ioctl_hwmon hm = { true, name, drvdata, grps, }; > + > + xrt_subdev_root_request(pdev, XRT_ROOT_HWMON, (void *)&hm); > + return hm.xpih_hwmon_dev; > +} > + > +void xleaf_unregister_hwmon(struct platform_device *pdev, struct device *hwmon) > +{ > + struct xrt_root_ioctl_hwmon hm = { false, }; > + > + hm.xpih_hwmon_dev = hwmon; > + xrt_subdev_root_request(pdev, XRT_ROOT_HWMON, (void *)&hm); > +} > diff --git a/drivers/fpga/xrt/lib/subdev_pool.h b/drivers/fpga/xrt/lib/subdev_pool.h > new file mode 100644 > index 000000000000..50a8490e0e41 apologies for delay, was busy. If it seems like i forgot a train of thought, i did. > --- /dev/null > +++ b/drivers/fpga/xrt/lib/subdev_pool.h > @@ -0,0 +1,53 @@ > +/* SPDX-License-Identifier: GPL-2.0 */ > +/* > + * Header file for Xilinx Runtime (XRT) driver > + * > + * Copyright (C) 2020-2021 Xilinx, Inc. > + * > + * Authors: > + * Cheng Zhen <maxz@xilinx.com> > + */ > + > +#ifndef _XRT_SUBDEV_POOL_H_ > +#define _XRT_SUBDEV_POOL_H_ > + > +#include "xroot.h" > + > +/* > + * It manages a list of xrt_subdevs for root and group drivers. 'It' does not have a lot of context, better would be The xrt_subdev_pool struct .. > + */ > +struct xrt_subdev_pool { > + struct list_head xsp_dev_list; > + struct device *xsp_owner; > + struct mutex xsp_lock; /* pool lock */ Header files should be self contained, a quick look at xroot.h makes me suspicious that device and mutex decls assume the includer has added their headers before this one > + bool xsp_closing; If you thing additional state will be needed, you could change this to a bitfield. sizewise with compiler padding i don't think the size would change. > +}; > + > +/* > + * Subdev pool API for root and group drivers only. 'API' makes me think these should go in include/linux/fpga Do/will these functions get called outside of the drivers/fpga ? > + */ > +void xrt_subdev_pool_init(struct device *dev, > + struct xrt_subdev_pool *spool); > +void xrt_subdev_pool_fini(struct xrt_subdev_pool *spool); > +int xrt_subdev_pool_get(struct xrt_subdev_pool *spool, > + xrt_subdev_match_t match, > + void *arg, struct device *holder_dev, > + struct platform_device **pdevp); > +int xrt_subdev_pool_put(struct xrt_subdev_pool *spool, > + struct platform_device *pdev, > + struct device *holder_dev); > +int xrt_subdev_pool_add(struct xrt_subdev_pool *spool, > + enum xrt_subdev_id id, xrt_subdev_root_cb_t pcb, > + void *pcb_arg, char *dtb); > +int xrt_subdev_pool_del(struct xrt_subdev_pool *spool, > + enum xrt_subdev_id id, int instance); > +ssize_t xrt_subdev_pool_get_holders(struct xrt_subdev_pool *spool, > + struct platform_device *pdev, > + char *buf, size_t len); > + > +void xrt_subdev_pool_trigger_event(struct xrt_subdev_pool *spool, > + enum xrt_events evt); > +void xrt_subdev_pool_handle_event(struct xrt_subdev_pool *spool, > + struct xrt_event *evt); > + > +#endif /* _XRT_SUBDEV_POOL_H_ */ > diff --git a/drivers/fpga/xrt/lib/xroot.c b/drivers/fpga/xrt/lib/xroot.c > new file mode 100644 > index 000000000000..3dc7b0243277 > --- /dev/null > +++ b/drivers/fpga/xrt/lib/xroot.c > @@ -0,0 +1,598 @@ > +// SPDX-License-Identifier: GPL-2.0 > +/* > + * Xilinx Alveo FPGA Root Functions > + * > + * Copyright (C) 2020-2021 Xilinx, Inc. > + * > + * Authors: > + * Cheng Zhen <maxz@xilinx.com> > + */ > + > +#include <linux/module.h> > +#include <linux/pci.h> > +#include <linux/hwmon.h> > +#include "xroot.h" > +#include "subdev_pool.h" > +#include "group.h" > +#include "metadata.h" > + > +#define XROOT_PDEV(xr) ((xr)->pdev) > +#define XROOT_DEV(xr) (&(XROOT_PDEV(xr)->dev)) > +#define xroot_err(xr, fmt, args...) \ > + dev_err(XROOT_DEV(xr), "%s: " fmt, __func__, ##args) > +#define xroot_warn(xr, fmt, args...) \ > + dev_warn(XROOT_DEV(xr), "%s: " fmt, __func__, ##args) > +#define xroot_info(xr, fmt, args...) \ > + dev_info(XROOT_DEV(xr), "%s: " fmt, __func__, ##args) > +#define xroot_dbg(xr, fmt, args...) \ > + dev_dbg(XROOT_DEV(xr), "%s: " fmt, __func__, ##args) > + > +#define XRT_VSEC_ID 0x20 Is this the best place to define some pci magic ? It looks like the xroot is combination of the root of the device tree and the pci setup for the board. Can the pci-ness be split and the root mostly handling how the subtrees are organized ? > + > +#define XROOT_GRP_FIRST (-1) > +#define XROOT_GRP_LAST (-2) > + > +static int xroot_root_cb(struct device *, void *, u32, void *); > + > +struct xroot_evt { > + struct list_head list; > + struct xrt_event evt; > + struct completion comp; > + bool async; > +}; > + > +struct xroot_events { > + struct mutex evt_lock; /* event lock */ > + struct list_head evt_list; > + struct work_struct evt_work; > +}; > + > +struct xroot_grps { > + struct xrt_subdev_pool pool; > + struct work_struct bringup_work; > + atomic_t bringup_pending; > + atomic_t bringup_failed; combine with bitfield > + struct completion bringup_comp; > +}; > + > +struct xroot { > + struct pci_dev *pdev; > + struct xroot_events events; > + struct xroot_grps grps; > + struct xroot_pf_cb pf_cb; expand pf_cb, maybe 'physical_function_callback' ? > +}; > + > +struct xroot_grp_match_arg { > + enum xrt_subdev_id id; > + int instance; > +}; > + > +static bool xroot_grp_match(enum xrt_subdev_id id, > + struct platform_device *pdev, void *arg) > +{ > + struct xroot_grp_match_arg *a = (struct xroot_grp_match_arg *)arg; > + return id == a->id && pdev->id == a->instance; scanning the code i expected to see ... && pdev->instance == a->instance pdev->id == a->instance looks like a bug, a change to pdev->id element name to pdev->instance or in needed of a comment. > +} > + > +static int xroot_get_group(struct xroot *xr, int instance, > + struct platform_device **grpp) > +{ > + int rc = 0; > + struct xrt_subdev_pool *grps = &xr->grps.pool; > + struct device *dev = DEV(xr->pdev); > + struct xroot_grp_match_arg arg = { XRT_SUBDEV_GRP, instance }; > + > + if (instance == XROOT_GRP_LAST) { > + rc = xrt_subdev_pool_get(grps, XRT_SUBDEV_MATCH_NEXT, > + *grpp, dev, grpp); > + } else if (instance == XROOT_GRP_FIRST) { > + rc = xrt_subdev_pool_get(grps, XRT_SUBDEV_MATCH_PREV, > + *grpp, dev, grpp); For consistency, maybe the suffix of ...MATCH_NEXT/PREV should be changed to LAST/FIRST > + } else { > + rc = xrt_subdev_pool_get(grps, xroot_grp_match, > + &arg, dev, grpp); > + } > + > + if (rc && rc != -ENOENT) > + xroot_err(xr, "failed to hold group %d: %d", instance, rc); > + return rc; > +} > + > +static void xroot_put_group(struct xroot *xr, struct platform_device *grp) > +{ > + int inst = grp->id; > + int rc = xrt_subdev_pool_put(&xr->grps.pool, grp, DEV(xr->pdev)); > + > + if (rc) > + xroot_err(xr, "failed to release group %d: %d", inst, rc); > +} > + > +static int xroot_trigger_event(struct xroot *xr, > + struct xrt_event *e, bool async) > +{ > + struct xroot_evt *enew = vzalloc(sizeof(*enew)); > + > + if (!enew) > + return -ENOMEM; > + > + enew->evt = *e; > + enew->async = async; > + init_completion(&enew->comp); > + > + mutex_lock(&xr->events.evt_lock); > + list_add(&enew->list, &xr->events.evt_list); > + mutex_unlock(&xr->events.evt_lock); > + > + schedule_work(&xr->events.evt_work); > + > + if (async) > + return 0; > + > + wait_for_completion(&enew->comp); > + vfree(enew); > + return 0; > +} > + > +static void > +xroot_group_trigger_event(struct xroot *xr, int inst, enum xrt_events e) > +{ > + int ret; > + struct platform_device *pdev = NULL; > + struct xrt_event evt = { 0 }; > + > + WARN_ON(inst < 0); > + /* Only triggers subdev specific events. */ > + if (e != XRT_EVENT_POST_CREATION && e != XRT_EVENT_PRE_REMOVAL) { > + xroot_err(xr, "invalid event %d", e); > + return; > + } > + > + ret = xroot_get_group(xr, inst, &pdev); > + if (ret) > + return; > + > + /* Triggers event for children, first. */ > + (void)xleaf_ioctl(pdev, XRT_GROUP_TRIGGER_EVENT, (void *)(uintptr_t)e); These voids are not needed, but maybe error checking is. > + > + /* Triggers event for itself. */ > + evt.xe_evt = e; > + evt.xe_subdev.xevt_subdev_id = XRT_SUBDEV_GRP; > + evt.xe_subdev.xevt_subdev_instance = inst; > + (void)xroot_trigger_event(xr, &evt, false); > + > + (void)xroot_put_group(xr, pdev); > +} > + > +int xroot_create_group(void *root, char *dtb) > +{ > + struct xroot *xr = (struct xroot *)root; > + int ret; > + > + atomic_inc(&xr->grps.bringup_pending); could this state and the error be moved to xrt_sbudev_pool_add where locking happens so atomics are not needed ? > + ret = xrt_subdev_pool_add(&xr->grps.pool, XRT_SUBDEV_GRP, > + xroot_root_cb, xr, dtb); > + if (ret >= 0) { > + schedule_work(&xr->grps.bringup_work); > + } else { > + atomic_dec(&xr->grps.bringup_pending); > + atomic_inc(&xr->grps.bringup_failed); > + xroot_err(xr, "failed to create group: %d", ret); > + } > + return ret; > +} > +EXPORT_SYMBOL_GPL(xroot_create_group); > + > +static int xroot_destroy_single_group(struct xroot *xr, int instance) > +{ A better name would be 'xroot_destroy_group' > + struct platform_device *pdev = NULL; > + int ret; > + > + WARN_ON(instance < 0); > + ret = xroot_get_group(xr, instance, &pdev); > + if (ret) > + return ret; > + > + xroot_group_trigger_event(xr, instance, XRT_EVENT_PRE_REMOVAL); > + > + /* Now tear down all children in this group. */ > + ret = xleaf_ioctl(pdev, XRT_GROUP_FINI_CHILDREN, NULL); > + (void)xroot_put_group(xr, pdev); > + if (!ret) { > + ret = xrt_subdev_pool_del(&xr->grps.pool, XRT_SUBDEV_GRP, > + instance); > + } > + > + return ret; > +} > + > +static int xroot_destroy_group(struct xroot *xr, int instance) A better name would be 'xroot_destroy_groups' > +{ > + struct platform_device *target = NULL; > + struct platform_device *deps = NULL; > + int ret; > + > + WARN_ON(instance < 0); > + /* > + * Make sure target group exists and can't go away before > + * we remove it's dependents > + */ > + ret = xroot_get_group(xr, instance, &target); > + if (ret) > + return ret; > + > + /* > + * Remove all groups depend on target one. > + * Assuming subdevs in higher group ID can depend on ones in > + * lower ID groups, we remove them in the reservse order. > + */ > + while (xroot_get_group(xr, XROOT_GRP_LAST, &deps) != -ENOENT) { > + int inst = deps->id; > + > + xroot_put_group(xr, deps); > + if (instance == inst) > + break; breaking in the middle does not seem correct. please add a comment > + (void)xroot_destroy_single_group(xr, inst); > + deps = NULL; > + } > + > + /* Now we can remove the target group. */ > + xroot_put_group(xr, target); > + return xroot_destroy_single_group(xr, instance); > +} > + > +static int xroot_lookup_group(struct xroot *xr, > + struct xrt_root_ioctl_lookup_group *arg) > +{ > + int rc = -ENOENT; > + struct platform_device *grp = NULL; > + > + while (rc < 0 && xroot_get_group(xr, XROOT_GRP_LAST, &grp) != -ENOENT) { > + if (arg->xpilp_match_cb(XRT_SUBDEV_GRP, grp, > + arg->xpilp_match_arg)) { > + rc = grp->id; > + } > + xroot_put_group(xr, grp); > + } > + return rc; > +} > + > +static void xroot_event_work(struct work_struct *work) > +{ > + struct xroot_evt *tmp; > + struct xroot *xr = container_of(work, struct xroot, events.evt_work); > + > + mutex_lock(&xr->events.evt_lock); > + while (!list_empty(&xr->events.evt_list)) { > + tmp = list_first_entry(&xr->events.evt_list, > + struct xroot_evt, list); > + list_del(&tmp->list); > + mutex_unlock(&xr->events.evt_lock); why is unlocking necessary ? > + > + (void)xrt_subdev_pool_handle_event(&xr->grps.pool, &tmp->evt); > + > + if (tmp->async) > + vfree(tmp); > + else > + complete(&tmp->comp); > + > + mutex_lock(&xr->events.evt_lock); > + } > + mutex_unlock(&xr->events.evt_lock); > +} > + > +static void xroot_event_init(struct xroot *xr) > +{ > + INIT_LIST_HEAD(&xr->events.evt_list); > + mutex_init(&xr->events.evt_lock); > + INIT_WORK(&xr->events.evt_work, xroot_event_work); > +} > + > +static void xroot_event_fini(struct xroot *xr) > +{ > + flush_scheduled_work(); > + WARN_ON(!list_empty(&xr->events.evt_list)); > +} > + > +static int xroot_get_leaf(struct xroot *xr, struct xrt_root_ioctl_get_leaf *arg) > +{ > + int rc = -ENOENT; > + struct platform_device *grp = NULL; > + > + while (rc && xroot_get_group(xr, XROOT_GRP_LAST, &grp) != -ENOENT) { while (rc) ? while we see an error on xleaf_ioctl, keep going ? Seems like would rather have !rc similar below in put_leaf > + rc = xleaf_ioctl(grp, XRT_GROUP_GET_LEAF, arg); > + xroot_put_group(xr, grp); > + } > + return rc; > +} > + > +static int xroot_put_leaf(struct xroot *xr, struct xrt_root_ioctl_put_leaf *arg) > +{ > + int rc = -ENOENT; > + struct platform_device *grp = NULL; > + > + while (rc && xroot_get_group(xr, XROOT_GRP_LAST, &grp) != -ENOENT) { > + rc = xleaf_ioctl(grp, XRT_GROUP_PUT_LEAF, arg); > + xroot_put_group(xr, grp); > + } > + return rc; > +} > + > +static int xroot_root_cb(struct device *dev, void *parg, u32 cmd, void *arg) > +{ > + struct xroot *xr = (struct xroot *)parg; > + int rc = 0; > + > + switch (cmd) { > + /* Leaf actions. */ > + case XRT_ROOT_GET_LEAF: { > + struct xrt_root_ioctl_get_leaf *getleaf = > + (struct xrt_root_ioctl_get_leaf *)arg; > + rc = xroot_get_leaf(xr, getleaf); > + break; > + } > + case XRT_ROOT_PUT_LEAF: { > + struct xrt_root_ioctl_put_leaf *putleaf = > + (struct xrt_root_ioctl_put_leaf *)arg; > + rc = xroot_put_leaf(xr, putleaf); > + break; > + } looking at these two cases without any changes to arg but a cast, i think these and the next pass the void * onto the function and have the function manage the cast. > + case XRT_ROOT_GET_LEAF_HOLDERS: { > + struct xrt_root_ioctl_get_holders *holders = > + (struct xrt_root_ioctl_get_holders *)arg; > + rc = xrt_subdev_pool_get_holders(&xr->grps.pool, > + holders->xpigh_pdev, > + holders->xpigh_holder_buf, > + holders->xpigh_holder_buf_len); > + break; > + } > + > + /* Group actions. */ > + case XRT_ROOT_CREATE_GROUP: > + rc = xroot_create_group(xr, (char *)arg); > + break; > + case XRT_ROOT_REMOVE_GROUP: > + rc = xroot_destroy_group(xr, (int)(uintptr_t)arg); > + break; > + case XRT_ROOT_LOOKUP_GROUP: { > + struct xrt_root_ioctl_lookup_group *getgrp = > + (struct xrt_root_ioctl_lookup_group *)arg; > + rc = xroot_lookup_group(xr, getgrp); > + break; > + } > + case XRT_ROOT_WAIT_GROUP_BRINGUP: > + rc = xroot_wait_for_bringup(xr) ? 0 : -EINVAL; > + break; > + > + /* Event actions. */ > + case XRT_ROOT_EVENT: > + case XRT_ROOT_EVENT_ASYNC: { > + bool async = (cmd == XRT_ROOT_EVENT_ASYNC); > + struct xrt_event *evt = (struct xrt_event *)arg; > + > + rc = xroot_trigger_event(xr, evt, async); > + break; > + } > + > + /* Device info. */ > + case XRT_ROOT_GET_RESOURCE: { > + struct xrt_root_ioctl_get_res *res = > + (struct xrt_root_ioctl_get_res *)arg; > + res->xpigr_res = xr->pdev->resource; > + break; > + } > + case XRT_ROOT_GET_ID: { > + struct xrt_root_ioctl_get_id *id = > + (struct xrt_root_ioctl_get_id *)arg; > + > + id->xpigi_vendor_id = xr->pdev->vendor; > + id->xpigi_device_id = xr->pdev->device; > + id->xpigi_sub_vendor_id = xr->pdev->subsystem_vendor; > + id->xpigi_sub_device_id = xr->pdev->subsystem_device; > + break; > + } > + > + /* MISC generic PCIE driver functions. */ misc functions may need a need some place else. Is there a way to extend the cmd with some additional layer of abstraction ? > + case XRT_ROOT_HOT_RESET: { > + xr->pf_cb.xpc_hot_reset(xr->pdev); > + break; > + } > + case XRT_ROOT_HWMON: { > + struct xrt_root_ioctl_hwmon *hwmon = > + (struct xrt_root_ioctl_hwmon *)arg; > + > + if (hwmon->xpih_register) { > + hwmon->xpih_hwmon_dev = > + hwmon_device_register_with_info(DEV(xr->pdev), > + hwmon->xpih_name, > + hwmon->xpih_drvdata, > + NULL, > + hwmon->xpih_groups); > + } else { > + (void)hwmon_device_unregister(hwmon->xpih_hwmon_dev); > + } > + break; > + } > + > + default: > + xroot_err(xr, "unknown IOCTL cmd %d", cmd); > + rc = -EINVAL; > + break; > + } > + > + return rc; > +} > + > +static void xroot_bringup_group_work(struct work_struct *work) > +{ > + struct platform_device *pdev = NULL; > + struct xroot *xr = container_of(work, struct xroot, grps.bringup_work); > + > + while (xroot_get_group(xr, XROOT_GRP_FIRST, &pdev) != -ENOENT) { > + int r, i; > + > + i = pdev->id; > + r = xleaf_ioctl(pdev, XRT_GROUP_INIT_CHILDREN, NULL); > + (void)xroot_put_group(xr, pdev); > + if (r == -EEXIST) > + continue; /* Already brough up, nothing to do. */ > + if (r) > + atomic_inc(&xr->grps.bringup_failed); > + > + xroot_group_trigger_event(xr, i, XRT_EVENT_POST_CREATION); > + > + if (atomic_dec_and_test(&xr->grps.bringup_pending)) > + complete(&xr->grps.bringup_comp); > + } > +} > + > +static void xroot_grps_init(struct xroot *xr) Consistency in terms is needed. In the last few lines i see group, grp, grps, my vote is for group(s) > +{ > + xrt_subdev_pool_init(DEV(xr->pdev), &xr->grps.pool); > + INIT_WORK(&xr->grps.bringup_work, xroot_bringup_group_work); > + atomic_set(&xr->grps.bringup_pending, 0); > + atomic_set(&xr->grps.bringup_failed, 0); > + init_completion(&xr->grps.bringup_comp); > +} > + > +static void xroot_grps_fini(struct xroot *xr) > +{ > + flush_scheduled_work(); > + xrt_subdev_pool_fini(&xr->grps.pool); > +} > + > +int xroot_add_vsec_node(void *root, char *dtb) > +{ This is the pci part i think needs to move to its own file. > + struct xroot *xr = (struct xroot *)root; > + struct device *dev = DEV(xr->pdev); > + struct xrt_md_endpoint ep = { 0 }; > + int cap = 0, ret = 0; > + u32 off_low, off_high, vsec_bar, header; > + u64 vsec_off; > + > + while ((cap = pci_find_next_ext_capability(xr->pdev, cap, > + PCI_EXT_CAP_ID_VNDR))) { > + pci_read_config_dword(xr->pdev, cap + PCI_VNDR_HEADER, &header); > + if (PCI_VNDR_HEADER_ID(header) == XRT_VSEC_ID) > + break; > + } > + if (!cap) { > + xroot_info(xr, "No Vendor Specific Capability."); > + return -ENOENT; > + } > + > + if (pci_read_config_dword(xr->pdev, cap + 8, &off_low) || > + pci_read_config_dword(xr->pdev, cap + 12, &off_high)) { > + xroot_err(xr, "pci_read vendor specific failed."); > + return -EINVAL; > + } > + > + ep.ep_name = XRT_MD_NODE_VSEC; > + ret = xrt_md_add_endpoint(dev, dtb, &ep); > + if (ret) { > + xroot_err(xr, "add vsec metadata failed, ret %d", ret); > + goto failed; > + } > + > + vsec_bar = cpu_to_be32(off_low & 0xf); > + ret = xrt_md_set_prop(dev, dtb, XRT_MD_NODE_VSEC, NULL, > + XRT_MD_PROP_BAR_IDX, &vsec_bar, sizeof(vsec_bar)); > + if (ret) { > + xroot_err(xr, "add vsec bar idx failed, ret %d", ret); > + goto failed; > + } > + > + vsec_off = cpu_to_be64(((u64)off_high << 32) | (off_low & ~0xfU)); > + ret = xrt_md_set_prop(dev, dtb, XRT_MD_NODE_VSEC, NULL, > + XRT_MD_PROP_OFFSET, &vsec_off, sizeof(vsec_off)); > + if (ret) { > + xroot_err(xr, "add vsec offset failed, ret %d", ret); > + goto failed; > + } > + > +failed: > + return ret; > +} > +EXPORT_SYMBOL_GPL(xroot_add_vsec_node); > + > +int xroot_add_simple_node(void *root, char *dtb, const char *endpoint) > +{ > + struct xroot *xr = (struct xroot *)root; > + struct device *dev = DEV(xr->pdev); > + struct xrt_md_endpoint ep = { 0 }; > + int ret = 0; > + > + ep.ep_name = endpoint; > + ret = xrt_md_add_endpoint(dev, dtb, &ep); > + if (ret) > + xroot_err(xr, "add %s failed, ret %d", endpoint, ret); > + > + return ret; > +} > +EXPORT_SYMBOL_GPL(xroot_add_simple_node); > + > +bool xroot_wait_for_bringup(void *root) > +{ > + struct xroot *xr = (struct xroot *)root; > + > + wait_for_completion(&xr->grps.bringup_comp); > + return atomic_xchg(&xr->grps.bringup_failed, 0) == 0; Is there going to a race in intialization ? > +} > +EXPORT_SYMBOL_GPL(xroot_wait_for_bringup); > + > +int xroot_probe(struct pci_dev *pdev, struct xroot_pf_cb *cb, void **root) > +{ > + struct device *dev = DEV(pdev); > + struct xroot *xr = NULL; > + > + dev_info(dev, "%s: probing...", __func__); > + > + xr = devm_kzalloc(dev, sizeof(*xr), GFP_KERNEL); > + if (!xr) > + return -ENOMEM; > + > + xr->pdev = pdev; > + xr->pf_cb = *cb; > + xroot_grps_init(xr); > + xroot_event_init(xr); > + > + *root = xr; > + return 0; > +} > +EXPORT_SYMBOL_GPL(xroot_probe); > + > +void xroot_remove(void *root) > +{ > + struct xroot *xr = (struct xroot *)root; > + struct platform_device *grp = NULL; > + > + xroot_info(xr, "leaving..."); > + > + if (xroot_get_group(xr, XROOT_GRP_FIRST, &grp) == 0) { > + int instance = grp->id; another instance = id, the variable and element names should be consistent. earlier (id, instance) is used to uniquely determine a node. if that is so then using the names should be kept seperate. > + > + xroot_put_group(xr, grp); > + (void)xroot_destroy_group(xr, instance); > + } > + > + xroot_event_fini(xr); > + xroot_grps_fini(xr); > +} > +EXPORT_SYMBOL_GPL(xroot_remove); > + > +void xroot_broadcast(void *root, enum xrt_events evt) > +{ > + struct xroot *xr = (struct xroot *)root; > + struct xrt_event e = { 0 }; > + > + /* Root pf driver only broadcasts below two events. */ > + if (evt != XRT_EVENT_POST_CREATION && evt != XRT_EVENT_PRE_REMOVAL) { > + xroot_info(xr, "invalid event %d", evt); > + return; > + } > + > + e.xe_evt = evt; > + e.xe_subdev.xevt_subdev_id = XRT_ROOT; > + e.xe_subdev.xevt_subdev_instance = 0; see.. id = instance = Tom > + (void)xroot_trigger_event(xr, &e, false); > +} > +EXPORT_SYMBOL_GPL(xroot_broadcast);
Hi Tom, On 02/21/2021 09:12 AM, Tom Rix wrote: > On 2/17/21 10:40 PM, Lizhi Hou wrote: >> Alveo FPGA firmware and partial reconfigure file are in xclbin format. > This code enumerates and extracts Will change this to Alveo FPGA firmware and partial reconfigure file are in xclbin format. This code enumerates and extracts sections from xclbin files. xclbin.h is cross platform and used across all platforms and OS. >> Add >> code to enumerate and extract sections from xclbin files. xclbin.h is cross >> platform and used across all platforms and OS >> >> Signed-off-by: Sonal Santan <sonal.santan@xilinx.com> >> Signed-off-by: Max Zhen <max.zhen@xilinx.com> >> Signed-off-by: Lizhi Hou <lizhih@xilinx.com> >> --- >> drivers/fpga/xrt/include/xclbin-helper.h | 52 +++ >> drivers/fpga/xrt/lib/xclbin.c | 394 ++++++++++++++++++++++ >> include/uapi/linux/xrt/xclbin.h | 408 +++++++++++++++++++++++ >> 3 files changed, 854 insertions(+) >> create mode 100644 drivers/fpga/xrt/include/xclbin-helper.h >> create mode 100644 drivers/fpga/xrt/lib/xclbin.c >> create mode 100644 include/uapi/linux/xrt/xclbin.h >> >> diff --git a/drivers/fpga/xrt/include/xclbin-helper.h b/drivers/fpga/xrt/include/xclbin-helper.h >> new file mode 100644 >> index 000000000000..68218efc9d0b >> --- /dev/null >> +++ b/drivers/fpga/xrt/include/xclbin-helper.h >> @@ -0,0 +1,52 @@ >> +/* SPDX-License-Identifier: GPL-2.0 */ >> +/* >> + * Header file for Xilinx Runtime (XRT) driver >> + * >> + * Copyright (C) 2020-2021 Xilinx, Inc. >> + * >> + * Authors: >> + * David Zhang <davidzha@xilinx.com> >> + * Sonal Santan <sonal.santan@xilinx.com> >> + */ >> + >> +#ifndef _XRT_XCLBIN_H >> +#define _XRT_XCLBIN_H > The header guard should match the filename. will fix this. > >> + >> +#include <linux/types.h> >> +#include <linux/device.h> >> +#include <linux/xrt/xclbin.h> >> + >> +#define ICAP_XCLBIN_V2 "xclbin2" >> +#define DMA_HWICAP_BITFILE_BUFFER_SIZE 1024 >> +#define MAX_XCLBIN_SIZE (1024 * 1024 * 1024) /* Assuming xclbin <= 1G, always */ > #defines should have a prefix, maybe XRT_ or XCLBIN_ Will add prefix XCLBIN_ >> + >> +enum axlf_section_kind; >> +struct axlf; >> + >> +/** >> + * Bitstream header information as defined by Xilinx tools. >> + * Please note that this struct definition is not owned by the driver. >> + */ >> +struct hw_icap_bit_header { > File headers usually have fixed length fields like uint32_t > > Is this a structure the real header is converted into ? This is not real header. This structure saves the information extracted from bitstream header. > >> + unsigned int header_length; /* Length of header in 32 bit words */ >> + unsigned int bitstream_length; /* Length of bitstream to read in bytes*/ >> + unsigned char *design_name; /* Design name get from bitstream */ >> + unsigned char *part_name; /* Part name read from bitstream */ >> + unsigned char *date; /* Date read from bitstream header */ >> + unsigned char *time; /* Bitstream creation time */ >> + unsigned int magic_length; /* Length of the magic numbers */ >> + unsigned char *version; /* Version string */ >> +}; >> + >> +const char *xrt_xclbin_kind_to_string(enum axlf_section_kind kind); > Only add decl's that are using in multiple files. > > This is only defined in xclbin.c, why does it need to be in the header ? Will remove this. > >> +int xrt_xclbin_get_section(const struct axlf *xclbin, >> + enum axlf_section_kind kind, void **data, >> + uint64_t *len); >> +int xrt_xclbin_get_metadata(struct device *dev, const struct axlf *xclbin, char **dtb); >> +int xrt_xclbin_parse_bitstream_header(const unsigned char *data, >> + unsigned int size, >> + struct hw_icap_bit_header *header); >> +void xrt_xclbin_free_header(struct hw_icap_bit_header *header); >> +const char *xrt_clock_type2epname(enum CLOCK_TYPE type); > CLOCK_TYPE needs a prefix, something like XCLBIN_CLOCK_TYPE Will change to XCLBIN_CLOCK_TYPE. >> + >> +#endif /* _XRT_XCLBIN_H */ >> diff --git a/drivers/fpga/xrt/lib/xclbin.c b/drivers/fpga/xrt/lib/xclbin.c >> new file mode 100644 >> index 000000000000..47dc6ca25c1b >> --- /dev/null >> +++ b/drivers/fpga/xrt/lib/xclbin.c >> @@ -0,0 +1,394 @@ >> +// SPDX-License-Identifier: GPL-2.0 >> +/* >> + * Xilinx Alveo FPGA Driver XCLBIN parser >> + * >> + * Copyright (C) 2020-2021 Xilinx, Inc. >> + * >> + * Authors: David Zhang <davidzha@xilinx.com> >> + */ >> + >> +#include <asm/errno.h> >> +#include <linux/vmalloc.h> >> +#include <linux/device.h> >> +#include "xclbin-helper.h" >> +#include "metadata.h" >> + > What is XHI ? Maybe expand this, at the lease should comment Will use BITSTREAM_ instead. >> +/* Used for parsing bitstream header */ >> +#define XHI_EVEN_MAGIC_BYTE 0x0f >> +#define XHI_ODD_MAGIC_BYTE 0xf0 >> + >> +/* Extra mode for IDLE */ >> +#define XHI_OP_IDLE -1 >> +#define XHI_BIT_HEADER_FAILURE -1 >> + >> +/* The imaginary module length register */ >> +#define XHI_MLR 15 >> + >> +static inline unsigned char xhi_data_and_inc(const unsigned char *d, int *i, int sz) > could move to the *.h I will restructure caller function xrt_xclbin_parse_bitstream_header() and remove xhi_data_and_inc(). >> +{_ >> + unsigned char data; >> + >> + if (*i >= sz) >> + return -1; > The return value of this funtion is not always checked, at the least add a dev_err here >> + >> + data = d[*i]; >> + (*i)++; >> + >> + return data; >> +} >> + >> +static const struct axlf_section_header * >> +xrt_xclbin_get_section_hdr(const struct axlf *xclbin, >> + enum axlf_section_kind kind) >> +{ >> + int i = 0; >> + >> + for (i = 0; i < xclbin->m_header.m_numSections; i++) { >> + if (xclbin->m_sections[i].m_sectionKind == kind) >> + return &xclbin->m_sections[i]; >> + } >> + >> + return NULL; >> +} >> + >> +static int >> +xrt_xclbin_check_section_hdr(const struct axlf_section_header *header, >> + u64 xclbin_len) >> +{ >> + int ret; >> + >> + ret = (header->m_sectionOffset + header->m_sectionSize) > xclbin_len ? -EINVAL : 0; > Tristate is harder to read, consider replacing with if() > > int ret = 0 > > if () > > ret = Will change to if statement. > >> + >> + return ret; >> +} >> + >> +static int xrt_xclbin_section_info(const struct axlf *xclbin, >> + enum axlf_section_kind kind, >> + u64 *offset, u64 *size) >> +{ >> + const struct axlf_section_header *mem_header = NULL; >> + u64 xclbin_len; >> + int err = 0; >> + >> + mem_header = xrt_xclbin_get_section_hdr(xclbin, kind); >> + if (!mem_header) >> + return -EINVAL; >> + >> + xclbin_len = xclbin->m_header.m_length; >> + if (xclbin_len > MAX_XCLBIN_SIZE) >> + return -EINVAL; > This check can be added to the function call.. > > or the sanity checking added to the earier call to *get_section_hdr > > There a number of small functions that can be combined. Will change this and combine the small functions. > >> + >> + err = xrt_xclbin_check_section_hdr(mem_header, xclbin_len); >> + if (err) >> + return err; >> + >> + *offset = mem_header->m_sectionOffset; >> + *size = mem_header->m_sectionSize; >> + >> + return 0; >> +} >> + >> +/* caller should free the allocated memory for **data */ > must free > > This comment also needs to be with the *.h decl Will change this and add the same comment to .h > >> +int xrt_xclbin_get_section(const struct axlf *buf, >> + enum axlf_section_kind kind, >> + void **data, u64 *len) >> +{ >> + const struct axlf *xclbin = (const struct axlf *)buf; >> + void *section = NULL; >> + int err = 0; >> + u64 offset = 0; >> + u64 size = 0; >> + >> + err = xrt_xclbin_section_info(xclbin, kind, &offset, &size); >> + if (err) >> + return err; >> + >> + section = vmalloc(size); >> + if (!section) >> + return -ENOMEM; >> + >> + memcpy(section, ((const char *)xclbin) + offset, size); >> + >> + *data = section; > a general comment > > for exported function checking the validity of the inputs in more important. > > here you assume **data is valid, really you should check. Will add check for exported functions. > >> + if (len) >> + *len = size; > len setting being optional, needs to be in the *.h comment Will add comment. >> + >> + return 0; >> +} >> +EXPORT_SYMBOL_GPL(xrt_xclbin_get_section); >> + > Instead of allocating new memory and making copies of bits of *data > > why not have the points reference data ? Agree. I will change to use this points reference data. > > The size operations look like translating big endian data to little endian. > > This will break on a big endian host. It does not translate to little endian. It converts to host endian. We can not use existing function because of the alignment. > >> +/* parse bitstream header */ >> +int xrt_xclbin_parse_bitstream_header(const unsigned char *data, >> + unsigned int size, >> + struct hw_icap_bit_header *header) >> +{ >> + unsigned int index; >> + unsigned int len; >> + unsigned int tmp; >> + unsigned int i; >> + >> + memset(header, 0, sizeof(*header)); >> + /* Start Index at start of bitstream */ >> + index = 0; >> + >> + /* Initialize HeaderLength. If header returned early inidicates >> + * failure. > This side effect should be documented in the *.h comment. > > Also the multi line comment is a bit weird, not sure if it is ok Will remove this. The function will return -EINVAL for failure cases. > >> + */ >> + header->header_length = XHI_BIT_HEADER_FAILURE; >> + >> + /* Get "Magic" length */ >> + header->magic_length = xhi_data_and_inc(data, &index, size); >> + header->magic_length = (header->magic_length << 8) | xhi_data_and_inc(data, &index, size); >> + >> + /* Read in "magic" */ >> + for (i = 0; i < header->magic_length - 1; i++) { >> + tmp = xhi_data_and_inc(data, &index, size); >> + if (i % 2 == 0 && tmp != XHI_EVEN_MAGIC_BYTE) >> + return -1; /* INVALID_FILE_HEADER_ERROR */ >> + >> + if (i % 2 == 1 && tmp != XHI_ODD_MAGIC_BYTE) >> + return -1; /* INVALID_FILE_HEADER_ERROR */ >> + } >> + >> + /* Read null end of magic data. */ >> + tmp = xhi_data_and_inc(data, &index, size); >> + >> + /* Read 0x01 (short) */ >> + tmp = xhi_data_and_inc(data, &index, size); >> + tmp = (tmp << 8) | xhi_data_and_inc(data, &index, size); >> + >> + /* Check the "0x01" half word */ >> + if (tmp != 0x01) >> + return -1; /* INVALID_FILE_HEADER_ERROR */ >> + >> + /* Read 'a' */ >> + tmp = xhi_data_and_inc(data, &index, size); >> + if (tmp != 'a') >> + return -1; /* INVALID_FILE_HEADER_ERROR */ >> + >> + /* Get Design Name length */ >> + len = xhi_data_and_inc(data, &index, size); >> + len = (len << 8) | xhi_data_and_inc(data, &index, size); >> + >> + /* allocate space for design name and final null character. */ >> + header->design_name = vmalloc(len); >> + if (!header->design_name) >> + return -ENOMEM; >> + >> + /* Read in Design Name */ >> + for (i = 0; i < len; i++) >> + header->design_name[i] = xhi_data_and_inc(data, &index, size); >> + >> + if (header->design_name[len - 1] != '\0') >> + return -1; >> + >> + header->version = strstr(header->design_name, "Version=") + strlen("Version="); >> + >> + /* Read 'b' */ >> + tmp = xhi_data_and_inc(data, &index, size); >> + if (tmp != 'b') >> + return -1; /* INVALID_FILE_HEADER_ERROR */ >> + >> + /* Get Part Name length */ >> + len = xhi_data_and_inc(data, &index, size); >> + len = (len << 8) | xhi_data_and_inc(data, &index, size); >> + >> + /* allocate space for part name and final null character. */ >> + header->part_name = vmalloc(len); >> + if (!header->part_name) >> + return -ENOMEM; >> + >> + /* Read in part name */ >> + for (i = 0; i < len; i++) >> + header->part_name[i] = xhi_data_and_inc(data, &index, size); >> + >> + if (header->part_name[len - 1] != '\0') >> + return -1; >> + >> + /* Read 'c' */ >> + tmp = xhi_data_and_inc(data, &index, size); >> + if (tmp != 'c') >> + return -1; /* INVALID_FILE_HEADER_ERROR */ >> + >> + /* Get date length */ >> + len = xhi_data_and_inc(data, &index, size); >> + len = (len << 8) | xhi_data_and_inc(data, &index, size); >> + >> + /* allocate space for date and final null character. */ >> + header->date = vmalloc(len); >> + if (!header->date) >> + return -ENOMEM; >> + >> + /* Read in date name */ >> + for (i = 0; i < len; i++) >> + header->date[i] = xhi_data_and_inc(data, &index, size); >> + >> + if (header->date[len - 1] != '\0') >> + return -1; > generally -EINVAL is more meaningful than -1 Will fix this. >> + >> + /* Read 'd' */ >> + tmp = xhi_data_and_inc(data, &index, size); >> + if (tmp != 'd') >> + return -1; /* INVALID_FILE_HEADER_ERROR */ >> + >> + /* Get time length */ >> + len = xhi_data_and_inc(data, &index, size); >> + len = (len << 8) | xhi_data_and_inc(data, &index, size); >> + >> + /* allocate space for time and final null character. */ >> + header->time = vmalloc(len); >> + if (!header->time) >> + return -ENOMEM; >> + >> + /* Read in time name */ >> + for (i = 0; i < len; i++) >> + header->time[i] = xhi_data_and_inc(data, &index, size); >> + >> + if (header->time[len - 1] != '\0') >> + return -1; >> + >> + /* Read 'e' */ >> + tmp = xhi_data_and_inc(data, &index, size); >> + if (tmp != 'e') >> + return -1; /* INVALID_FILE_HEADER_ERROR */ >> + >> + /* Get byte length of bitstream */ >> + header->bitstream_length = xhi_data_and_inc(data, &index, size); >> + header->bitstream_length = (header->bitstream_length << 8) | >> + xhi_data_and_inc(data, &index, size); >> + header->bitstream_length = (header->bitstream_length << 8) | >> + xhi_data_and_inc(data, &index, size); >> + header->bitstream_length = (header->bitstream_length << 8) | >> + xhi_data_and_inc(data, &index, size); > generally a problem > > This is confusing, collect the bytes in a temp[] and construct the header->bitstream_length in on statement. > > This is a case where xhi_data_and_inc return is not checked and if it failed could blow up later. Will restructure this function and check the possible overflow. > >> + >> + header->header_length = index; > index is not a good variable name if it going to be stored as a length. > > consider changing it to something like current_length. Will change it to offset. > >> + >> + return 0; >> +} >> +EXPORT_SYMBOL_GPL(xrt_xclbin_parse_bitstream_header); >> + >> +void xrt_xclbin_free_header(struct hw_icap_bit_header *header) >> +{ >> + vfree(header->design_name); >> + vfree(header->part_name); >> + vfree(header->date); >> + vfree(header->time); > missing header->version Will remove xrt_xclbin_free_header(). All the pointers will point to reference data instead of allocation. >> +} >> +EXPORT_SYMBOL_GPL(xrt_xclbin_free_header); >> + >> +struct xrt_clock_desc { >> + char *clock_ep_name; >> + u32 clock_xclbin_type; >> + char *clkfreq_ep_name; >> +} clock_desc[] = { >> + { >> + .clock_ep_name = XRT_MD_NODE_CLK_KERNEL1, >> + .clock_xclbin_type = CT_DATA, >> + .clkfreq_ep_name = XRT_MD_NODE_CLKFREQ_K1, >> + }, >> + { >> + .clock_ep_name = XRT_MD_NODE_CLK_KERNEL2, >> + .clock_xclbin_type = CT_KERNEL, >> + .clkfreq_ep_name = XRT_MD_NODE_CLKFREQ_K2, >> + }, >> + { >> + .clock_ep_name = XRT_MD_NODE_CLK_KERNEL3, >> + .clock_xclbin_type = CT_SYSTEM, >> + .clkfreq_ep_name = XRT_MD_NODE_CLKFREQ_HBM, >> + }, >> +}; >> + >> +const char *xrt_clock_type2epname(enum CLOCK_TYPE type) >> +{ >> + int i; >> + >> + for (i = 0; i < ARRAY_SIZE(clock_desc); i++) { >> + if (clock_desc[i].clock_xclbin_type == type) >> + return clock_desc[i].clock_ep_name; >> + } >> + return NULL; >> +} >> +EXPORT_SYMBOL_GPL(xrt_clock_type2epname); > What is clock stuff doing in xclbin ? > > I think clock needs its own file xclbin file contains a section which describes the clock settings to running this xclbin on hardware. The _clock_ functions convert clock section to XRT driver metadata which is in device tree format. > >> + >> +static const char *clock_type2clkfreq_name(u32 type) >> +{ >> + int i; >> + >> + for (i = 0; i < ARRAY_SIZE(clock_desc); i++) { >> + if (clock_desc[i].clock_xclbin_type == type) >> + return clock_desc[i].clkfreq_ep_name; >> + } >> + return NULL; >> +} >> + >> +static int xrt_xclbin_add_clock_metadata(struct device *dev, >> + const struct axlf *xclbin, >> + char *dtb) >> +{ >> + int i; >> + u16 freq; >> + struct clock_freq_topology *clock_topo; >> + int rc = xrt_xclbin_get_section(xclbin, CLOCK_FREQ_TOPOLOGY, >> + (void **)&clock_topo, NULL); >> + >> + if (rc) >> + return 0; > failing is ok ? If clock section does not exist in xclbin, that means the xclbin uses default clock. And this is a valid case. I will add comment /* if clock section does not exist, add nothing and return success */ >> + >> + for (i = 0; i < clock_topo->m_count; i++) { >> + u8 type = clock_topo->m_clock_freq[i].m_type; >> + const char *ep_name = xrt_clock_type2epname(type); >> + const char *counter_name = clock_type2clkfreq_name(type); >> + >> + if (!ep_name || !counter_name) >> + continue; >> + >> + freq = cpu_to_be16(clock_topo->m_clock_freq[i].m_freq_Mhz); >> + rc = xrt_md_set_prop(dev, dtb, ep_name, NULL, XRT_MD_PROP_CLK_FREQ, >> + &freq, sizeof(freq)); >> + if (rc) >> + break; >> + >> + rc = xrt_md_set_prop(dev, dtb, ep_name, NULL, XRT_MD_PROP_CLK_CNT, >> + counter_name, strlen(counter_name) + 1); >> + if (rc) >> + break; > Failing in a loop, why isn't there some cleanup of the *set_prop() calls ? The entire blob will be freed outside if this function return failure. >> + } >> + >> + vfree(clock_topo); >> + >> + return rc; >> +} >> + >> +int xrt_xclbin_get_metadata(struct device *dev, const struct axlf *xclbin, char **dtb) >> +{ >> + char *md = NULL, *newmd = NULL; >> + u64 len; > *dtb = NULL; Will fix this. >> + int rc = xrt_xclbin_get_section(xclbin, PARTITION_METADATA, >> + (void **)&md, &len); >> + >> + if (rc) >> + goto done; >> + >> + /* Sanity check the dtb section. */ >> + if (xrt_md_size(dev, md) > len) { >> + rc = -EINVAL; >> + goto done; >> + } >> + >> + newmd = xrt_md_dup(dev, md); >> + if (!newmd) { >> + rc = -EFAULT; >> + goto done; >> + } >> + /* Convert various needed xclbin sections into dtb. */ >> + rc = xrt_xclbin_add_clock_metadata(dev, xclbin, newmd); > newmd is only valid here, but the above error handling jump here. change this to > > if (!rc) > > *dtb = newmd > > else > > vfree(newmd) > > done: > > vfree(md) > > return rc; Will change it. >> + >> +done: >> + if (rc == 0) >> + *dtb = newmd; >> + else >> + vfree(newmd); >> + vfree(md); >> + return rc; >> +} >> +EXPORT_SYMBOL_GPL(xrt_xclbin_get_metadata); >> diff --git a/include/uapi/linux/xrt/xclbin.h b/include/uapi/linux/xrt/xclbin.h >> new file mode 100644 >> index 000000000000..53f140123ef1 >> --- /dev/null >> +++ b/include/uapi/linux/xrt/xclbin.h >> @@ -0,0 +1,408 @@ >> +/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */ >> +/* >> + * Xilinx FPGA compiled binary container format >> + * >> + * Copyright (C) 2015-2021, Xilinx Inc >> + */ >> + >> +#ifndef _XCLBIN_H_ >> +#define _XCLBIN_H_ >> + >> +#ifdef _WIN32 > WIN32 ? > > Only 1 other header has this ifdef > >> + #include <cstdint> >> + #include <algorithm> > c++ is being assumed for windows >> + #include "windows/uuid.h" > thank you for not including windows.h ;) >> +#else >> + #if defined(__KERNEL__) >> + #include <linux/types.h> >> + #include <linux/uuid.h> >> + #include <linux/version.h> >> + #elif defined(__cplusplus) >> + #include <cstdlib> >> + #include <cstdint> >> + #include <algorithm> >> + #include <uuid/uuid.h> >> + #else >> + #include <stdlib.h> >> + #include <stdint.h> >> + #include <uuid/uuid.h> >> + #endif >> +#endif >> + > Review these includes, some could be convenience includes. removed uuid.h and version.h. > > ex/ linux/version.h with no obvious use of version macros. > > struct axlf_header { > + uint64_t m_length; /* Total size of the xclbin file */ > .. snip .. > + union { > + char m_next_axlf[16]; /* Name of next xclbin file */ > + /* in the daisy chain */ > + uuid_t uuid; /* uuid of this xclbin*/ > + }; > > As mentioned in an earlier patch, if uuid_t is larger than 16 bytes, axlf_header breaks. > while it is convenient to have this type here, it would be better this access was handled in another way. > Maybe a host specific function. Agree. will change to "unsigned char uuid[16]". > > I also do not see a pragma pack, usually this is set of 1 so the compiler does not shuffle elements, increase size etc. This data structure is shared with other tools. And the structure is well defined with reasonable alignment. It is compatible with all compilers we have tested. So pragma pack is not necessary. > >> +#ifdef __cplusplus >> +extern "C" { >> +#endif >> + >> +/** >> + * DOC: Container format for Xilinx FPGA images >> + * The container stores bitstreams, metadata and firmware images. >> + * xclbin/xsabin is ELF-like binary container format. It is structured > is an ELF-like file format. It is a structured Will fix this. >> + * series of sections. There is a file header followed by several section >> + * headers which is followed by sections. A section header points to an >> + * actual section. There is an optional signature at the end. The >> + * following figure illustrates a typical xclbin: >> + * >> + * +---------------------+ >> + * | | >> + * | HEADER | >> + * +---------------------+ >> + * | SECTION HEADER | >> + * | | >> + * +---------------------+ >> + * | ... | >> + * | | >> + * +---------------------+ >> + * | SECTION HEADER | >> + * | | >> + * +---------------------+ >> + * | SECTION | >> + * | | >> + * +---------------------+ >> + * | ... | >> + * | | >> + * +---------------------+ >> + * | SECTION | >> + * | | >> + * +---------------------+ >> + * | SIGNATURE | >> + * | (OPTIONAL) | >> + * +---------------------+ > This ascii art is a mixture of tabs and spaces, for someone with tab = 2 spaces, this will look messed up. > > convert the tabs to spaces Will fix this. > >> + */ >> + >> +enum XCLBIN_MODE { >> + XCLBIN_FLAT, > generally > > all enums used in a file format should be initialized. > > This likely should be > > XCLBIN_FLAT = 0, Will fix this. > >> + XCLBIN_PR, >> + XCLBIN_TANDEM_STAGE2, >> + XCLBIN_TANDEM_STAGE2_WITH_PR, >> + XCLBIN_HW_EMU, >> + XCLBIN_SW_EMU, >> + XCLBIN_MODE_MAX >> +}; >> + >> +enum axlf_section_kind { >> + BITSTREAM = 0, >> + CLEARING_BITSTREAM, >> + EMBEDDED_METADATA, >> + FIRMWARE, >> + DEBUG_DATA, >> + SCHED_FIRMWARE, >> + MEM_TOPOLOGY, >> + CONNECTIVITY, >> + IP_LAYOUT, >> + DEBUG_IP_LAYOUT, >> + DESIGN_CHECK_POINT, >> + CLOCK_FREQ_TOPOLOGY, >> + MCS, >> + BMC, >> + BUILD_METADATA, >> + KEYVALUE_METADATA, >> + USER_METADATA, >> + DNA_CERTIFICATE, >> + PDI, >> + BITSTREAM_PARTIAL_PDI, >> + PARTITION_METADATA, >> + EMULATION_DATA, >> + SYSTEM_METADATA, >> + SOFT_KERNEL, >> + ASK_FLASH, >> + AIE_METADATA, >> + ASK_GROUP_TOPOLOGY, >> + ASK_GROUP_CONNECTIVITY >> +}; >> + >> +enum MEM_TYPE { >> + MEM_DDR3, >> + MEM_DDR4, >> + MEM_DRAM, >> + MEM_STREAMING, >> + MEM_PREALLOCATED_GLOB, >> + MEM_ARE, >> + MEM_HBM, >> + MEM_BRAM, >> + MEM_URAM, >> + MEM_STREAMING_CONNECTION >> +}; >> + >> +enum IP_TYPE { >> + IP_MB = 0, >> + IP_KERNEL, >> + IP_DNASC, >> + IP_DDR4_CONTROLLER, >> + IP_MEM_DDR4, >> + IP_MEM_HBM >> +}; >> + >> +struct axlf_section_header { >> + uint32_t m_sectionKind; /* Section type */ >> + char m_sectionName[16]; /* Examples: "stage2", "clear1", */ >> + /* "clear2", "ocl1", "ocl2, */ >> + /* "ublaze", "sched" */ >> + uint64_t m_sectionOffset; /* File offset of section data */ >> + uint64_t m_sectionSize; /* Size of section data */ >> +}; >> + >> +struct axlf_header { >> + uint64_t m_length; /* Total size of the xclbin file */ >> + uint64_t m_timeStamp; /* Number of seconds since epoch */ >> + /* when xclbin was created */ >> + uint64_t m_featureRomTimeStamp; /* TimeSinceEpoch of the featureRom */ >> + uint16_t m_versionPatch; /* Patch Version */ >> + uint8_t m_versionMajor; /* Major Version - Version: 2.1.0*/ > i did not see the version checked earlier, which one is expected ? Will check Major. >> + uint8_t m_versionMinor; /* Minor Version */ >> + uint32_t m_mode; /* XCLBIN_MODE */ >> + union { >> + struct { >> + uint64_t m_platformId; /* 64 bit platform ID: */ >> + /* vendor-device-subvendor-subdev */ >> + uint64_t m_featureId; /* 64 bit feature id */ >> + } rom; >> + unsigned char rom_uuid[16]; /* feature ROM UUID for which */ >> + /* this xclbin was generated */ >> + }; >> + unsigned char m_platformVBNV[64]; /* e.g. */ > what is VBNV? VBNV stands for Vendor, BoardID, Name, Version. It is a string like <Vendor>:<BoardID>:<Name>:<Version> or <Vendor>_<BoardID>_<Name>_<Version> >> + /* xilinx:xil-accel-rd-ku115:4ddr-xpr:3.4: null terminated */ >> + union { >> + char m_next_axlf[16]; /* Name of next xclbin file */ >> + /* in the daisy chain */ >> + uuid_t uuid; /* uuid of this xclbin*/ >> + }; >> + char m_debug_bin[16]; /* Name of binary with debug */ >> + /* information */ >> + uint32_t m_numSections; /* Number of section headers */ >> +}; >> + >> +struct axlf { >> + char m_magic[8]; /* Should be "xclbin2\0" */ >> + int32_t m_signature_length; /* Length of the signature. */ >> + /* -1 indicates no signature */ >> + unsigned char reserved[28]; /* Note: Initialized to 0xFFs */ >> + >> + unsigned char m_keyBlock[256]; /* Signature for validation */ >> + /* of binary */ >> + uint64_t m_uniqueId; /* axlf's uniqueId, use it to */ >> + /* skip redownload etc */ >> + struct axlf_header m_header; /* Inline header */ >> + struct axlf_section_header m_sections[1]; /* One or more section */ >> + /* headers follow */ >> +}; >> + >> +/* bitstream information */ >> +struct xlnx_bitstream { >> + uint8_t m_freq[8]; >> + char bits[1]; >> +}; >> + >> +/**** MEMORY TOPOLOGY SECTION ****/ >> +struct mem_data { >> + uint8_t m_type; /* enum corresponding to mem_type. */ >> + uint8_t m_used; /* if 0 this bank is not present */ >> + union { >> + uint64_t m_size; /* if mem_type DDR, then size in KB; */ >> + uint64_t route_id; /* if streaming then "route_id" */ >> + }; >> + union { >> + uint64_t m_base_address;/* if DDR then the base address; */ >> + uint64_t flow_id; /* if streaming then "flow id" */ >> + }; >> + unsigned char m_tag[16]; /* DDR: BANK0,1,2,3, has to be null */ >> + /* terminated; if streaming then stream0, 1 etc */ >> +}; >> + >> +struct mem_topology { >> + int32_t m_count; /* Number of mem_data */ >> + struct mem_data m_mem_data[1]; /* Should be sorted on mem_type */ >> +}; >> + >> +/**** CONNECTIVITY SECTION ****/ >> +/* Connectivity of each argument of Kernel. It will be in terms of argument > This section does not make sense. > > Likely you mean some algorithm kernel, rather than the linux kernel. The kernel here means hardware IP kernel. I will change the term to CU (Compute Unit). > >> + * index associated. For associating kernel instances with arguments and >> + * banks, start at the connectivity section. Using the m_ip_layout_index >> + * access the ip_data.m_name. Now we can associate this kernel instance >> + * with its original kernel name and get the connectivity as well. This >> + * enables us to form related groups of kernel instances. >> + */ >> + >> +struct connection { >> + int32_t arg_index; /* From 0 to n, may not be contiguous as scalars */ >> + /* skipped */ >> + int32_t m_ip_layout_index; /* index into the ip_layout section. */ >> + /* ip_layout.m_ip_data[index].m_type == IP_KERNEL */ >> + int32_t mem_data_index; /* index of the m_mem_data . Flag error is */ >> + /* m_used false. */ >> +}; >> + >> +struct connectivity { >> + int32_t m_count; >> + struct connection m_connection[1]; >> +}; >> + >> +/**** IP_LAYOUT SECTION ****/ >> + >> +/* IP Kernel */ >> +#define IP_INT_ENABLE_MASK 0x0001 >> +#define IP_INTERRUPT_ID_MASK 0x00FE >> +#define IP_INTERRUPT_ID_SHIFT 0x1 >> + >> +enum IP_CONTROL { >> + AP_CTRL_HS = 0, >> + AP_CTRL_CHAIN = 1, >> + AP_CTRL_NONE = 2, >> + AP_CTRL_ME = 3, >> + ACCEL_ADAPTER = 4 > assigning beyond the first is not necessary unless there are dups or gaps Will fix this. >> +}; >> + >> +#define IP_CONTROL_MASK 0xFF00 >> +#define IP_CONTROL_SHIFT 0x8 >> + >> +/* IPs on AXI lite - their types, names, and base addresses.*/ >> +struct ip_data { >> + uint32_t m_type; /* map to IP_TYPE enum */ >> + union { >> + uint32_t properties; /* Default: 32-bits to indicate ip */ >> + /* specific property. */ >> + /* m_type: IP_KERNEL >> + * m_int_enable : Bit - 0x0000_0001; >> + * m_interrupt_id : Bits - 0x0000_00FE; >> + * m_ip_control : Bits = 0x0000_FF00; >> + */ >> + struct { /* m_type: IP_MEM_* */ >> + uint16_t m_index; >> + uint8_t m_pc_index; >> + uint8_t unused; >> + } indices; >> + }; >> + uint64_t m_base_address; >> + uint8_t m_name[64]; /* eg Kernel name corresponding to KERNEL */ >> + /* instance, can embed CU name in future. */ >> +}; >> + >> +struct ip_layout { >> + int32_t m_count; >> + struct ip_data m_ip_data[1]; /* All the ip_data needs to be sorted */ >> + /* by m_base_address. */ > general > > doing the bla[1] for c++ ? This file is cross platform and having an array with size 0 chokes certain compilers. Thanks, Lizhi > > Tom > >> +}; >> + >> +/*** Debug IP section layout ****/ >> +enum DEBUG_IP_TYPE { >> + UNDEFINED = 0, >> + LAPC, >> + ILA, >> + AXI_MM_MONITOR, >> + AXI_TRACE_FUNNEL, >> + AXI_MONITOR_FIFO_LITE, >> + AXI_MONITOR_FIFO_FULL, >> + ACCEL_MONITOR, >> + AXI_STREAM_MONITOR, >> + AXI_STREAM_PROTOCOL_CHECKER, >> + TRACE_S2MM, >> + AXI_DMA, >> + TRACE_S2MM_FULL >> +}; >> + >> +struct debug_ip_data { >> + uint8_t m_type; /* type of enum DEBUG_IP_TYPE */ >> + uint8_t m_index_lowbyte; >> + uint8_t m_properties; >> + uint8_t m_major; >> + uint8_t m_minor; >> + uint8_t m_index_highbyte; >> + uint8_t m_reserved[2]; >> + uint64_t m_base_address; >> + char m_name[128]; >> +}; >> + >> +struct debug_ip_layout { >> + uint16_t m_count; >> + struct debug_ip_data m_debug_ip_data[1]; >> +}; >> + >> +/* Supported clock frequency types */ >> +enum CLOCK_TYPE { >> + CT_UNUSED = 0, /* Initialized value */ >> + CT_DATA = 1, /* Data clock */ >> + CT_KERNEL = 2, /* Kernel clock */ >> + CT_SYSTEM = 3 /* System Clock */ >> +}; >> + >> +/* Clock Frequency Entry */ >> +struct clock_freq { >> + uint16_t m_freq_Mhz; /* Frequency in MHz */ >> + uint8_t m_type; /* Clock type (enum CLOCK_TYPE) */ >> + uint8_t m_unused[5]; /* Not used - padding */ >> + char m_name[128]; /* Clock Name */ >> +}; >> + >> +/* Clock frequency section */ >> +struct clock_freq_topology { >> + int16_t m_count; /* Number of entries */ >> + struct clock_freq m_clock_freq[1]; /* Clock array */ >> +}; >> + >> +/* Supported MCS file types */ >> +enum MCS_TYPE { >> + MCS_UNKNOWN = 0, /* Initialized value */ >> + MCS_PRIMARY = 1, /* The primary mcs file data */ >> + MCS_SECONDARY = 2, /* The secondary mcs file data */ >> +}; >> + >> +/* One chunk of MCS data */ >> +struct mcs_chunk { >> + uint8_t m_type; /* MCS data type */ >> + uint8_t m_unused[7]; /* padding */ >> + uint64_t m_offset; /* data offset from the start of */ >> + /* the section */ >> + uint64_t m_size; /* data size */ >> +}; >> + >> +/* MCS data section */ >> +struct mcs { >> + int8_t m_count; /* Number of chunks */ >> + int8_t m_unused[7]; /* padding */ >> + struct mcs_chunk m_chunk[1]; /* MCS chunks followed by data */ >> +}; >> + >> +/* bmc data section */ >> +struct bmc { >> + uint64_t m_offset; /* data offset from the start of */ >> + /* the section */ >> + uint64_t m_size; /* data size (bytes) */ >> + char m_image_name[64]; /* Name of the image */ >> + /* (e.g., MSP432P401R) */ >> + char m_device_name[64]; /* Device ID (e.g., VCU1525) */ >> + char m_version[64]; >> + char m_md5value[33]; /* MD5 Expected Value */ >> + /* (e.g., 56027182079c0bd621761b7dab5a27ca)*/ >> + char m_padding[7]; /* Padding */ >> +}; >> + >> +/* soft kernel data section, used by classic driver */ >> +struct soft_kernel { >> + /** Prefix Syntax: >> + * mpo - member, pointer, offset >> + * This variable represents a zero terminated string >> + * that is offseted from the beginning of the section. >> + * The pointer to access the string is initialized as follows: >> + * char * pCharString = (address_of_section) + (mpo value) >> + */ >> + uint32_t mpo_name; /* Name of the soft kernel */ >> + uint32_t m_image_offset; /* Image offset */ >> + uint32_t m_image_size; /* Image size */ >> + uint32_t mpo_version; /* Version */ >> + uint32_t mpo_md5_value; /* MD5 checksum */ >> + uint32_t mpo_symbol_name; /* Symbol name */ >> + uint32_t m_num_instances; /* Number of instances */ >> + uint8_t padding[36]; /* Reserved for future use */ >> + uint8_t reservedExt[16]; /* Reserved for future extended data */ >> +}; >> + >> +enum CHECKSUM_TYPE { >> + CST_UNKNOWN = 0, >> + CST_SDBM = 1, >> + CST_LAST >> +}; >> + >> +#ifdef __cplusplus >> +} >> +#endif >> + >> +#endif
Hi Tom, On 2/22/21 10:50 AM, Tom Rix wrote: > CAUTION: This message has originated from an External Source. Please use proper judgment and caution when opening attachments, clicking links, or responding to this email. > > > On 2/17/21 10:40 PM, Lizhi Hou wrote: >> group driver that manages life cycle of a bunch of leaf driver instances >> and bridges them with root. >> >> Signed-off-by: Sonal Santan <sonal.santan@xilinx.com> >> Signed-off-by: Max Zhen <max.zhen@xilinx.com> >> Signed-off-by: Lizhi Hou <lizhih@xilinx.com> >> --- >> drivers/fpga/xrt/include/group.h | 27 ++++ >> drivers/fpga/xrt/lib/group.c | 265 +++++++++++++++++++++++++++++++ >> 2 files changed, 292 insertions(+) >> create mode 100644 drivers/fpga/xrt/include/group.h >> create mode 100644 drivers/fpga/xrt/lib/group.c >> >> diff --git a/drivers/fpga/xrt/include/group.h b/drivers/fpga/xrt/include/group.h >> new file mode 100644 >> index 000000000000..1874cdd5120d >> --- /dev/null >> +++ b/drivers/fpga/xrt/include/group.h >> @@ -0,0 +1,27 @@ >> +/* SPDX-License-Identifier: GPL-2.0 */ >> +/* >> + * Header file for Xilinx Runtime (XRT) driver > A bit too generic, please add a description or remove. Will remove. >> + * >> + * Copyright (C) 2020-2021 Xilinx, Inc. >> + * >> + * Authors: >> + * Cheng Zhen <maxz@xilinx.com> >> + */ >> + >> +#ifndef _XRT_GROUP_H_ >> +#define _XRT_GROUP_H_ >> + >> +#include "xleaf.h" > This is patch 6, consider comments on patch 4. Will move this header to other patch. >> + >> +/* >> + * Group driver IOCTL calls. > Are these really ioctl calls? > > Seems more like messages between nodes in a tree. > > Consider changing to better jagon, maybe ioctl -> msg You're right. They are not really ioctl calls. They are just calls b/w leaf nodes. I changed to leaf calls/commands. > >> + */ >> +enum xrt_group_ioctl_cmd { >> + XRT_GROUP_GET_LEAF = XRT_XLEAF_CUSTOM_BASE, /* See comments in xleaf.h */ > XRT_LEAF_CUSTOM_BASE is a #define, while these are enums. To be consistent, the XRT_LEAF_CUSTOM_BASE should be an enum in xleaf, you can initialize it to 64 there. Will fix. >> + XRT_GROUP_PUT_LEAF, >> + XRT_GROUP_INIT_CHILDREN, >> + XRT_GROUP_FINI_CHILDREN, >> + XRT_GROUP_TRIGGER_EVENT, >> +}; >> + >> +#endif /* _XRT_GROUP_H_ */ >> diff --git a/drivers/fpga/xrt/lib/group.c b/drivers/fpga/xrt/lib/group.c >> new file mode 100644 >> index 000000000000..6ba56eea479b >> --- /dev/null >> +++ b/drivers/fpga/xrt/lib/group.c >> @@ -0,0 +1,265 @@ >> +// SPDX-License-Identifier: GPL-2.0 >> +/* >> + * Xilinx Alveo FPGA Group Driver >> + * >> + * Copyright (C) 2020-2021 Xilinx, Inc. >> + * >> + * Authors: >> + * Cheng Zhen <maxz@xilinx.com> >> + */ >> + >> +#include <linux/mod_devicetable.h> >> +#include <linux/platform_device.h> >> +#include "xleaf.h" >> +#include "subdev_pool.h" >> +#include "group.h" >> +#include "metadata.h" >> +#include "main.h" >> + >> +#define XRT_GRP "xrt_group" >> + >> +struct xrt_group { >> + struct platform_device *pdev; >> + struct xrt_subdev_pool leaves; >> + bool leaves_created; >> + struct mutex lock; /* lock for group */ >> +}; >> + >> +static int xrt_grp_root_cb(struct device *dev, void *parg, >> + u32 cmd, void *arg) > could 'cmd' be some enum type ? Will fix. >> +{ >> + int rc; >> + struct platform_device *pdev = >> + container_of(dev, struct platform_device, dev); >> + struct xrt_group *xg = (struct xrt_group *)parg; >> + >> + switch (cmd) { >> + case XRT_ROOT_GET_LEAF_HOLDERS: { >> + struct xrt_root_ioctl_get_holders *holders = >> + (struct xrt_root_ioctl_get_holders *)arg; >> + rc = xrt_subdev_pool_get_holders(&xg->leaves, >> + holders->xpigh_pdev, >> + holders->xpigh_holder_buf, >> + holders->xpigh_holder_buf_len); >> + break; >> + } >> + default: >> + /* Forward parent call to root. */ >> + rc = xrt_subdev_root_request(pdev, cmd, arg); >> + break; >> + } >> + >> + return rc; >> +} >> + >> +static int xrt_grp_create_leaves(struct xrt_group *xg) >> +{ >> + struct xrt_subdev_platdata *pdata = DEV_PDATA(xg->pdev); >> + enum xrt_subdev_id did; >> + struct xrt_subdev_endpoints *eps = NULL; >> + int ep_count = 0, i, ret = 0, failed = 0; >> + unsigned long mlen; >> + char *dtb, *grp_dtb = NULL; >> + const char *ep_name; >> + >> + mutex_lock(&xg->lock); >> + >> + if (xg->leaves_created) { >> + mutex_unlock(&xg->lock); > This happens should be programming error, so print out some error message The root driver does not remember which group has created leaves or not. It'll just blindly make the call. The group driver itself should remember and tell the root that it's done already or not. So, this is not considered as an error. >> + return -EEXIST; >> + } >> + >> + xrt_info(xg->pdev, "bringing up leaves..."); >> + >> + /* Create all leaves based on dtb. */ >> + if (!pdata) >> + goto bail; > move to above the lock and fail with something like -EINVAL Will fix. >> + >> + mlen = xrt_md_size(DEV(xg->pdev), pdata->xsp_dtb); >> + if (mlen == XRT_MD_INVALID_LENGTH) { >> + xrt_err(xg->pdev, "invalid dtb, len %ld", mlen); >> + goto bail; >> + } >> + >> + grp_dtb = vmalloc(mlen); >> + if (!grp_dtb) >> + goto bail; > failed is only set in the loop. This is an unreported -ENOMEM Will fix. >> + >> + memcpy(grp_dtb, pdata->xsp_dtb, mlen); >> + for (did = 0; did < XRT_SUBDEV_NUM;) { > why isn't the did incremented ? This is not a bug, but I will fix it by rewriting this function so that it'll be easier to follow (hopefully :-)). >> + eps = eps ? eps + 1 : xrt_drv_get_endpoints(did); > this assumes the enpoints are in an array and accessed serially. > > this is fragile. > > convert to using just the xrt_drv_get_endpoints() call It does not seem to be fragile? The endpoint data structure is private data structure so it has to be an array as defined. It's usage is just like an ID table as we have in other PCIE drivers. > >> + if (!eps || !eps->xse_names) { >> + did++; >> + eps = NULL; >> + continue; >> + } >> + ret = xrt_md_create(DEV(xg->pdev), &dtb); >> + if (ret) { >> + xrt_err(xg->pdev, "create md failed, drv %s", >> + xrt_drv_name(did)); >> + failed++; > failed but no cleanup of earier successes The leaves already created will still be there until the group is destroyed. This is not considered as fatal error. >> + continue; >> + } >> + for (i = 0; eps->xse_names[i].ep_name || > this assumes that xse_names[] always has a guard. > > why not use xse_min_ep ? xse_min_ep is to tell caller the minimum number of end points needs to be collected before instantiate the leaf driver. it does not indicate exactly how many end points this leaf can handle (it might be able to handle more). So, the guard is necessary to tell caller total number of end points it can handle. > >> + eps->xse_names[i].regmap_name; i++) { >> + ep_name = (char *)eps->xse_names[i].ep_name; >> + if (!ep_name) { >> + xrt_md_get_compatible_endpoint(DEV(xg->pdev), >> + grp_dtb, >> + eps->xse_names[i].regmap_name, >> + &ep_name); >> + } >> + if (!ep_name) >> + continue; >> + >> + ret = xrt_md_copy_endpoint(DEV(xg->pdev), >> + dtb, grp_dtb, ep_name, >> + (char *)eps->xse_names[i].regmap_name, >> + NULL); >> + if (ret) >> + continue; >> + xrt_md_del_endpoint(DEV(xg->pdev), grp_dtb, ep_name, >> + (char *)eps->xse_names[i].regmap_name); >> + ep_count++; >> + } >> + if (ep_count >= eps->xse_min_ep) { > This only happens if all additions are successful. This happens if the minimum number of end points has been collected. Anyway, the function is going to be rewritten. >> + ret = xrt_subdev_pool_add(&xg->leaves, did, >> + xrt_grp_root_cb, xg, dtb); >> + eps = NULL; >> + if (ret < 0) { >> + failed++; >> + xrt_err(xg->pdev, "failed to create %s: %d", >> + xrt_drv_name(did), ret); >> + } >> + } else if (ep_count > 0) { >> + xrt_md_copy_all_endpoints(DEV(xg->pdev), grp_dtb, dtb); >> + } >> + vfree(dtb); >> + ep_count = 0; >> + } >> + >> + xg->leaves_created = true; > This is true even if some failed ? Yes, this is OK. Some functionality may be missing if some leaves can be instantiated, but the group will be in leaves created state now. >> + >> +bail: >> + vfree(grp_dtb); >> + mutex_unlock(&xg->lock); >> + >> + return failed == 0 ? 0 : -ECHILD; >> +} >> + >> +static void xrt_grp_remove_leaves(struct xrt_group *xg) >> +{ >> + mutex_lock(&xg->lock); >> + >> + if (!xg->leaves_created) { >> + mutex_unlock(&xg->lock); >> + return; >> + } >> + >> + xrt_info(xg->pdev, "tearing down leaves..."); >> + xrt_subdev_pool_fini(&xg->leaves); > partial failure above and the subdev_pool is not created ? It is still created, just not fully populated. >> + xg->leaves_created = false; >> + >> + mutex_unlock(&xg->lock); >> +} >> + >> +static int xrt_grp_probe(struct platform_device *pdev) >> +{ >> + struct xrt_group *xg; >> + >> + xrt_info(pdev, "probing..."); >> + >> + xg = devm_kzalloc(&pdev->dev, sizeof(*xg), GFP_KERNEL); >> + if (!xg) >> + return -ENOMEM; >> + >> + xg->pdev = pdev; >> + mutex_init(&xg->lock); >> + xrt_subdev_pool_init(DEV(pdev), &xg->leaves); >> + platform_set_drvdata(pdev, xg); >> + >> + return 0; >> +} >> + >> +static int xrt_grp_remove(struct platform_device *pdev) >> +{ >> + struct xrt_group *xg = platform_get_drvdata(pdev); >> + >> + xrt_info(pdev, "leaving..."); >> + xrt_grp_remove_leaves(xg); > lock ? xrt_grp_remove_leaves() takes lock internally. Thanks, Max > > Tom > >> + return 0; >> +} >> + >> +static int xrt_grp_ioctl(struct platform_device *pdev, u32 cmd, void *arg) >> +{ >> + int rc = 0; >> + struct xrt_group *xg = platform_get_drvdata(pdev); >> + >> + switch (cmd) { >> + case XRT_XLEAF_EVENT: >> + /* Simply forward to every child. */ >> + xrt_subdev_pool_handle_event(&xg->leaves, >> + (struct xrt_event *)arg); >> + break; >> + case XRT_GROUP_GET_LEAF: { >> + struct xrt_root_ioctl_get_leaf *get_leaf = >> + (struct xrt_root_ioctl_get_leaf *)arg; >> + >> + rc = xrt_subdev_pool_get(&xg->leaves, get_leaf->xpigl_match_cb, >> + get_leaf->xpigl_match_arg, >> + DEV(get_leaf->xpigl_pdev), >> + &get_leaf->xpigl_leaf); >> + break; >> + } >> + case XRT_GROUP_PUT_LEAF: { >> + struct xrt_root_ioctl_put_leaf *put_leaf = >> + (struct xrt_root_ioctl_put_leaf *)arg; >> + >> + rc = xrt_subdev_pool_put(&xg->leaves, put_leaf->xpipl_leaf, >> + DEV(put_leaf->xpipl_pdev)); >> + break; >> + } >> + case XRT_GROUP_INIT_CHILDREN: >> + rc = xrt_grp_create_leaves(xg); >> + break; >> + case XRT_GROUP_FINI_CHILDREN: >> + xrt_grp_remove_leaves(xg); >> + break; >> + case XRT_GROUP_TRIGGER_EVENT: >> + xrt_subdev_pool_trigger_event(&xg->leaves, (enum xrt_events)(uintptr_t)arg); >> + break; >> + default: >> + xrt_err(pdev, "unknown IOCTL cmd %d", cmd); >> + rc = -EINVAL; >> + break; >> + } >> + return rc; >> +} >> + >> +static struct xrt_subdev_drvdata xrt_grp_data = { >> + .xsd_dev_ops = { >> + .xsd_ioctl = xrt_grp_ioctl, >> + }, >> +}; >> + >> +static const struct platform_device_id xrt_grp_id_table[] = { >> + { XRT_GRP, (kernel_ulong_t)&xrt_grp_data }, >> + { }, >> +}; >> + >> +static struct platform_driver xrt_group_driver = { >> + .driver = { >> + .name = XRT_GRP, >> + }, >> + .probe = xrt_grp_probe, >> + .remove = xrt_grp_remove, >> + .id_table = xrt_grp_id_table, >> +}; >> + >> +void group_leaf_init_fini(bool init) >> +{ >> + if (init) >> + xleaf_register_driver(XRT_SUBDEV_GRP, &xrt_group_driver, NULL); >> + else >> + xleaf_unregister_driver(XRT_SUBDEV_GRP); >> +}
On 2/17/21 10:40 PM, Lizhi Hou wrote: > fpga-mgr and region implementation for xclbin download which will be > called from main platform driver > > Signed-off-by: Sonal Santan <sonal.santan@xilinx.com> > Signed-off-by: Max Zhen <max.zhen@xilinx.com> > Signed-off-by: Lizhi Hou <lizhih@xilinx.com> > --- > drivers/fpga/xrt/mgmt/fmgr-drv.c | 187 +++++++++++ > drivers/fpga/xrt/mgmt/fmgr.h | 28 ++ > drivers/fpga/xrt/mgmt/main-region.c | 471 ++++++++++++++++++++++++++++ > 3 files changed, 686 insertions(+) > create mode 100644 drivers/fpga/xrt/mgmt/fmgr-drv.c > create mode 100644 drivers/fpga/xrt/mgmt/fmgr.h > create mode 100644 drivers/fpga/xrt/mgmt/main-region.c > > diff --git a/drivers/fpga/xrt/mgmt/fmgr-drv.c b/drivers/fpga/xrt/mgmt/fmgr-drv.c > new file mode 100644 > index 000000000000..a44d35ecdb60 > --- /dev/null > +++ b/drivers/fpga/xrt/mgmt/fmgr-drv.c > @@ -0,0 +1,187 @@ > +// SPDX-License-Identifier: GPL-2.0 > +/* > + * FPGA Manager Support for Xilinx Alveo Management Function Driver > + * > + * Copyright (C) 2020-2021 Xilinx, Inc. > + * > + * Authors: Sonal.Santan@xilinx.com > + */ > + > +#include <linux/cred.h> > +#include <linux/efi.h> > +#include <linux/fpga/fpga-mgr.h> > +#include <linux/platform_device.h> > +#include <linux/module.h> > +#include <linux/vmalloc.h> > + > +#include "xclbin-helper.h" > +#include "xleaf.h" > +#include "fmgr.h" > +#include "xleaf/axigate.h" > +#include "xleaf/icap.h" > +#include "main-impl.h" > + > +struct xfpga_class { > + const struct platform_device *pdev; > + char name[64]; > +}; > + > +/* > + * xclbin download plumbing -- find the download subsystem, ICAP and > + * pass the xclbin for heavy lifting > + */ > +static int xmgmt_download_bitstream(struct platform_device *pdev, > + const struct axlf *xclbin) > + > +{ > + struct hw_icap_bit_header bit_header = { 0 }; > + struct platform_device *icap_leaf = NULL; > + struct xrt_icap_ioctl_wr arg; > + char *bitstream = NULL; > + u64 bit_len; > + int ret; > + > + ret = xrt_xclbin_get_section(xclbin, BITSTREAM, (void **)&bitstream, &bit_len); > + if (ret || !bitstream) { !bitstream check is unneeded > + xrt_err(pdev, "bitstream not found"); > + return -ENOENT; > + } > + ret = xrt_xclbin_parse_bitstream_header(bitstream, > + DMA_HWICAP_BITFILE_BUFFER_SIZE, > + &bit_header); > + if (ret) { > + ret = -EINVAL; > + xrt_err(pdev, "invalid bitstream header"); > + goto done; > + } > + if (bit_header.header_length + bit_header.bitstream_length > bit_len) { > + ret = -EINVAL; > + xrt_err(pdev, "invalid bitstream length. header %d, bitstream %d, section len %lld", > + bit_header.header_length, bit_header.bitstream_length, bit_len); > + goto done; > + } > + > + icap_leaf = xleaf_get_leaf_by_id(pdev, XRT_SUBDEV_ICAP, PLATFORM_DEVID_NONE); > + if (!icap_leaf) { > + ret = -ENODEV; > + xrt_err(pdev, "icap does not exist"); > + xrt_xclbin_free_header(&bit_header); > + goto done; > + } > + arg.xiiw_bit_data = bitstream + bit_header.header_length; > + arg.xiiw_data_len = bit_header.bitstream_length; > + ret = xleaf_ioctl(icap_leaf, XRT_ICAP_WRITE, &arg); > + if (ret) > + xrt_err(pdev, "write bitstream failed, ret = %d", ret); > + > + xrt_xclbin_free_header(&bit_header); memory leak when something fails and goto done's > +done: previous general problem, use mutliple label in error handling blocks > + if (icap_leaf) > + xleaf_put_leaf(pdev, icap_leaf); > + vfree(bitstream); > + > + return ret; > +} > + > +/* > + * There is no HW prep work we do here since we need the full > + * xclbin for its sanity check. > + */ > +static int xmgmt_pr_write_init(struct fpga_manager *mgr, > + struct fpga_image_info *info, > + const char *buf, size_t count) > +{ > + const struct axlf *bin = (const struct axlf *)buf; > + struct xfpga_class *obj = mgr->priv; > + > + if (!(info->flags & FPGA_MGR_PARTIAL_RECONFIG)) { > + xrt_info(obj->pdev, "%s only supports partial reconfiguration\n", obj->name); > + return -EINVAL; > + } > + > + if (count < sizeof(struct axlf)) > + return -EINVAL; > + > + if (count > bin->m_header.m_length) > + return -EINVAL; > + > + xrt_info(obj->pdev, "Prepare download of xclbin %pUb of length %lld B", > + &bin->m_header.uuid, bin->m_header.m_length); > + > + return 0; > +} > + > +/* > + * The implementation requries full xclbin image before we can start > + * programming the hardware via ICAP subsystem. Full image is required The full image > + * for checking the validity of xclbin and walking the sections to > + * discover the bitstream. > + */ > +static int xmgmt_pr_write(struct fpga_manager *mgr, > + const char *buf, size_t count) > +{ > + const struct axlf *bin = (const struct axlf *)buf; > + struct xfpga_class *obj = mgr->priv; > + > + if (bin->m_header.m_length != count) > + return -EINVAL; > + > + return xmgmt_download_bitstream((void *)obj->pdev, bin); > +} > + > +static int xmgmt_pr_write_complete(struct fpga_manager *mgr, > + struct fpga_image_info *info) > +{ > + const struct axlf *bin = (const struct axlf *)info->buf; > + struct xfpga_class *obj = mgr->priv; > + > + xrt_info(obj->pdev, "Finished download of xclbin %pUb", > + &bin->m_header.uuid); > + return 0; > +} > + > +static enum fpga_mgr_states xmgmt_pr_state(struct fpga_manager *mgr) > +{ > + return FPGA_MGR_STATE_UNKNOWN; why just this state ? > +} > + > +static const struct fpga_manager_ops xmgmt_pr_ops = { > + .initial_header_size = sizeof(struct axlf), > + .write_init = xmgmt_pr_write_init, > + .write = xmgmt_pr_write, > + .write_complete = xmgmt_pr_write_complete, > + .state = xmgmt_pr_state, > +}; > + > +struct fpga_manager *xmgmt_fmgr_probe(struct platform_device *pdev) > +{ > + struct xfpga_class *obj = devm_kzalloc(DEV(pdev), sizeof(struct xfpga_class), > + GFP_KERNEL); > + struct fpga_manager *fmgr = NULL; > + int ret = 0; > + > + if (!obj) > + return ERR_PTR(-ENOMEM); > + > + snprintf(obj->name, sizeof(obj->name), "Xilinx Alveo FPGA Manager"); > + obj->pdev = pdev; > + fmgr = fpga_mgr_create(&pdev->dev, > + obj->name, > + &xmgmt_pr_ops, > + obj); > + if (!fmgr) > + return ERR_PTR(-ENOMEM); > + > + ret = fpga_mgr_register(fmgr); > + if (ret) { > + fpga_mgr_free(fmgr); > + return ERR_PTR(ret); > + } > + return fmgr; > +} > + > +int xmgmt_fmgr_remove(struct fpga_manager *fmgr) > +{ > + fpga_mgr_unregister(fmgr); > + return 0; > +} > diff --git a/drivers/fpga/xrt/mgmt/fmgr.h b/drivers/fpga/xrt/mgmt/fmgr.h > new file mode 100644 > index 000000000000..e1fc033e2542 > --- /dev/null > +++ b/drivers/fpga/xrt/mgmt/fmgr.h > @@ -0,0 +1,28 @@ > +/* SPDX-License-Identifier: GPL-2.0 */ > +/* > + * Header file for Xilinx Alveo Management Function Driver > + * > + * Copyright (C) 2020-2021 Xilinx, Inc. > + * > + * Authors: Sonal.Santan@xilinx.com > + */ > + > +#ifndef _XMGMT_FMGR_H_ > +#define _XMGMT_FMGR_H_ > + > +#include <linux/fpga/fpga-mgr.h> > +#include <linux/mutex.h> > + > +#include <linux/xrt/xclbin.h> > + > +enum xfpga_sec_level { > + XFPGA_SEC_NONE = 0, > + XFPGA_SEC_DEDICATE, > + XFPGA_SEC_SYSTEM, > + XFPGA_SEC_MAX = XFPGA_SEC_SYSTEM, > +}; This enum is not used, remove. > + > +struct fpga_manager *xmgmt_fmgr_probe(struct platform_device *pdev); > +int xmgmt_fmgr_remove(struct fpga_manager *fmgr); > + > +#endif > diff --git a/drivers/fpga/xrt/mgmt/main-region.c b/drivers/fpga/xrt/mgmt/main-region.c > new file mode 100644 > index 000000000000..9779693fe7ae > --- /dev/null > +++ b/drivers/fpga/xrt/mgmt/main-region.c > @@ -0,0 +1,471 @@ > +// SPDX-License-Identifier: GPL-2.0 > +/* > + * FPGA Region Support for Xilinx Alveo Management Function Driver > + * > + * Copyright (C) 2020-2021 Xilinx, Inc. > + * Bulk of the code borrowed from XRT mgmt driver file, fmgr.c > + * > + * Authors: Lizhi.Hou@xilinx.com > + */ > + > +#include <linux/uuid.h> > +#include <linux/fpga/fpga-bridge.h> > +#include <linux/fpga/fpga-region.h> > +#include "metadata.h" > +#include "xleaf.h" > +#include "xleaf/axigate.h" > +#include "xclbin-helper.h" > +#include "main-impl.h" > + > +struct xmgmt_bridge { > + struct platform_device *pdev; > + const char *axigate_name; axigate ? this element could just be 'name' it seems like 'axigate' means 'bridge', why not use 'bridge' ? > +}; > + > +struct xmgmt_region { > + struct platform_device *pdev; > + struct fpga_region *fregion; > + uuid_t intf_uuid; > + struct fpga_bridge *fbridge; > + int grp_inst; > + uuid_t dep_uuid; > + struct list_head list; clean up element names fregion -> region grp_inst -> group_instance ect. > +}; > + > +struct xmgmt_region_match_arg { > + struct platform_device *pdev; > + uuid_t *uuids; > + u32 uuid_num; > +}; > + > +static int xmgmt_br_enable_set(struct fpga_bridge *bridge, bool enable) > +{ > + struct xmgmt_bridge *br_data = (struct xmgmt_bridge *)bridge->priv; > + struct platform_device *axigate_leaf; > + int rc; > + > + axigate_leaf = xleaf_get_leaf_by_epname(br_data->pdev, br_data->axigate_name); > + if (!axigate_leaf) { > + xrt_err(br_data->pdev, "failed to get leaf %s", > + br_data->axigate_name); > + return -ENOENT; > + } > + > + if (enable) > + rc = xleaf_ioctl(axigate_leaf, XRT_AXIGATE_FREE, NULL); > + else > + rc = xleaf_ioctl(axigate_leaf, XRT_AXIGATE_FREEZE, NULL); > + > + if (rc) { > + xrt_err(br_data->pdev, "failed to %s gate %s, rc %d", > + (enable ? "free" : "freeze"), br_data->axigate_name, > + rc); > + } > + > + xleaf_put_leaf(br_data->pdev, axigate_leaf); > + > + return rc; > +} > + > +const struct fpga_bridge_ops xmgmt_bridge_ops = { > + .enable_set = xmgmt_br_enable_set > +}; > + > +static void xmgmt_destroy_bridge(struct fpga_bridge *br) > +{ > + struct xmgmt_bridge *br_data = br->priv; > + > + if (!br_data) > + return; > + > + xrt_info(br_data->pdev, "destroy fpga bridge %s", br_data->axigate_name); > + fpga_bridge_unregister(br); > + > + devm_kfree(DEV(br_data->pdev), br_data); > + > + fpga_bridge_free(br); > +} > + > +static struct fpga_bridge *xmgmt_create_bridge(struct platform_device *pdev, > + char *dtb) > +{ > + struct xmgmt_bridge *br_data; > + struct fpga_bridge *br = NULL; > + const char *gate; > + int rc; > + > + br_data = devm_kzalloc(DEV(pdev), sizeof(*br_data), GFP_KERNEL); > + if (!br_data) > + return NULL; > + br_data->pdev = pdev; > + > + br_data->axigate_name = XRT_MD_NODE_GATE_ULP; > + rc = xrt_md_find_endpoint(&pdev->dev, dtb, XRT_MD_NODE_GATE_ULP, > + NULL, &gate); > + if (rc) { > + br_data->axigate_name = XRT_MD_NODE_GATE_PLP; > + rc = xrt_md_find_endpoint(&pdev->dev, dtb, XRT_MD_NODE_GATE_PLP, > + NULL, &gate); > + } > + if (rc) { > + xrt_err(pdev, "failed to get axigate, rc %d", rc); > + goto failed; > + } > + > + br = fpga_bridge_create(DEV(pdev), br_data->axigate_name, > + &xmgmt_bridge_ops, br_data); > + if (!br) { > + xrt_err(pdev, "failed to create bridge"); > + goto failed; > + } > + > + rc = fpga_bridge_register(br); > + if (rc) { > + xrt_err(pdev, "failed to register bridge, rc %d", rc); > + goto failed; > + } > + > + xrt_info(pdev, "created fpga bridge %s", br_data->axigate_name); > + > + return br; > + > +failed: > + if (br) > + fpga_bridge_free(br); > + if (br_data) > + devm_kfree(DEV(pdev), br_data); > + > + return NULL; > +} > + > +static void xmgmt_destroy_region(struct fpga_region *re) re, to me means regular expression. can you use 'region' instead ? > +{ > + struct xmgmt_region *r_data = re->priv; > + > + xrt_info(r_data->pdev, "destroy fpga region %llx%llx", need a sperator here ? between %llx%llx > + re->compat_id->id_l, re->compat_id->id_h); > + > + fpga_region_unregister(re); > + > + if (r_data->grp_inst > 0) > + xleaf_destroy_group(r_data->pdev, r_data->grp_inst); > + > + if (r_data->fbridge) > + xmgmt_destroy_bridge(r_data->fbridge); > + > + if (r_data->fregion->info) { > + fpga_image_info_free(r_data->fregion->info); > + r_data->fregion->info = NULL; > + } > + > + fpga_region_free(re); > + > + devm_kfree(DEV(r_data->pdev), r_data); > +} > + > +static int xmgmt_region_match(struct device *dev, const void *data) > +{ > + const struct xmgmt_region_match_arg *arg = data; > + const struct fpga_region *match_re; > + int i; > + > + if (dev->parent != &arg->pdev->dev) > + return false; > + > + match_re = to_fpga_region(dev); > + /* > + * The device tree provides both parent and child uuids for an > + * xclbin in one array. Here we try both uuids to see if it matches > + * with target region's compat_id. Strictly speaking we should > + * only match xclbin's parent uuid with target region's compat_id > + * but given the uuids by design are unique comparing with both > + * does not hurt. > + */ > + for (i = 0; i < arg->uuid_num; i++) { > + if (!memcmp(match_re->compat_id, &arg->uuids[i], > + sizeof(*match_re->compat_id))) > + return true; > + } > + > + return false; > +} > + > +static int xmgmt_region_match_base(struct device *dev, const void *data) > +{ > + const struct xmgmt_region_match_arg *arg = data; > + const struct fpga_region *match_re; > + const struct xmgmt_region *r_data; > + > + if (dev->parent != &arg->pdev->dev) > + return false; > + > + match_re = to_fpga_region(dev); me getting confused thinking match_re is 'match regular expression' > + r_data = match_re->priv; > + if (uuid_is_null(&r_data->dep_uuid)) > + return true; > + > + return false; > +} > + > +static int xmgmt_region_match_by_depuuid(struct device *dev, const void *data) what is a dep uuid ? should add a '_' so function name is xmgmt_region_match_by_dep_uuid() this is quite long. > +{ > + const struct xmgmt_region_match_arg *arg = data; > + const struct fpga_region *match_re; > + const struct xmgmt_region *r_data; > + > + if (dev->parent != &arg->pdev->dev) > + return false; > + > + match_re = to_fpga_region(dev); > + r_data = match_re->priv; > + if (!memcmp(&r_data->dep_uuid, arg->uuids, sizeof(uuid_t))) arg->uuids is an array arg->uuid_num is its extent. should be a loop or check on uuid_num == 1 or both. > + return true; > + > + return false; > +} > + > +static void xmgmt_region_cleanup(struct fpga_region *re) > +{ > + struct xmgmt_region *r_data = re->priv, *temp; > + struct platform_device *pdev = r_data->pdev; > + struct fpga_region *match_re = NULL; > + struct device *start_dev = NULL; > + struct xmgmt_region_match_arg arg; > + LIST_HEAD(free_list); > + > + list_add_tail(&r_data->list, &free_list); > + arg.pdev = pdev; > + arg.uuid_num = 1; > + > + while (!r_data) { > + arg.uuids = (uuid_t *)r_data->fregion->compat_id; > + match_re = fpga_region_class_find(start_dev, &arg, > + xmgmt_region_match_by_depuuid); > + if (match_re) { > + r_data = match_re->priv; This setting of r_data and continuing is strange, add a comment. or if you intend to do a pair of operations, do the pair within the if block and remove the strangeness. > + list_add_tail(&r_data->list, &free_list); > + start_dev = &match_re->dev; > + put_device(&match_re->dev); > + continue; > + } > + > + r_data = list_is_last(&r_data->list, &free_list) ? NULL : > + list_next_entry(r_data, list); > + start_dev = NULL; > + } > + > + list_for_each_entry_safe_reverse(r_data, temp, &free_list, list) { > + if (list_is_first(&r_data->list, &free_list)) { > + if (r_data->grp_inst > 0) { > + xleaf_destroy_group(pdev, r_data->grp_inst); > + r_data->grp_inst = -1; > + } > + if (r_data->fregion->info) { > + fpga_image_info_free(r_data->fregion->info); > + r_data->fregion->info = NULL; > + } > + continue; add a comment, why is a continue needed here ? > + } > + xmgmt_destroy_region(r_data->fregion); > + } > +} > + > +void xmgmt_region_cleanup_all(struct platform_device *pdev) > +{ > + struct fpga_region *base_re; > + struct xmgmt_region_match_arg arg; > + > + arg.pdev = pdev; > + > + for (base_re = fpga_region_class_find(NULL, &arg, xmgmt_region_match_base); > + base_re; > + base_re = fpga_region_class_find(NULL, &arg, xmgmt_region_match_base)) { convert to a while while (base_region = ... ) { > + put_device(&base_re->dev); > + > + xmgmt_region_cleanup(base_re); > + xmgmt_destroy_region(base_re); > + } > +} > + > +/* > + * Program a given region with given xclbin image. Bring up the subdevs and the Program a region with a xclbin image. > + * group object to contain the subdevs. > + */ > +static int xmgmt_region_program(struct fpga_region *re, const void *xclbin, char *dtb) > +{ > + struct xmgmt_region *r_data = re->priv; > + struct platform_device *pdev = r_data->pdev; > + struct fpga_image_info *info; > + const struct axlf *xclbin_obj = xclbin; > + int rc; > + > + info = fpga_image_info_alloc(&pdev->dev); > + if (!info) > + return -ENOMEM; > + > + info->buf = xclbin; > + info->count = xclbin_obj->m_header.m_length; > + info->flags |= FPGA_MGR_PARTIAL_RECONFIG; > + re->info = info; > + rc = fpga_region_program_fpga(re); > + if (rc) { > + xrt_err(pdev, "programming xclbin failed, rc %d", rc); > + return rc; > + } free info ? > + > + /* free bridges to allow reprogram */ > + if (re->get_bridges) > + fpga_bridges_put(&re->bridge_list); > + > + /* > + * Next bringup the subdevs for this region which will be managed by > + * its own group object. > + */ > + r_data->grp_inst = xleaf_create_group(pdev, dtb); > + if (r_data->grp_inst < 0) { > + xrt_err(pdev, "failed to create group, rc %d", > + r_data->grp_inst); > + rc = r_data->grp_inst; > + return rc; > + } > + > + rc = xleaf_wait_for_group_bringup(pdev); > + if (rc) > + xrt_err(pdev, "group bringup failed, rc %d", rc); failed but no error handling, shouldn't the leaves and group be torn down ? > + return rc; > +} > + > +static int xmgmt_get_bridges(struct fpga_region *re) > +{ > + struct xmgmt_region *r_data = re->priv; > + struct device *dev = &r_data->pdev->dev; > + > + return fpga_bridge_get_to_list(dev, re->info, &re->bridge_list); > +} > + > +/* > + * Program/create FPGA regions based on input xclbin file. This is key function > + * stitching the flow together: 'This is ' .. sentence does not make sense, but is not needed drop it. > > + * 1. Identify a matching existing region for this xclbin > + * 2. Tear down any previous objects for the found region > + * 3. Program this region with input xclbin > + * 4. Iterate over this region's interface uuids to determine if it defines any > + * child region. Create fpga_region for the child region. > + */ > +int xmgmt_process_xclbin(struct platform_device *pdev, > + struct fpga_manager *fmgr, > + const struct axlf *xclbin, > + enum provider_kind kind) > +{ > + struct fpga_region *re, *compat_re = NULL; > + struct xmgmt_region_match_arg arg; should initialize to { 0 } > + struct xmgmt_region *r_data; > + char *dtb = NULL; > + int rc, i; > + > + rc = xrt_xclbin_get_metadata(DEV(pdev), xclbin, &dtb); > + if (rc) { > + xrt_err(pdev, "failed to get dtb: %d", rc); > + goto failed; > + } > + > + xrt_md_get_intf_uuids(DEV(pdev), dtb, &arg.uuid_num, NULL); should also check return and return that error code, it isn't always -EINVAL > + if (arg.uuid_num == 0) { > + xrt_err(pdev, "failed to get intf uuid"); > + rc = -EINVAL; > + goto failed; > + } > + arg.uuids = vzalloc(sizeof(uuid_t) * arg.uuid_num); > + if (!arg.uuids) { > + rc = -ENOMEM; > + goto failed; > + } > + arg.pdev = pdev; > + > + xrt_md_get_intf_uuids(DEV(pdev), dtb, &arg.uuid_num, arg.uuids); This can still fail, check this return and check the expected num of uuid's has not changed. > + > + /* if this is not base firmware, search for a compatible region */ > + if (kind != XMGMT_BLP) { > + compat_re = fpga_region_class_find(NULL, &arg, > + xmgmt_region_match); > + if (!compat_re) { > + xrt_err(pdev, "failed to get compatible region"); > + rc = -ENOENT; > + goto failed; > + } > + > + xmgmt_region_cleanup(compat_re); > + > + rc = xmgmt_region_program(compat_re, xclbin, dtb); > + if (rc) { > + xrt_err(pdev, "failed to program region"); > + goto failed; > + } > + } > + > + /* create all the new regions contained in this xclbin */ > + for (i = 0; i < arg.uuid_num; i++) { > + if (compat_re && !memcmp(compat_re->compat_id, &arg.uuids[i], > + sizeof(*compat_re->compat_id))) > + /* region for this interface already exists */ > + continue; > + re = fpga_region_create(DEV(pdev), fmgr, xmgmt_get_bridges); > + if (!re) { > + xrt_err(pdev, "failed to create fpga region"); > + rc = -EFAULT; > + goto failed; > + } > + r_data = devm_kzalloc(DEV(pdev), sizeof(*r_data), GFP_KERNEL); > + if (!r_data) { > + rc = -ENOMEM; > + fpga_region_free(re); > + goto failed; Failed in a loop but no cleanup of previous iterations. Tom > + } > + r_data->pdev = pdev; > + r_data->fregion = re; > + r_data->grp_inst = -1; > + memcpy(&r_data->intf_uuid, &arg.uuids[i], > + sizeof(r_data->intf_uuid)); > + if (compat_re) { > + memcpy(&r_data->dep_uuid, compat_re->compat_id, > + sizeof(r_data->intf_uuid)); > + } > + r_data->fbridge = xmgmt_create_bridge(pdev, dtb); > + if (!r_data->fbridge) { > + xrt_err(pdev, "failed to create fpga bridge"); > + rc = -EFAULT; > + devm_kfree(DEV(pdev), r_data); > + fpga_region_free(re); > + goto failed; > + } > + > + re->compat_id = (struct fpga_compat_id *)&r_data->intf_uuid; > + re->priv = r_data; > + > + rc = fpga_region_register(re); > + if (rc) { > + xrt_err(pdev, "failed to register fpga region"); > + xmgmt_destroy_bridge(r_data->fbridge); > + fpga_region_free(re); > + devm_kfree(DEV(pdev), r_data); > + goto failed; > + } > + > + xrt_info(pdev, "created fpga region %llx%llx", > + re->compat_id->id_l, re->compat_id->id_h); > + } > + > +failed: > + if (compat_re) > + put_device(&compat_re->dev); > + > + if (rc) { > + if (compat_re) > + xmgmt_region_cleanup(compat_re); > + } > + > + if (dtb) > + vfree(dtb); > + > + return rc; > +}
On 2/26/21 1:23 PM, Lizhi Hou wrote: > Hi Tom, > > snip >> >> I also do not see a pragma pack, usually this is set of 1 so the compiler does not shuffle elements, increase size etc. > This data structure is shared with other tools. And the structure is well defined with reasonable alignment. It is compatible with all compilers we have tested. So pragma pack is not necessary. You can not have possibly tested all the configurations since the kernel supports many arches and compilers. If the tested existing alignment is ok, pragma pack should be a noop on your tested configurations. And help cover the untested configurations. Tom
Hello Moritz, > -----Original Message----- > From: Moritz Fischer <mdf@kernel.org> > Sent: Sunday, February 21, 2021 10:40 AM > To: Tom Rix <trix@redhat.com> > Cc: Lizhi Hou <lizhih@xilinx.com>; linux-kernel@vger.kernel.org; > mdf@kernel.org; Lizhi Hou <lizhih@xilinx.com>; linux-fpga@vger.kernel.org; > Max Zhen <maxz@xilinx.com>; Sonal Santan <sonals@xilinx.com>; Michal > Simek <michals@xilinx.com>; Stefano Stabellini <stefanos@xilinx.com>; > devicetree@vger.kernel.org; robh@kernel.org; Max Zhen <maxz@xilinx.com> > Subject: Re: [PATCH V3 XRT Alveo 18/18] fpga: xrt: Kconfig and Makefile > updates for XRT drivers > > On Sun, Feb 21, 2021 at 06:57:31AM -0800, Tom Rix wrote: > > As I am looking through the files, I have this comment. > > > > fpga/ is currently a single directory, while files could be organized > > in subdirectories like > > > > dfl/pci.c > > > > instead have the possible subdir name as a prefix to the filename. > > > > dfl-pci.c > > > > For consistency, > > > > xrt/metadata/metadata.c > > > > should be > > > > xrt-metadata.c > > Agreed. Keep the prefix. > > > > Likewise the build infra needs to integrated within the existing files > > fpga/Kconfig,Makefile > > > > This is a bigish refactor, so let's get a second opinion. > > In what sense? You mean adding a subdirectory? Maybe something like this > > drivers/fpga > - dfl/ > - xilinx/ > - intel/ > - lattice/ > - xrt/ > ... > > would generally make sense. > > We didn't have enough drivers to prioritize that yet, but we can look into it. If longer term we would like to reorganize the drivers/fpga directory structure should we keep the current directory structure for XRT as in the patch series? > > > > Moritz ? > > > > On 2/17/21 10:40 PM, Lizhi Hou wrote: > > > Update fpga Kconfig/Makefile and add Kconfig/Makefile for new drivers. > > Expand the comment, there are several new configs that could use an > > explanation > > > > > > Signed-off-by: Sonal Santan <sonal.santan@xilinx.com> > > > Signed-off-by: Max Zhen <max.zhen@xilinx.com> > > > Signed-off-by: Lizhi Hou <lizhih@xilinx.com> > > > --- > > > MAINTAINERS | 11 +++++++++++ > > > drivers/Makefile | 1 + > > > drivers/fpga/Kconfig | 2 ++ > > > drivers/fpga/Makefile | 4 ++++ > > > drivers/fpga/xrt/Kconfig | 8 ++++++++ > > > drivers/fpga/xrt/lib/Kconfig | 16 ++++++++++++++++ > > > drivers/fpga/xrt/lib/Makefile | 30 ++++++++++++++++++++++++++++++ > > > drivers/fpga/xrt/metadata/Kconfig | 12 ++++++++++++ > > > drivers/fpga/xrt/metadata/Makefile | 16 ++++++++++++++++ > > > drivers/fpga/xrt/mgmt/Kconfig | 15 +++++++++++++++ > > > drivers/fpga/xrt/mgmt/Makefile | 19 +++++++++++++++++++ > > > 11 files changed, 134 insertions(+) create mode 100644 > > > drivers/fpga/xrt/Kconfig create mode 100644 > > > drivers/fpga/xrt/lib/Kconfig create mode 100644 > > > drivers/fpga/xrt/lib/Makefile create mode 100644 > > > drivers/fpga/xrt/metadata/Kconfig create mode 100644 > > > drivers/fpga/xrt/metadata/Makefile > > > create mode 100644 drivers/fpga/xrt/mgmt/Kconfig create mode > > > 100644 drivers/fpga/xrt/mgmt/Makefile > > > > > > diff --git a/MAINTAINERS b/MAINTAINERS index > > > d3e847f7f3dc..e6e147c2454c 100644 > > > --- a/MAINTAINERS > > > +++ b/MAINTAINERS > > > @@ -6973,6 +6973,17 @@ F: Documentation/fpga/ > > > F: drivers/fpga/ > > > F: include/linux/fpga/ > > > > > > +FPGA XRT DRIVERS > > > +M: Lizhi Hou <lizhi.hou@xilinx.com> > > > +R: Max Zhen <max.zhen@xilinx.com> > > > +R: Sonal Santan <sonal.santan@xilinx.com> > > > +L: linux-fpga@vger.kernel.org > > > +S: Maintained > > > +W: https://github.com/Xilinx/XRT > > > +F: Documentation/fpga/xrt.rst > > > +F: drivers/fpga/xrt/ > > > +F: include/uapi/linux/xrt/ > > > + > > > FPU EMULATOR > > > M: Bill Metzenthen <billm@melbpc.org.au> > > > S: Maintained > > > diff --git a/drivers/Makefile b/drivers/Makefile index > > > fd11b9ac4cc3..e03912af8e48 100644 > > > --- a/drivers/Makefile > > > +++ b/drivers/Makefile > > > @@ -178,6 +178,7 @@ obj-$(CONFIG_STM) += hwtracing/stm/ > > > obj-$(CONFIG_ANDROID) += android/ > > > obj-$(CONFIG_NVMEM) += nvmem/ > > > obj-$(CONFIG_FPGA) += fpga/ > > > +obj-y += fpga/xrt/metadata/ > > > > This is wrong. > > > > Move metadata building to fpga/ Makefile and pick an appropriate config, > not just 'obj-y' Will update. > > > > > obj-$(CONFIG_FSI) += fsi/ > > > obj-$(CONFIG_TEE) += tee/ > > > obj-$(CONFIG_MULTIPLEXER) += mux/ > > > diff --git a/drivers/fpga/Kconfig b/drivers/fpga/Kconfig index > > > 5645226ca3ce..aeca635b1f25 100644 > > > --- a/drivers/fpga/Kconfig > > > +++ b/drivers/fpga/Kconfig > > > @@ -216,4 +216,6 @@ config FPGA_MGR_ZYNQMP_FPGA > > > to configure the programmable logic(PL) through PS > > > on ZynqMP SoC. > > > > > > +source "drivers/fpga/xrt/Kconfig" > > > + > > > endif # FPGA > > > diff --git a/drivers/fpga/Makefile b/drivers/fpga/Makefile index > > > d8e21dfc6778..2b4453ff7c52 100644 > > > --- a/drivers/fpga/Makefile > > > +++ b/drivers/fpga/Makefile > > > @@ -46,3 +46,7 @@ dfl-afu-objs += dfl-afu-error.o > > > > > > # Drivers for FPGAs which implement DFL > > > obj-$(CONFIG_FPGA_DFL_PCI) += dfl-pci.o > > > + > > > +# XRT drivers for Alveo > > > +obj-$(CONFIG_FPGA_XRT_LIB) += xrt/lib/ > > > +obj-$(CONFIG_FPGA_XRT_XMGMT) += xrt/mgmt/ > > > > I don't see how mgmnt would work without lib. If that is so > > > > these configs could collapse to CONFIG_FPGA_XRT > > > > > diff --git a/drivers/fpga/xrt/Kconfig b/drivers/fpga/xrt/Kconfig new > > > file mode 100644 index 000000000000..0e2c59589ddd > > > --- /dev/null > > > +++ b/drivers/fpga/xrt/Kconfig > > > @@ -0,0 +1,8 @@ > > > +# SPDX-License-Identifier: GPL-2.0-only # # Xilinx Alveo FPGA > > > +device configuration # > > > + > > > +source "drivers/fpga/xrt/metadata/Kconfig" > > > +source "drivers/fpga/xrt/lib/Kconfig" > > > +source "drivers/fpga/xrt/mgmt/Kconfig" > > > diff --git a/drivers/fpga/xrt/lib/Kconfig > > > b/drivers/fpga/xrt/lib/Kconfig new file mode 100644 index > > > 000000000000..eed5cb73f5e2 > > > --- /dev/null > > > +++ b/drivers/fpga/xrt/lib/Kconfig > > > @@ -0,0 +1,16 @@ > > > +# SPDX-License-Identifier: GPL-2.0-only # # XRT Alveo FPGA device > > > +configuration # > > > + > > > +config FPGA_XRT_LIB > > > + tristate "XRT Alveo Driver Library" > > > + depends on HWMON && PCI && HAS_IOMEM > > > + select FPGA_XRT_METADATA > > > + help > > > + Select this option to enable Xilinx XRT Alveo driver library. This > > > + library is core infrastructure of XRT Alveo FPGA drivers which > > > + provides functions for working with device nodes, iteration and > > > + lookup of platform devices, common interfaces for platform devices, > > > + plumbing of function call and ioctls between platform devices and > > > + parent partitions. > > > diff --git a/drivers/fpga/xrt/lib/Makefile > > > b/drivers/fpga/xrt/lib/Makefile new file mode 100644 index > > > 000000000000..5641231b2a36 > > > --- /dev/null > > > +++ b/drivers/fpga/xrt/lib/Makefile > > > @@ -0,0 +1,30 @@ > > > +# SPDX-License-Identifier: GPL-2.0 > > > +# > > > +# Copyright (C) 2020-2021 Xilinx, Inc. All rights reserved. > > > +# > > > +# Authors: Sonal.Santan@xilinx.com > > > +# > > > + > > > +FULL_XRT_PATH=$(srctree)/$(src)/.. > > > +FULL_DTC_PATH=$(srctree)/scripts/dtc/libfdt > > > + > > > +obj-$(CONFIG_FPGA_XRT_LIB) += xrt-lib.o > > > + > > > +xrt-lib-objs := \ > > > + main.o \ > > > + xroot.o \ > > > + xclbin.o \ > > > + subdev.o \ > > > + cdev.o \ > > > + group.o \ > > > + xleaf/vsec.o \ > > > + xleaf/axigate.o \ > > > + xleaf/devctl.o \ > > > + xleaf/icap.o \ > > > + xleaf/clock.o \ > > > + xleaf/clkfreq.o \ > > > + xleaf/ucs.o \ > > > + xleaf/calib.o \ > > > + > > > +ccflags-y := -I$(FULL_XRT_PATH)/include \ > > > + -I$(FULL_DTC_PATH) > > > diff --git a/drivers/fpga/xrt/metadata/Kconfig > > > b/drivers/fpga/xrt/metadata/Kconfig > > > new file mode 100644 > > > index 000000000000..5012c9c6584d > > > --- /dev/null > > > +++ b/drivers/fpga/xrt/metadata/Kconfig > > > @@ -0,0 +1,12 @@ > > > +# SPDX-License-Identifier: GPL-2.0-only # # XRT Alveo FPGA device > > > +configuration # > > > + > > > +config FPGA_XRT_METADATA > > > + bool "XRT Alveo Driver Metadata Parser" > > > + select LIBFDT > > > + help > > > + This option provides helper functions to parse Xilinx Alveo FPGA > > > + firmware metadata. The metadata is in device tree format and XRT > > and the XRT > > > + driver uses it to discover HW subsystems behind PCIe BAR. > > the HW > > > diff --git a/drivers/fpga/xrt/metadata/Makefile > > > b/drivers/fpga/xrt/metadata/Makefile > > > new file mode 100644 > > > index 000000000000..14f65ef1595c > > > --- /dev/null > > > +++ b/drivers/fpga/xrt/metadata/Makefile > > > @@ -0,0 +1,16 @@ > > > +# SPDX-License-Identifier: GPL-2.0 > > > +# > > > +# Copyright (C) 2020-2021 Xilinx, Inc. All rights reserved. > > > +# > > > +# Authors: Sonal.Santan@xilinx.com > > > +# > > > + > > > +FULL_XRT_PATH=$(srctree)/$(src)/.. > > > +FULL_DTC_PATH=$(srctree)/scripts/dtc/libfdt > > > + > > > +obj-$(CONFIG_FPGA_XRT_METADATA) += xrt-md.o > > > + > > > +xrt-md-objs := metadata.o > > > + > > > +ccflags-y := -I$(FULL_XRT_PATH)/include \ > > > + -I$(FULL_DTC_PATH) > > > diff --git a/drivers/fpga/xrt/mgmt/Kconfig > > > b/drivers/fpga/xrt/mgmt/Kconfig new file mode 100644 index > > > 000000000000..2b2a2c34685c > > > --- /dev/null > > > +++ b/drivers/fpga/xrt/mgmt/Kconfig > > > @@ -0,0 +1,15 @@ > > > +# SPDX-License-Identifier: GPL-2.0-only # # Xilinx XRT FPGA device > > > +configuration # > > > + > > > +config FPGA_XRT_XMGMT > > > + tristate "Xilinx Alveo Management Driver" > > > + depends on HWMON && PCI && FPGA_XRT_LIB > > > > FPGA_XRT_LIB also depends on HWMON and PCI, so this could be minimized. > > > > Tom > > > > > + select FPGA_XRT_METADATA > > > + select FPGA_BRIDGE > > > + select FPGA_REGION > > > + help > > > + Select this option to enable XRT PCIe driver for Xilinx Alveo FPGA. > > > + This driver provides interfaces for userspace application to access > > > + Alveo FPGA device. > > > diff --git a/drivers/fpga/xrt/mgmt/Makefile > > > b/drivers/fpga/xrt/mgmt/Makefile new file mode 100644 index > > > 000000000000..8051708c361c > > > --- /dev/null > > > +++ b/drivers/fpga/xrt/mgmt/Makefile > > > @@ -0,0 +1,19 @@ > > > +# SPDX-License-Identifier: GPL-2.0 > > > +# > > > +# Copyright (C) 2020-2021 Xilinx, Inc. All rights reserved. > > > +# > > > +# Authors: Sonal.Santan@xilinx.com > > > +# > > > + > > > +FULL_XRT_PATH=$(srctree)/$(src)/.. > > > +FULL_DTC_PATH=$(srctree)/scripts/dtc/libfdt > > > + > > > +obj-$(CONFIG_FPGA_XRT_XMGMT) += xmgmt.o > > > + > > > +xmgmt-objs := root.o \ > > > + main.o \ > > > + fmgr-drv.o \ > > > + main-region.o > > > + > > > +ccflags-y := -I$(FULL_XRT_PATH)/include \ > > > + -I$(FULL_DTC_PATH) > > > > - Moritz -Sonal
Hello Tom, > -----Original Message----- > From: Tom Rix <trix@redhat.com> > Sent: Friday, February 19, 2021 2:26 PM > To: Lizhi Hou <lizhih@xilinx.com>; linux-kernel@vger.kernel.org > Cc: Lizhi Hou <lizhih@xilinx.com>; linux-fpga@vger.kernel.org; Max Zhen > <maxz@xilinx.com>; Sonal Santan <sonals@xilinx.com>; Michal Simek > <michals@xilinx.com>; Stefano Stabellini <stefanos@xilinx.com>; > devicetree@vger.kernel.org; mdf@kernel.org; robh@kernel.org; Max Zhen > <maxz@xilinx.com> > Subject: Re: [PATCH V3 XRT Alveo 01/18] Documentation: fpga: Add a > document describing XRT Alveo drivers > > From the documentation, there are a couple of big questions and a bunch of > word smithing. > > pseudo-bus : do we need a bus ? We are looking for guidance here. > > xrt-lib real platform devices that aren't fpga, do they need to move to another > subsystem ? > Drivers for the IPs that show up in the Alveo shell are not generic enough. They fit into the framework that XRT uses. Is the idea that that they can be used in a different context? > Overall looks good, love the ascii art! > > On 2/17/21 10:40 PM, Lizhi Hou wrote: > > Describe XRT driver architecture and provide basic overview of Xilinx > > Alveo platform. > > > > Signed-off-by: Sonal Santan <sonal.santan@xilinx.com> > > Signed-off-by: Max Zhen <max.zhen@xilinx.com> > > Signed-off-by: Lizhi Hou <lizhih@xilinx.com> > > --- > > Documentation/fpga/index.rst | 1 + > > Documentation/fpga/xrt.rst | 842 > +++++++++++++++++++++++++++++++++++ > > 2 files changed, 843 insertions(+) > > create mode 100644 Documentation/fpga/xrt.rst > > > > diff --git a/Documentation/fpga/index.rst > > b/Documentation/fpga/index.rst index f80f95667ca2..30134357b70d 100644 > > --- a/Documentation/fpga/index.rst > > +++ b/Documentation/fpga/index.rst > > @@ -8,6 +8,7 @@ fpga > > :maxdepth: 1 > > > > dfl > > + xrt > > > > .. only:: subproject and html > > > > diff --git a/Documentation/fpga/xrt.rst b/Documentation/fpga/xrt.rst > > new file mode 100644 index 000000000000..9bc2d2785cb9 > > --- /dev/null > > +++ b/Documentation/fpga/xrt.rst > > @@ -0,0 +1,842 @@ > > +.. SPDX-License-Identifier: GPL-2.0 > > + > > +================================== > > +XRTV2 Linux Kernel Driver Overview > > +================================== > > + > > +Authors: > > + > > +* Sonal Santan <sonal.santan@xilinx.com> > > +* Max Zhen <max.zhen@xilinx.com> > > +* Lizhi Hou <lizhi.hou@xilinx.com> > > + > > +XRTV2 drivers are second generation `XRT > > +<https://github.com/Xilinx/XRT>`_ drivers which support `Alveo > > +<https://www.xilinx.com/products/boards-and-kits/alveo.html>`_ > > +PCIe platforms from Xilinx. > > + > > +XRTV2 drivers support *subsystem* style data driven platforms where > > +driver's > where the driver's > > +configuration and behavior is determined by meta data provided by the > > +platform (in *device tree* format). Primary management physical > > +function (MPF) driver is called **xmgmt**. Primary user physical > > +function (UPF) driver is called > > +**xuser** and is under development. xrt driver framework and HW > > +subsystem drivers are packaged into a library module called > > +**xrt-lib**, which is shared by **xmgmt** and **xuser** (under > > +development). The xrt driver framework > xuser still under development ? > > +implements a pseudo-bus which is used to discover HW subsystems and > > +facilitate > > A pseudo-bus. > > It would be good if this was close to what was done for dfl here > > https://lore.kernel.org/linux-fpga/1605159759-3439-1-git-send-email- > yilun.xu@intel.com/ > I am wondering if we can phase in the migration to formal bus architecture based on struct bus_type as a follow on set of patches? > > +inter HW subsystem interaction. > > + > > +Driver Modules > > +============== > > + > > +xrt-lib.ko > > +---------- > > + > > +Repository of all subsystem drivers and pure software modules that > > +can potentially > > subsystem drivers > > drivers in fpga/ should be for managing just the fpganess of the fpga. > > soft devices ex/ a soft tty should go to their respective subsystem location > > Are there any in this patchset you think might move ? We have already shrunk the patch to only include FPGA centric pieces necessary to get the bitstream download implemented. Should we explore the question of subsystem drivers when we add support for more features of the Alveo shell? > > Maybe we can defer reviewing those now. > > > +be shared between xmgmt and xuser. All these drivers are structured > > +as Linux *platform driver* and are instantiated by xmgmt (or xuser > > +under development) based on meta data associated with hardware. The > > +metadata is in the form of device tree > > with the hardware > > form of a device tree > Will change > > +as mentioned before. Each platform driver statically defines a > > +subsystem node array by using node name or a string in its > > +``compatible`` property. And this array is eventually translated to IOMEM > resources of the platform device. > > + > > +The xrt-lib core infrastructure provides hooks to platform drivers > > +for device node management, user file operations and ioctl callbacks. > > +The core also provides pseudo-bus functionality for platform driver > > +registration, discovery and inter platform driver ioctl calls. > > core infrastructure. > Will update. > The interfaces to the infrastructure are not in include/linux/fpga/ > > Maybe this needs to change. > Were you thinking of moving XRT infrastructure header files from drivers/fpga/xrt/include to include/linux/fpga? > > + > > +.. note:: > > + See code in ``include/xleaf.h`` > > + > > + > > +xmgmt.ko > > +-------- > > + > > +The xmgmt driver is a PCIe device driver driving MPF found on > > +Xilinx's Alveo PCIE device. It consists of one *root* driver, one or > > +more *group* drivers and one or more *xleaf* drivers. The root and > > +MPF specific xleaf drivers are in xmgmt.ko. The group driver and other xleaf > drivers are in xrt-lib.ko. > I am not sure if *.ko is correct, these will also be intree. > > + > > +The instantiation of specific group driver or xleaf driver is > > +completely data > of a specific > > +driven based on meta data (mostly in device tree format) found > > +through VSEC > mostly ? what is the deviation from device tree ? > > +capability and inside firmware files, such as platform xsabin or user xclbin > file. > > +The root driver manages life cycle of multiple group drivers, which, > > +in turn, > the life cycle > > +manages multiple xleaf drivers. This allows a single set of driver > > +code to support > > set of drivers > > drop 'code' > Will update > > +all kinds of subsystems exposed by different shells. The difference > > +among all these subsystems will be handled in xleaf drivers with root > > +and group drivers being part of the infrastructure and provide common > > +services for all leaves found on all platforms. > > + > > +The driver object model looks like the following:: > > + > > + +-----------+ > > + | xroot | > > + +-----+-----+ > > + | > > + +-----------+-----------+ > > + | | > > + v v > > + +-----------+ +-----------+ > > + | group | ... | group | > > + +-----+-----+ +------+----+ > > + | | > > + | | > > + +-----+----+ +-----+----+ > > + | | | | > > + v v v v > > + +-------+ +-------+ +-------+ +-------+ > > + | xleaf |..| xleaf | | xleaf |..| xleaf | > > + +-------+ +-------+ +-------+ +-------+ > > + > > +As an example for Xilinx Alveo U50 before user xclbin download, the > > +tree looks like the following:: > > + > > + +-----------+ > > + | xmgmt | > > + +-----+-----+ > > + | > > + +-------------------------+--------------------+ > > + | | | > > + v v v > > + +--------+ +--------+ +--------+ > > + | group0 | | group1 | | group2 | > > + +----+---+ +----+---+ +---+----+ > > + | | | > > + | | | > > + +-----+-----+ +----+-----+---+ +-----+-----+----+--------+ > > + | | | | | | | | | > > + v v | v v | v v | > > + +------------+ +------+ | +------+ +------+ | +------+ > > + +------------+ +-----------+ | > > + | xmgmt_main | | VSEC | | | GPIO | | QSPI | | | CMC | | > > + | AXI-GATE0 | | > > + +------------+ +------+ | +------+ +------+ | +------+ > > + +------------+ +-----------+ | > > + | +---------+ | +------+ +-----------+ | > > + +>| MAILBOX | +->| ICAP | | AXI-GATE1 |<+ > > + +---------+ | +------+ +-----------+ > > + | +-------+ > > + +->| CALIB | > > + +-------+ > > + > Nice ascii art! > > +After an xclbin is download, group3 will be added and the tree looks > > +like the > > +following:: > > + > > + +-----------+ > > + | xmgmt | > > + +-----+-----+ > > + | > > + +-------------------------+--------------------+-----------------+ > > + | | | | > > + v v v | > > + +--------+ +--------+ +--------+ | > > + | group0 | | group1 | | group2 | | > > + +----+---+ +----+---+ +---+----+ | > > + | | | | > > + | | | | > > + +-----+-----+ +-----+-----+---+ +-----+-----+----+--------+ | > > + | | | | | | | | | | > > + v v | v v | v v | | > > + +------------+ +------+ | +------+ +------+ | +------+ +-----------+ | | > > + | xmgmt_main | | VSEC | | | GPIO | | QSPI | | | CMC | | AXI-GATE0 | | > | > > + +------------+ +------+ | +------+ +------+ | +------+ +-----------+ | | > > + | +---------+ | +------+ +-----------+ | | > > + +>| MAILBOX | +->| ICAP | | AXI-GATE1 |<+ | > > + +---------+ | +------+ +-----------+ | > > + | +-------+ | > > + +->| CALIB | | > > + +-------+ | > > + +---+----+ | > > + | group3 |<--------------------------------------------+ > > + +--------+ > > + | > > + | > > + +-------+--------+---+--+--------+------+-------+ > > + | | | | | | | > > + v | v | v | v > > + +--------+ | +--------+ | +--------+ | +-----+ > > + | CLOCK0 | | | CLOCK1 | | | CLOCK2 | | | UCS | > > + +--------+ v +--------+ v +--------+ v +-----+ > > + +-------------+ +-------------+ +-------------+ > > + | CLOCK-FREQ0 | | CLOCK-FREQ1 | | CLOCK-FREQ2 | > > + +-------------+ +-------------+ +-------------+ > > + > > + > > +xmgmt-root > > +^^^^^^^^^^ > > + > > +The xmgmt-root driver is a PCIe device driver attached to MPF. It's > > +part of the infrastructure of the MPF driver and resides in xmgmt.ko. > > +This driver > > + > > +* manages one or more group drivers > > +* provides access to functionalities that requires pci_dev, such as > > +PCIE config > > + space access, to other xleaf drivers through root calls > > +* together with group driver, facilities event callbacks for other > > +xleaf drivers > > +* together with group driver, facilities inter-leaf driver calls for > > +other xleaf > Maybe drop 'together with group driver' Will update > > + drivers > > + > > +When root driver starts, it will explicitly create an initial group > > +instance, which contains xleaf drivers that will trigger the creation > > +of other group instances. The root driver will wait for all group and > > +leaves to be created before it returns from it's probe routine and > > +claim success of the initialization of the entire xmgmt driver. > What happens if there a failure in one leaf ? Does the whole board go down ? > > + > > +.. note:: > > + See code in ``lib/xroot.c`` and ``mgmt/root.c`` > > + > > + > > +group > > +^^^^^ > > + > > +The group driver is a platform device driver whose life cycle is > > +managed by > Maybe call this a 'pseudo device' Will update > > +root and does not have real IO mem or IRQ resources. It's part of the > > +infrastructure of the MPF driver and resides in xrt-lib.ko. This > > +driver > > + > > +* manages one or more xleaf drivers so that multiple leaves can be > > +managed as a > > + group > can drop 'so that multiple leaves can be managed as a group' to me, this is the > same as 'one or more' Will do > > +* provides access to root from leaves, so that root calls, event > > +notifications > > + and inter-leaf calls can happen > > + > > +In xmgmt, an initial group driver instance will be created by root, > > +which > by the root > > +contains leaves that will trigger group instances to be created to > > +manage groups of leaves found on different partitions on hardware, > > +such as VSEC, Shell, and User. > > + > > +Every *fpga_region* has a group object associated with it. The group > > +is created when xclbin image is loaded on the fpga_region. The > > +existing group is destroyed when a new xclbin image is loaded. The > > +fpga_region persists across xclbin downloads. > The connection of a 'group' node to a fpga region region is fairly important, > maybe move this section earlier. 'group' as an fpganess thing would be kept in > fpga/ subsystem. Will update > > + > > +.. note:: > > + See code in ``lib/group.c`` > > + > > + > > +xleaf > > +^^^^^ > > + > > +The xleaf driver is a platform device driver whose life cycle is > > +managed by a group driver and may or may not have real IO mem or IRQ > > +resources. They are the real meat of xmgmt and contains platform > > +specific code to Shell and User found on a MPF. > > + > > Maybe a split is pseudo device leaves, those without real IO mem, stay in > fpga/ others go ? > This goes back to the earlier question of what minimal set of platform drivers should stay in fpga subsystem. There are some like bridge or configuration engine (also called icap) which have their own IO mem but do not have a life outside of fpga subsystem. > > +A xleaf driver may not have real hardware resources when it merely > > +acts as a driver that manages certain in-memory states for xmgmt. > > +These in-memory states could be shared by multiple other leaves. > > + > This implies locking and some message passing. > > +Leaf drivers assigned to specific hardware resources drive specific > > +subsystem in > drive a specific > > +the device. To manipulate the subsystem or carry out a task, a xleaf > > +driver may ask help from root via root calls and/or from other leaves via > inter-leaf calls. > > + > > +A xleaf can also broadcast events through infrastructure code for > > +other leaves to process. It can also receive event notification from > > +infrastructure about certain events, such as post-creation or pre-exit of a > particular xleaf. > I would like to see some examples of how the inter node communications work. Would update to show an example. > > + > > +.. note:: > > + See code in ``lib/xleaf/*.c`` > > + > > + > > +FPGA Manager Interaction > > +======================== > > + > > +fpga_manager > > +------------ > > + > > +An instance of fpga_manager is created by xmgmt_main and is used for > > +xclbin > for the xclbin > > +image download. fpga_manager requires the full xclbin image before it > > +can start programming the FPGA configuration engine via ICAP platform > driver. > > via the ICAP > > what is ICAP ? Will update. ICAP stands for Internal Configuration Access Port used for configuring the fpga. > > > + > > +fpga_region > > +----------- > > + > > +For every interface exposed by currently loaded xclbin/xsabin in the > > +*parent* > by the currently > > +fpga_region a new instance of fpga_region is created like a *child* region. > fpga_region, > > +The device tree of the *parent* fpga_region defines the resources for > > +a new instance of fpga_bridge which isolates the parent from > and isolates > > +child fpga_region. This new instance of fpga_bridge will be used when > > +a xclbin image is loaded on the child fpga_region. After the xclbin > > +image is downloaded to the fpga_region, an instance of group is > > +created for the fpga_region using the device tree obtained as part of > > +xclbin. If this device > of the xclbin > > +tree defines any child interfaces then it can trigger the creation of > interfaces, then > > +fpga_bridge and fpga_region for the next region in the chain. > a fpga_bridge and a fpga_region > > + > > +fpga_bridge > > +----------- > > + > > +Like fpga_region, matching fpga_bridge is also created by walking the > > +device > Like the fpga_region, a matchin > > +tree of the parent group. > > + > > +Driver Interfaces > > +================= > > + > > +xmgmt Driver Ioctls > > +------------------- > > + > > +Ioctls exposed by xmgmt driver to user space are enumerated in the > > +following > > +table: > > + > > +== ===================== ============================ > ========================== > > +# Functionality ioctl request code data format > > +== ===================== ============================ > ========================== > > +1 FPGA image download XMGMT_IOCICAPDOWNLOAD_AXLF > xmgmt_ioc_bitstream_axlf > > +== ===================== ============================ > > +========================== > > This data format is described below, maybe swap this section with that so > > folks will know what xmgmnt_ioc_bitstream_axlf is before this section. > Will update. > > + > > +User xclbin can be downloaded by using xbmgmt tool from XRT open > > +source suite. See > > A user xclbin > > using the xbmgmt > > from the XRT > Will update > > +example usage below:: > > + > > + xbmgmt partition --program --path > > + /lib/firmware/xilinx/862c7020a250293e32036f19956669e5/test/verify.xc > > + lbin --force > > + > > +xmgmt Driver Sysfs > > +------------------ > > + > > +xmgmt driver exposes a rich set of sysfs interfaces. Subsystem > > +platform drivers export sysfs node for every platform instance. > > + > > +Every partition also exports its UUIDs. See below for examples:: > > + > > + /sys/bus/pci/devices/0000:06:00.0/xmgmt_main.0/interface_uuids > > + /sys/bus/pci/devices/0000:06:00.0/xmgmt_main.0/logic_uuids > > + > > + > > +hwmon > > +----- > > + > > +xmgmt driver exposes standard hwmon interface to report voltage, > > +current, temperature, power, etc. These can easily be viewed using > > +*sensors* command line utility. > > + > > +Alveo Platform Overview > > +======================= > > + > > +Alveo platforms are architected as two physical FPGA partitions: > > +*Shell* and *User*. The Shell provides basic infrastructure for the > > +Alveo platform like PCIe connectivity, board management, Dynamic > > +Function Exchange (DFX), sensors, clocking, reset, and security. User > > +partition contains user compiled FPGA > the user compiled > > +binary which is loaded by a process called DFX also known as partial > > +reconfiguration. > > + > > +Physical partitions require strict HW compatibility with each other > > +for DFX to work properly. > > swap order > > For DFX to work properly physical partitions .. > > Will update > > Every physical partition has two interface UUIDs: *parent* UUID > > +and *child* UUID. For simple single stage platforms, Shell → User > > +forms parent child relationship. For complex two stage platforms, > > +Base → Shell → User forms the parent child relationship chain. > this bit is confusing. is this related to uuid? > > + > > +.. note:: > > + Partition compatibility matching is key design component of Alveo > platforms > > + and XRT. Partitions have child and parent relationship. A loaded > > +partition > have a child > > + exposes child partition UUID to advertise its compatibility > > + requirement for > > the child's > > can drop 'for child partition' Will update > > > + child partition. When loading a child partition the xmgmt > > + management driver > When loading a child partition, > > + matches parent UUID of the child partition against child UUID exported by > > + the parent. Parent and child partition UUIDs are stored in the *xclbin* > > + (for user) or *xsabin* (for base and shell). > > this is confusing, is this part of the file image format ? > > Maybe save/move till the image layout. Yes these IDs are stored in xclbin image format. Will move the sections around as suggested. > > > Except for root UUID, VSEC, > > + hardware itself does not know about UUIDs. UUIDs are stored in xsabin > and > > + xclbin. > This is confusing too, not sure how to untangle. Will reword. > > + > > + > > +The physical partitions and their loading is illustrated below:: > > + > > + SHELL USER > > + +-----------+ +-------------------+ > > + | | | | > > + | VSEC UUID | CHILD PARENT | LOGIC UUID | > > + | o------->|<--------o | > > + | | UUID UUID | | > > + +-----+-----+ +--------+----------+ > > + | | > > + . . > > + | | > > + +---+---+ +------+--------+ > > + | POR | | USER COMPILED | > > + | FLASH | | XCLBIN | > > + +-------+ +---------------+ > > + > > + > > +Loading Sequence > > +---------------- > > + > > +The Shell partition is loaded from flash at system boot time. It > > +establishes the PCIe link and exposes two physical functions to the > > +BIOS. After OS boot, xmgmt > the OS boots, the xmgmt > > +driver attaches to PCIe physical function 0 exposed by the Shell and > > +then looks for VSEC in PCIe extended configuration space. Using VSEC > > +it determines the logic > > the PCIe > > The driver uses VSEC to determine the UUID of Shell. The UUID is also used to > load a matching ... > Will update > > +UUID of Shell and uses the UUID to load matching *xsabin* file from > > +Linux firmware directory. The xsabin file contains metadata to > > +discover peripherals that are part of Shell and firmware(s) for any > embedded soft processors in Shell. > the firmware needed for any ... Will update > > + > > +The Shell exports child interface UUID which is used for > > +compatibility check when > > export a child > > for a compatibility check > Will update > > +loading user compiled xclbin over the User partition as part of DFX. > > +When a user requests loading of a specific xclbin the xmgmt > > +management driver reads the parent > xclbin, the > > +interface UUID specified in the xclbin and matches it with child > > +interface UUID exported by Shell to determine if xclbin is compatible > > +with the Shell. If match fails loading of xclbin is denied. > > + > > +xclbin loading is requested using ICAP_DOWNLOAD_AXLF ioctl command. > > +When loading xclbin, xmgmt driver performs the following *logical* > operations: > > + > > +1. Copy xclbin from user to kernel memory 2. Sanity check the xclbin > > +contents 3. Isolate the User partition 4. Download the bitstream > > +using the FPGA config engine (ICAP) 5. De-isolate the User partition > > +6. Program the clocks (ClockWiz) driving the User partition > maybe drop '(ClockWiz)' > > +7. Wait for memory controller (MIG) calibration > for the > > +8. Return the loading status back to the caller > > + > > +`Platform Loading Overview > > +<https://xilinx.github.io/XRT/master/html/platforms_partitions.html>` > > +_ provides more detailed information on platform loading. > > + > the link works. > > + > > +xsabin > > +------ > > + > > +Each Alveo platform comes packaged with its own xsabin. The xsabin is > > +trusted > is a trusted > > +component of the platform. For format details refer to > > +:ref:`xsabin_xclbin_container_format` > > +below. xsabin contains basic information like UUIDs, platform name > > +and metadata in the form of device tree. See :ref:`device_tree_usage` > below for details and example. > of a device > > + > > +xclbin > > +------ > > + > > +xclbin is compiled by end user using > > +`Vitis > > +<https://www.xilinx.com/products/design-tools/vitis/vitis-platform.ht > > +ml>`_ > this link works, seems reasonable landing > > +tool set from Xilinx. The xclbin contains sections describing user > > +compiled acceleration engines/kernels, memory subsystems, clocking > > +information etc. It also contains bitstream for the user partition, > > +UUIDs, platform name, etc. xclbin uses > bitstreams > > +the same container format as xsabin which is described below. > > + > > + > > +.. _xsabin_xclbin_container_format: > > + > > +xsabin/xclbin Container Format > > +------------------------------ > > + > > +xclbin/xsabin is ELF-like binary container format. It is structured > > +as series of sections. There is a file header followed by several > > +section headers which is followed by sections. A section header > > +points to an actual section. There is an optional signature at the end. The > format is defined by header file ``xclbin.h``. > > +The following figure illustrates a typical xclbin:: > > + > > + > > + +---------------------+ > > + | | > > + | HEADER | > > + +---------------------+ > > + | SECTION HEADER | > > + | | > > + +---------------------+ > > + | ... | > > + | | > > + +---------------------+ > > + | SECTION HEADER | > > + | | > > + +---------------------+ > > + | SECTION | > > + | | > > + +---------------------+ > > + | ... | > > + | | > > + +---------------------+ > > + | SECTION | > > + | | > > + +---------------------+ > > + | SIGNATURE | > > + | (OPTIONAL) | > > + +---------------------+ > > + > > + > > +xclbin/xsabin files can be packaged, un-packaged and inspected using > > +XRT utility called **xclbinutil**. xclbinutil is part of XRT open > > +source software stack. The source code for xclbinutil can be found at > > +https://github.com/Xilinx/XRT/tree/master/src/runtime_src/tools/xclbi > > +nutil > > + > Works, but maybe the location of a manpage or doc would be better. > > +For example to enumerate the contents of a xclbin/xsabin use the > > +*--info* switch as shown below:: > > + > > + > > + xclbinutil --info --input > > + /opt/xilinx/firmware/u50/gen3x16-xdma/blp/test/bandwidth.xclbin > > + xclbinutil --info --input > > + /lib/firmware/xilinx/862c7020a250293e32036f19956669e5/partition.xsab > > + in > > + > > + > > +.. _device_tree_usage: > > + > > +Device Tree Usage > > +----------------- > > + > > +As mentioned previously xsabin stores metadata which advertise HW > > +subsystems present in a partition. The metadata is stored in device tree > format with well defined schema. > > +XRT management driver uses this information to bind *platform > > +drivers* to the subsystem instantiations. The platform drivers are > > +found in **xrt-lib.ko** kernel module defined later. > > + > > +Logic UUID > > +^^^^^^^^^^ > > +A partition is identified uniquely through ``logic_uuid`` property:: > > + > > + /dts-v1/; > > + / { > > + logic_uuid = "0123456789abcdef0123456789abcdef"; > > + ... > > + } > > + > > +Schema Version > > +^^^^^^^^^^^^^^ > > +Schema version is defined through ``schema_version`` node. And it > > +contains ``major`` and ``minor`` properties as below:: > > + > > + /dts-v1/; > > + / { > > + schema_version { > > + major = <0x01>; > > + minor = <0x00>; > > + }; > > + ... > > + } > > + > > +Partition UUIDs > > +^^^^^^^^^^^^^^^ > > +As said earlier, each partition may have parent and child UUIDs. > > +These UUIDs are defined by ``interfaces`` node and ``interface_uuid`` > property:: > > + > > + /dts-v1/; > > + / { > > + interfaces { > > + @0 { > > + interface_uuid = "0123456789abcdef0123456789abcdef"; > > + }; > > + @1 { > > + interface_uuid = "fedcba9876543210fedcba9876543210"; > > + }; > > + ... > > + }; > > + ... > > + } > > + > > + > > +Subsystem Instantiations > > +^^^^^^^^^^^^^^^^^^^^^^^^ > > +Subsystem instantiations are captured as children of > > +``addressable_endpoints`` > > +node:: > > + > > + /dts-v1/; > > + / { > > + addressable_endpoints { > > + abc { > > + ... > > + }; > > + def { > > + ... > > + }; > > + ... > > + } > > + } > > + > > +Subnode 'abc' and 'def' are the name of subsystem nodes > > + > > +Subsystem Node > > +^^^^^^^^^^^^^^ > > +Each subsystem node and its properties define a hardware instance:: > > + > > + > > + addressable_endpoints { > > + abc { > > + reg = <0xa 0xb> > > + pcie_physical_function = <0x0>; > > + pcie_bar_mapping = <0x2>; > > + compatible = "abc def"; > > + firmware { > > + firmware_product_name = "abc" > > + firmware_branch_name = "def" > > + firmware_version_major = <1> > > + firmware_version_minor = <2> > > + }; > > + } > > + ... > > + } > > + > > +:reg: > > + Property defines address range. '<0xa 0xb>' is BAR offset and length > > +pair, both are 64-bit integer. > > +:pcie_physical_function: > > + Property specifies which PCIe physical function the subsystem node resides. > > +:pcie_bar_mapping: > > + Property specifies which PCIe BAR the subsystem node resides. > > +'<0x2>' is BAR index and it is 0 if this property is not defined. > > +:compatible: > > + Property is a list of strings. The first string in the list > > +specifies the exact subsystem node. The following strings represent > > +other devices that the device is compatible with. > > +:firmware: > > + Subnode defines the firmware required by this subsystem node. > > + > > +Alveo U50 Platform Example > > +^^^^^^^^^^^^^^^^^^^^^^^^^^ > > +:: > > + > > + /dts-v1/; > > + > > + /{ > > + logic_uuid = "f465b0a3ae8c64f619bc150384ace69b"; > > + > > + schema_version { > > + major = <0x01>; > > + minor = <0x00>; > > + }; > > + > > + interfaces { > > + > > + @0 { > > + interface_uuid = "862c7020a250293e32036f19956669e5"; > > + }; > > + }; > > + > > + addressable_endpoints { > > + > > + ep_blp_rom_00 { > > + reg = <0x00 0x1f04000 0x00 0x1000>; > > + pcie_physical_function = <0x00>; > > + compatible = "xilinx.com,reg_abs-axi_bram_ctrl- > 1.0\0axi_bram_ctrl"; > > + }; > > + > > + ep_card_flash_program_00 { > > + reg = <0x00 0x1f06000 0x00 0x1000>; > > + pcie_physical_function = <0x00>; > > + compatible = "xilinx.com,reg_abs-axi_quad_spi- > 1.0\0axi_quad_spi"; > > + interrupts = <0x03 0x03>; > > + }; > > + > > + ep_cmc_firmware_mem_00 { > > + reg = <0x00 0x1e20000 0x00 0x20000>; > > + pcie_physical_function = <0x00>; > > + compatible = > > + "xilinx.com,reg_abs-axi_bram_ctrl-1.0\0axi_bram_ctrl"; > > + > > + firmware { > > + firmware_product_name = "cmc"; > > + firmware_branch_name = "u50"; > > + firmware_version_major = <0x01>; > > + firmware_version_minor = <0x00>; > > + }; > > + }; > > + > > + ep_cmc_intc_00 { > > + reg = <0x00 0x1e03000 0x00 0x1000>; > > + pcie_physical_function = <0x00>; > > + compatible = "xilinx.com,reg_abs-axi_intc-1.0\0axi_intc"; > > + interrupts = <0x04 0x04>; > > + }; > > + > > + ep_cmc_mutex_00 { > > + reg = <0x00 0x1e02000 0x00 0x1000>; > > + pcie_physical_function = <0x00>; > > + compatible = "xilinx.com,reg_abs-axi_gpio-1.0\0axi_gpio"; > > + }; > > + > > + ep_cmc_regmap_00 { > > + reg = <0x00 0x1e08000 0x00 0x2000>; > > + pcie_physical_function = <0x00>; > > + compatible = > > + "xilinx.com,reg_abs-axi_bram_ctrl-1.0\0axi_bram_ctrl"; > > + > > + firmware { > > + firmware_product_name = "sc-fw"; > > + firmware_branch_name = "u50"; > > + firmware_version_major = <0x05>; > > + }; > > + }; > > + > > + ep_cmc_reset_00 { > > + reg = <0x00 0x1e01000 0x00 0x1000>; > > + pcie_physical_function = <0x00>; > > + compatible = "xilinx.com,reg_abs-axi_gpio-1.0\0axi_gpio"; > > + }; > > + > > + ep_ddr_mem_calib_00 { > > + reg = <0x00 0x63000 0x00 0x1000>; > > + pcie_physical_function = <0x00>; > > + compatible = "xilinx.com,reg_abs-axi_gpio-1.0\0axi_gpio"; > > + }; > > + > > + ep_debug_bscan_mgmt_00 { > > + reg = <0x00 0x1e90000 0x00 0x10000>; > > + pcie_physical_function = <0x00>; > > + compatible = "xilinx.com,reg_abs-debug_bridge- > 1.0\0debug_bridge"; > > + }; > > + > > + ep_ert_base_address_00 { > > + reg = <0x00 0x21000 0x00 0x1000>; > > + pcie_physical_function = <0x00>; > > + compatible = "xilinx.com,reg_abs-axi_gpio-1.0\0axi_gpio"; > > + }; > > + > > + ep_ert_command_queue_mgmt_00 { > > + reg = <0x00 0x40000 0x00 0x10000>; > > + pcie_physical_function = <0x00>; > > + compatible = "xilinx.com,reg_abs-ert_command_queue- > 1.0\0ert_command_queue"; > > + }; > > + > > + ep_ert_command_queue_user_00 { > > + reg = <0x00 0x40000 0x00 0x10000>; > > + pcie_physical_function = <0x01>; > > + compatible = "xilinx.com,reg_abs-ert_command_queue- > 1.0\0ert_command_queue"; > > + }; > > + > > + ep_ert_firmware_mem_00 { > > + reg = <0x00 0x30000 0x00 0x8000>; > > + pcie_physical_function = <0x00>; > > + compatible = > > + "xilinx.com,reg_abs-axi_bram_ctrl-1.0\0axi_bram_ctrl"; > > + > > + firmware { > > + firmware_product_name = "ert"; > > + firmware_branch_name = "v20"; > > + firmware_version_major = <0x01>; > > + }; > > + }; > > + > > + ep_ert_intc_00 { > > + reg = <0x00 0x23000 0x00 0x1000>; > > + pcie_physical_function = <0x00>; > > + compatible = "xilinx.com,reg_abs-axi_intc-1.0\0axi_intc"; > > + interrupts = <0x05 0x05>; > > + }; > > + > > + ep_ert_reset_00 { > > + reg = <0x00 0x22000 0x00 0x1000>; > > + pcie_physical_function = <0x00>; > > + compatible = "xilinx.com,reg_abs-axi_gpio-1.0\0axi_gpio"; > > + }; > > + > > + ep_ert_sched_00 { > > + reg = <0x00 0x50000 0x00 0x1000>; > > + pcie_physical_function = <0x01>; > > + compatible = "xilinx.com,reg_abs-ert_sched-1.0\0ert_sched"; > > + interrupts = <0x09 0x0c>; > > + }; > > + > > + ep_fpga_configuration_00 { > > + reg = <0x00 0x1e88000 0x00 0x8000>; > > + pcie_physical_function = <0x00>; > > + compatible = "xilinx.com,reg_abs-axi_hwicap- > 1.0\0axi_hwicap"; > > + interrupts = <0x02 0x02>; > > + }; > > + > > + ep_icap_reset_00 { > > + reg = <0x00 0x1f07000 0x00 0x1000>; > > + pcie_physical_function = <0x00>; > > + compatible = "xilinx.com,reg_abs-axi_gpio-1.0\0axi_gpio"; > > + }; > > + > > + ep_msix_00 { > > + reg = <0x00 0x00 0x00 0x20000>; > > + pcie_physical_function = <0x00>; > > + compatible = "xilinx.com,reg_abs-msix-1.0\0msix"; > > + pcie_bar_mapping = <0x02>; > > + }; > > + > > + ep_pcie_link_mon_00 { > > + reg = <0x00 0x1f05000 0x00 0x1000>; > > + pcie_physical_function = <0x00>; > > + compatible = "xilinx.com,reg_abs-axi_gpio-1.0\0axi_gpio"; > > + }; > > + > > + ep_pr_isolate_plp_00 { > > + reg = <0x00 0x1f01000 0x00 0x1000>; > > + pcie_physical_function = <0x00>; > > + compatible = "xilinx.com,reg_abs-axi_gpio-1.0\0axi_gpio"; > > + }; > > + > > + ep_pr_isolate_ulp_00 { > > + reg = <0x00 0x1000 0x00 0x1000>; > > + pcie_physical_function = <0x00>; > > + compatible = "xilinx.com,reg_abs-axi_gpio-1.0\0axi_gpio"; > > + }; > > + > > + ep_uuid_rom_00 { > > + reg = <0x00 0x64000 0x00 0x1000>; > > + pcie_physical_function = <0x00>; > > + compatible = "xilinx.com,reg_abs-axi_bram_ctrl- > 1.0\0axi_bram_ctrl"; > > + }; > > + > > + ep_xdma_00 { > > + reg = <0x00 0x00 0x00 0x10000>; > > + pcie_physical_function = <0x01>; > > + compatible = "xilinx.com,reg_abs-xdma-1.0\0xdma"; > > + pcie_bar_mapping = <0x02>; > > + }; > > + }; > > + > > + } > > + > > + > > + > > +Deployment Models > > +================= > > + > > +Baremetal > > +--------- > > + > > +In bare-metal deployments both MPF and UPF are visible and > > +accessible. xmgmt > In bare-meta deployments, > > +driver binds to MPF. xmgmt driver operations are privileged and > > +available to system administrator. The full stack is illustrated below:: > > + > > + HOST > > + > > + [XMGMT] [XUSER] > > + | | > > + | | > > + +-----+ +-----+ > > + | MPF | | UPF | > > + | | | | > > + | PF0 | | PF1 | > > + +--+--+ +--+--+ > > + ......... ^................. ^.......... > > + | | > > + | PCIe DEVICE | > > + | | > > + +--+------------------+--+ > > + | SHELL | > > + | | > > + +------------------------+ > > + | USER | > > + | | > > + | | > > + | | > > + | | > > + +------------------------+ > > + > > + > > + > > +Virtualized > > +----------- > > + > > +In virtualized deployments privileged MPF is assigned to host but > > +unprivileged > In virtualized deployments, the > > +UPF is assigned to guest VM via PCIe pass-through. xmgmt driver in > > +host binds > in the host > > +to MPF. xmgmt driver operations are privileged and only accessible by > > +hosting > to the MPF > > +service provider. The full stack is illustrated below:: > > + > > + > > + ............. > > + HOST . VM . > > + . . > > + [XMGMT] . [XUSER] . > > + | . | . > > + | . | . > > + +-----+ . +-----+ . > > + | MPF | . | UPF | . > > + | | . | | . > > + | PF0 | . | PF1 | . > > + +--+--+ . +--+--+ . > > + ......... ^................. ^.......... > > + | | > > + | PCIe DEVICE | > > + | | > > + +--+------------------+--+ > > + | SHELL | > > + | | > > + +------------------------+ > > + | USER | > > + | | > > + | | > > + | | > > + | | > > + +------------------------+ > > + > > + > > + > > + > > + > > +Platform Security Considerations > > +================================ > > + > > +`Security of Alveo Platform > > +<https://xilinx.github.io/XRT/master/html/security.html>`_ > > +discusses the deployment options and security implications in great detail. > > This link works and looks great. > > Tom Thanks for the detailed review of the document. I am working on incorporating the feedback. One outstanding question is about usage of formal bus in XRT and if we should phase that in as a follow-on. It would also determine if IP drivers should move to other subsystems. -Sonal
Hi Moritz, On 02/21/2021 12:43 PM, Moritz Fischer wrote: > Lizhi, > > On Wed, Feb 17, 2021 at 10:40:01PM -0800, Lizhi Hou wrote: >> Hello, >> >> This is V3 of patch series which adds management physical function driver for Xilinx >> Alveo PCIe accelerator cards, https://www.xilinx.com/products/boards-and-kits/alveo.html >> This driver is part of Xilinx Runtime (XRT) open source stack. >> >> XILINX ALVEO PLATFORM ARCHITECTURE >> >> Alveo PCIe FPGA based platforms have a static *shell* partition and a partial >> re-configurable *user* partition. The shell partition is automatically loaded from >> flash when host is booted and PCIe is enumerated by BIOS. Shell cannot be changed >> till the next cold reboot. The shell exposes two PCIe physical functions: >> >> 1. management physical function >> 2. user physical function >> >> The patch series includes Documentation/xrt.rst which describes Alveo platform, >> XRT driver architecture and deployment model in more detail. >> >> Users compile their high level design in C/C++/OpenCL or RTL into FPGA image using >> Vitis https://www.xilinx.com/products/design-tools/vitis/vitis-platform.html >> tools. The compiled image is packaged as xclbin which contains partial bitstream >> for the user partition and necessary metadata. Users can dynamically swap the image >> running on the user partition in order to switch between different workloads by >> loading different xclbins. >> >> XRT DRIVERS FOR XILINX ALVEO >> >> XRT Linux kernel driver *xmgmt* binds to management physical function of Alveo >> platform. The modular driver framework is organized into several platform drivers >> which primarily handle the following functionality: >> >> 1. Loading firmware container also called xsabin at driver attach time >> 2. Loading of user compiled xclbin with FPGA Manager integration >> 3. Clock scaling of image running on user partition >> 4. In-band sensors: temp, voltage, power, etc. >> 5. Device reset and rescan >> >> The platform drivers are packaged into *xrt-lib* helper module with well >> defined interfaces. The module provides a pseudo-bus implementation for the >> platform drivers. More details on the driver model can be found in >> Documentation/xrt.rst. >> >> User physical function driver is not included in this patch series. >> >> LIBFDT REQUIREMENT >> >> XRT driver infrastructure uses Device Tree as a metadata format to discover >> HW subsystems in the Alveo PCIe device. The Device Tree schema used by XRT >> is documented in Documentation/xrt.rst. Unlike previous V1 and V2 version >> of patch series, V3 version does not require export of libfdt symbols. >> >> TESTING AND VALIDATION >> >> xmgmt driver can be tested with full XRT open source stack which includes user >> space libraries, board utilities and (out of tree) first generation user physical >> function driver xocl. XRT open source runtime stack is available at >> https://github.com/Xilinx/XRT >> >> Complete documentation for XRT open source stack including sections on Alveo/XRT >> security and platform architecture can be found here: >> >> https://xilinx.github.io/XRT/master/html/index.html >> https://xilinx.github.io/XRT/master/html/security.html >> https://xilinx.github.io/XRT/master/html/platforms_partitions.html >> >> Changes since v2: >> - Streamlined the driver framework into *xleaf*, *group* and *xroot* >> - Updated documentation to show the driver model with examples >> - Addressed kernel test robot errors >> - Added a selftest for basic driver framework >> - Documented device tree schema >> - Removed need to export libfdt symbols >> >> Changes since v1: >> - Updated the driver to use fpga_region and fpga_bridge for FPGA >> programming >> - Dropped platform drivers not related to PR programming to focus on XRT >> core framework >> - Updated Documentation/fpga/xrt.rst with information on XRT core framework >> - Addressed checkpatch issues >> - Dropped xrt- prefix from some header files >> >> For reference V1 version of patch series can be found here: >> >> https://lore.kernel.org/lkml/20201217075046.28553-1-sonals@xilinx.com/ >> https://lore.kernel.org/lkml/20201217075046.28553-2-sonals@xilinx.com/ >> https://lore.kernel.org/lkml/20201217075046.28553-3-sonals@xilinx.com/ >> https://lore.kernel.org/lkml/20201217075046.28553-4-sonals@xilinx.com/ >> https://lore.kernel.org/lkml/20201217075046.28553-5-sonals@xilinx.com/ >> https://lore.kernel.org/lkml/20201217075046.28553-6-sonals@xilinx.com/ >> https://lore.kernel.org/lkml/20201217075046.28553-7-sonals@xilinx.com/ >> >> Lizhi Hou (18): >> Documentation: fpga: Add a document describing XRT Alveo drivers >> fpga: xrt: driver metadata helper functions >> fpga: xrt: xclbin file helper functions >> fpga: xrt: xrt-lib platform driver manager >> fpga: xrt: group platform driver >> fpga: xrt: platform driver infrastructure >> fpga: xrt: management physical function driver (root) >> fpga: xrt: main platform driver for management function device >> fpga: xrt: fpga-mgr and region implementation for xclbin download >> fpga: xrt: VSEC platform driver >> fpga: xrt: UCS platform driver >> fpga: xrt: ICAP platform driver >> fpga: xrt: devctl platform driver >> fpga: xrt: clock platform driver >> fpga: xrt: clock frequence counter platform driver >> fpga: xrt: DDR calibration platform driver >> fpga: xrt: partition isolation platform driver >> fpga: xrt: Kconfig and Makefile updates for XRT drivers >> >> Documentation/fpga/index.rst | 1 + >> Documentation/fpga/xrt.rst | 842 ++++++++++++++++++++++ >> MAINTAINERS | 11 + >> drivers/Makefile | 1 + >> drivers/fpga/Kconfig | 2 + >> drivers/fpga/Makefile | 4 + >> drivers/fpga/xrt/Kconfig | 8 + >> drivers/fpga/xrt/include/events.h | 48 ++ >> drivers/fpga/xrt/include/group.h | 27 + >> drivers/fpga/xrt/include/metadata.h | 229 ++++++ >> drivers/fpga/xrt/include/subdev_id.h | 43 ++ >> drivers/fpga/xrt/include/xclbin-helper.h | 52 ++ >> drivers/fpga/xrt/include/xleaf.h | 276 +++++++ >> drivers/fpga/xrt/include/xleaf/axigate.h | 25 + >> drivers/fpga/xrt/include/xleaf/calib.h | 30 + >> drivers/fpga/xrt/include/xleaf/clkfreq.h | 23 + >> drivers/fpga/xrt/include/xleaf/clock.h | 31 + >> drivers/fpga/xrt/include/xleaf/devctl.h | 43 ++ >> drivers/fpga/xrt/include/xleaf/icap.h | 29 + >> drivers/fpga/xrt/include/xleaf/ucs.h | 24 + >> drivers/fpga/xrt/include/xmgmt-main.h | 37 + >> drivers/fpga/xrt/include/xroot.h | 114 +++ >> drivers/fpga/xrt/lib/Kconfig | 16 + >> drivers/fpga/xrt/lib/Makefile | 30 + >> drivers/fpga/xrt/lib/cdev.c | 231 ++++++ >> drivers/fpga/xrt/lib/group.c | 265 +++++++ >> drivers/fpga/xrt/lib/main.c | 274 +++++++ >> drivers/fpga/xrt/lib/main.h | 17 + >> drivers/fpga/xrt/lib/subdev.c | 871 +++++++++++++++++++++++ >> drivers/fpga/xrt/lib/subdev_pool.h | 53 ++ >> drivers/fpga/xrt/lib/xclbin.c | 394 ++++++++++ >> drivers/fpga/xrt/lib/xleaf/axigate.c | 298 ++++++++ >> drivers/fpga/xrt/lib/xleaf/calib.c | 226 ++++++ >> drivers/fpga/xrt/lib/xleaf/clkfreq.c | 221 ++++++ >> drivers/fpga/xrt/lib/xleaf/clock.c | 648 +++++++++++++++++ >> drivers/fpga/xrt/lib/xleaf/devctl.c | 206 ++++++ >> drivers/fpga/xrt/lib/xleaf/icap.c | 317 +++++++++ >> drivers/fpga/xrt/lib/xleaf/ucs.c | 235 ++++++ >> drivers/fpga/xrt/lib/xleaf/vsec.c | 359 ++++++++++ >> drivers/fpga/xrt/lib/xroot.c | 598 ++++++++++++++++ >> drivers/fpga/xrt/metadata/Kconfig | 12 + >> drivers/fpga/xrt/metadata/Makefile | 16 + >> drivers/fpga/xrt/metadata/metadata.c | 524 ++++++++++++++ >> drivers/fpga/xrt/mgmt/Kconfig | 15 + >> drivers/fpga/xrt/mgmt/Makefile | 19 + >> drivers/fpga/xrt/mgmt/fmgr-drv.c | 187 +++++ >> drivers/fpga/xrt/mgmt/fmgr.h | 28 + >> drivers/fpga/xrt/mgmt/main-impl.h | 37 + >> drivers/fpga/xrt/mgmt/main-region.c | 471 ++++++++++++ >> drivers/fpga/xrt/mgmt/main.c | 693 ++++++++++++++++++ >> drivers/fpga/xrt/mgmt/root.c | 342 +++++++++ >> include/uapi/linux/xrt/xclbin.h | 408 +++++++++++ >> include/uapi/linux/xrt/xmgmt-ioctl.h | 46 ++ >> 53 files changed, 9957 insertions(+) >> create mode 100644 Documentation/fpga/xrt.rst >> create mode 100644 drivers/fpga/xrt/Kconfig >> create mode 100644 drivers/fpga/xrt/include/events.h >> create mode 100644 drivers/fpga/xrt/include/group.h >> create mode 100644 drivers/fpga/xrt/include/metadata.h >> create mode 100644 drivers/fpga/xrt/include/subdev_id.h >> create mode 100644 drivers/fpga/xrt/include/xclbin-helper.h >> create mode 100644 drivers/fpga/xrt/include/xleaf.h >> create mode 100644 drivers/fpga/xrt/include/xleaf/axigate.h >> create mode 100644 drivers/fpga/xrt/include/xleaf/calib.h >> create mode 100644 drivers/fpga/xrt/include/xleaf/clkfreq.h >> create mode 100644 drivers/fpga/xrt/include/xleaf/clock.h >> create mode 100644 drivers/fpga/xrt/include/xleaf/devctl.h >> create mode 100644 drivers/fpga/xrt/include/xleaf/icap.h >> create mode 100644 drivers/fpga/xrt/include/xleaf/ucs.h >> create mode 100644 drivers/fpga/xrt/include/xmgmt-main.h >> create mode 100644 drivers/fpga/xrt/include/xroot.h >> create mode 100644 drivers/fpga/xrt/lib/Kconfig >> create mode 100644 drivers/fpga/xrt/lib/Makefile >> create mode 100644 drivers/fpga/xrt/lib/cdev.c >> create mode 100644 drivers/fpga/xrt/lib/group.c >> create mode 100644 drivers/fpga/xrt/lib/main.c >> create mode 100644 drivers/fpga/xrt/lib/main.h >> create mode 100644 drivers/fpga/xrt/lib/subdev.c >> create mode 100644 drivers/fpga/xrt/lib/subdev_pool.h >> create mode 100644 drivers/fpga/xrt/lib/xclbin.c >> create mode 100644 drivers/fpga/xrt/lib/xleaf/axigate.c >> create mode 100644 drivers/fpga/xrt/lib/xleaf/calib.c >> create mode 100644 drivers/fpga/xrt/lib/xleaf/clkfreq.c >> create mode 100644 drivers/fpga/xrt/lib/xleaf/clock.c >> create mode 100644 drivers/fpga/xrt/lib/xleaf/devctl.c >> create mode 100644 drivers/fpga/xrt/lib/xleaf/icap.c >> create mode 100644 drivers/fpga/xrt/lib/xleaf/ucs.c >> create mode 100644 drivers/fpga/xrt/lib/xleaf/vsec.c >> create mode 100644 drivers/fpga/xrt/lib/xroot.c >> create mode 100644 drivers/fpga/xrt/metadata/Kconfig >> create mode 100644 drivers/fpga/xrt/metadata/Makefile >> create mode 100644 drivers/fpga/xrt/metadata/metadata.c >> create mode 100644 drivers/fpga/xrt/mgmt/Kconfig >> create mode 100644 drivers/fpga/xrt/mgmt/Makefile >> create mode 100644 drivers/fpga/xrt/mgmt/fmgr-drv.c >> create mode 100644 drivers/fpga/xrt/mgmt/fmgr.h >> create mode 100644 drivers/fpga/xrt/mgmt/main-impl.h >> create mode 100644 drivers/fpga/xrt/mgmt/main-region.c >> create mode 100644 drivers/fpga/xrt/mgmt/main.c >> create mode 100644 drivers/fpga/xrt/mgmt/root.c >> create mode 100644 include/uapi/linux/xrt/xclbin.h >> create mode 100644 include/uapi/linux/xrt/xmgmt-ioctl.h >> >> -- >> 2.18.4 >> > Please fix the indents all across this patchset. Doesn't checkpatch with > --strict complain about this? checkpatch --strict did not complain. And we will fix this. > > Also more generally this looks like it should be a bus. Look at DFL for > reference. Tom asked the same question in 01/18 and Sonal replied. We may discuss with that thread. Thanks, Lizhi > > - Moritz
On 2/17/21 10:40 PM, Lizhi Hou wrote: > Add VSEC driver. VSEC is a hardware function discovered by walking > PCI Express configure space. A platform device node will be created > for it. VSEC provides board logic UUID and few offset of other hardware > functions. Is this vsec walking infra or is a general find a list of mmio regions that need to be mapped in and do the mapping in as a set of platform drivers ? > Signed-off-by: Sonal Santan <sonal.santan@xilinx.com> > Signed-off-by: Max Zhen <max.zhen@xilinx.com> > Signed-off-by: Lizhi Hou <lizhih@xilinx.com> > --- > drivers/fpga/xrt/lib/xleaf/vsec.c | 359 ++++++++++++++++++++++++++++++ > 1 file changed, 359 insertions(+) > create mode 100644 drivers/fpga/xrt/lib/xleaf/vsec.c > > diff --git a/drivers/fpga/xrt/lib/xleaf/vsec.c b/drivers/fpga/xrt/lib/xleaf/vsec.c > new file mode 100644 > index 000000000000..8e5cb22522ec > --- /dev/null > +++ b/drivers/fpga/xrt/lib/xleaf/vsec.c > @@ -0,0 +1,359 @@ > +// SPDX-License-Identifier: GPL-2.0 > +/* > + * Xilinx Alveo FPGA VSEC Driver > + * > + * Copyright (C) 2020-2021 Xilinx, Inc. > + * > + * Authors: > + * Lizhi Hou<Lizhi.Hou@xilinx.com> > + */ > + > +#include <linux/platform_device.h> > +#include "metadata.h" > +#include "xleaf.h" > + > +#define XRT_VSEC "xrt_vsec" > + > +#define VSEC_TYPE_UUID 0x50 > +#define VSEC_TYPE_FLASH 0x51 > +#define VSEC_TYPE_PLATINFO 0x52 > +#define VSEC_TYPE_MAILBOX 0x53 > +#define VSEC_TYPE_END 0xff Type of devices, this list can not grow much. > + > +#define VSEC_UUID_LEN 16 > + > +struct xrt_vsec_header { > + u32 format; > + u32 length; > + u32 entry_sz; > + u32 rsvd; > +} __packed; > + > +#define head_rd(g, r) \ > + ioread32((void *)(g)->base + offsetof(struct xrt_vsec_header, r)) > + > +#define GET_BAR(entry) (((entry)->bar_rev >> 4) & 0xf) > +#define GET_BAR_OFF(_entry) \ > + ({ typeof(_entry) entry = (_entry); \ > + ((entry)->off_lo | ((u64)(entry)->off_hi << 16)); }) A 48 bit value stored in xrt_md_endpoint.bar_off (long) bar_off should be u64 > +#define GET_REV(entry) ((entry)->bar_rev & 0xf) > + I prefer functions over macros. > +struct xrt_vsec_entry { > + u8 type; > + u8 bar_rev; > + u16 off_lo; > + u32 off_hi; > + u8 ver_type; > + u8 minor; > + u8 major; > + u8 rsvd0; > + u32 rsvd1; > +} __packed; > + > +#define read_entry(g, i, e) \ > + do { \ > + u32 *p = (u32 *)((g)->base + \ > + sizeof(struct xrt_vsec_header) + \ > + (i) * sizeof(struct xrt_vsec_entry)); \ > + u32 off; \ > + for (off = 0; \ > + off < sizeof(struct xrt_vsec_entry) / 4; \ > + off++) \ > + *((u32 *)(e) + off) = ioread32(p + off);\ > + } while (0) This could be a static inline func. > + > +struct vsec_device { > + u8 type; > + char *ep_name; > + ulong size; > + char *regmap; > +}; > + > +static struct vsec_device vsec_devs[] = { > + { > + .type = VSEC_TYPE_UUID, > + .ep_name = XRT_MD_NODE_BLP_ROM, > + .size = VSEC_UUID_LEN, > + .regmap = "vsec-uuid", > + }, > + { > + .type = VSEC_TYPE_FLASH, > + .ep_name = XRT_MD_NODE_FLASH_VSEC, > + .size = 4096, > + .regmap = "vsec-flash", > + }, > + { > + .type = VSEC_TYPE_PLATINFO, > + .ep_name = XRT_MD_NODE_PLAT_INFO, > + .size = 4, > + .regmap = "vsec-platinfo", > + }, > + { > + .type = VSEC_TYPE_MAILBOX, > + .ep_name = XRT_MD_NODE_MAILBOX_VSEC, > + .size = 48, > + .regmap = "vsec-mbx", > + }, This is a static list, how would a new type be added to this ? > +}; > + > +struct xrt_vsec { > + struct platform_device *pdev; > + void *base; > + ulong length; > + > + char *metadata; > + char uuid[VSEC_UUID_LEN]; > +}; > + > +static char *type2epname(u32 type) > +{ > + int i; > + > + for (i = 0; i < ARRAY_SIZE(vsec_devs); i++) { > + if (vsec_devs[i].type == type) > + return (vsec_devs[i].ep_name); > + } > + > + return NULL; > +} > + > +static ulong type2size(u32 type) > +{ > + int i; > + > + for (i = 0; i < ARRAY_SIZE(vsec_devs); i++) { > + if (vsec_devs[i].type == type) > + return (vsec_devs[i].size); > + } > + > + return 0; > +} > + > +static char *type2regmap(u32 type) > +{ > + int i; > + > + for (i = 0; i < ARRAY_SIZE(vsec_devs); i++) { > + if (vsec_devs[i].type == type) > + return (vsec_devs[i].regmap); > + } > + > + return NULL; > +} > + > +static int xrt_vsec_add_node(struct xrt_vsec *vsec, > + void *md_blob, struct xrt_vsec_entry *p_entry) > +{ > + struct xrt_md_endpoint ep; > + char regmap_ver[64]; > + int ret; > + > + if (!type2epname(p_entry->type)) > + return -EINVAL; > + > + /* > + * VSEC may have more than 1 mailbox instance for the card > + * which has more than 1 physical function. > + * This is not supported for now. Assuming only one mailbox > + */ are multiple uuid types allowed ? this says assume 1, but logic will recreate 1+ can you check if a mbx ep exists before creating ? > + > + snprintf(regmap_ver, sizeof(regmap_ver) - 1, "%d-%d.%d.%d", > + p_entry->ver_type, p_entry->major, p_entry->minor, > + GET_REV(p_entry)); > + ep.ep_name = type2epname(p_entry->type); > + ep.bar = GET_BAR(p_entry); > + ep.bar_off = GET_BAR_OFF(p_entry); here is the bar_off type overlow > + ep.size = type2size(p_entry->type); > + ep.regmap = type2regmap(p_entry->type); > + ep.regmap_ver = regmap_ver; > + ret = xrt_md_add_endpoint(DEV(vsec->pdev), vsec->metadata, &ep); > + if (ret) { > + xrt_err(vsec->pdev, "add ep failed, ret %d", ret); > + goto failed; > + } > + > +failed: > + return ret; > +} > + > +static int xrt_vsec_create_metadata(struct xrt_vsec *vsec) > +{ > + struct xrt_vsec_entry entry; > + int i, ret; > + > + ret = xrt_md_create(&vsec->pdev->dev, &vsec->metadata); > + if (ret) { > + xrt_err(vsec->pdev, "create metadata failed"); > + return ret; > + } > + > + for (i = 0; i * sizeof(entry) < vsec->length - > + sizeof(struct xrt_vsec_header); i++) { > + read_entry(vsec, i, &entry); > + xrt_vsec_add_node(vsec, vsec->metadata, &entry); This can fail. > + } > + > + return 0; > +} > + > +static int xrt_vsec_ioctl(struct platform_device *pdev, u32 cmd, void *arg) > +{ > + int ret = 0; > + > + switch (cmd) { > + case XRT_XLEAF_EVENT: > + /* Does not handle any event. */ > + break; > + default: > + ret = -EINVAL; > + xrt_err(pdev, "should never been called"); > + break; > + } This function looks like a noop. Is anything going to be added to this later ? > + > + return ret; > +} > + > +static int xrt_vsec_mapio(struct xrt_vsec *vsec) > +{ > + struct xrt_subdev_platdata *pdata = DEV_PDATA(vsec->pdev); > + const u32 *bar; > + const u64 *bar_off; > + struct resource *res = NULL; > + ulong addr; > + int ret; > + > + if (!pdata || xrt_md_size(DEV(vsec->pdev), pdata->xsp_dtb) == XRT_MD_INVALID_LENGTH) { > + xrt_err(vsec->pdev, "empty metadata"); > + return -EINVAL; > + } > + > + ret = xrt_md_get_prop(DEV(vsec->pdev), pdata->xsp_dtb, XRT_MD_NODE_VSEC, > + NULL, XRT_MD_PROP_BAR_IDX, (const void **)&bar, NULL); > + if (ret) { > + xrt_err(vsec->pdev, "failed to get bar idx, ret %d", ret); > + return -EINVAL; > + } > + > + ret = xrt_md_get_prop(DEV(vsec->pdev), pdata->xsp_dtb, XRT_MD_NODE_VSEC, > + NULL, XRT_MD_PROP_OFFSET, (const void **)&bar_off, NULL); > + if (ret) { > + xrt_err(vsec->pdev, "failed to get bar off, ret %d", ret); > + return -EINVAL; > + } > + > + xrt_info(vsec->pdev, "Map vsec at bar %d, offset 0x%llx", > + be32_to_cpu(*bar), be64_to_cpu(*bar_off)); > + > + xleaf_get_barres(vsec->pdev, &res, be32_to_cpu(*bar)); > + if (!res) { > + xrt_err(vsec->pdev, "failed to get bar addr"); > + return -EINVAL; > + } > + > + addr = res->start + (ulong)be64_to_cpu(*bar_off); review this type, addr is ulong and bar_off is not. > + > + vsec->base = ioremap(addr, sizeof(struct xrt_vsec_header)); > + if (!vsec->base) { > + xrt_err(vsec->pdev, "Map header failed"); > + return -EIO; > + } why the double call on ioremap ? just do the last one. > + > + vsec->length = head_rd(vsec, length); > + iounmap(vsec->base); > + vsec->base = ioremap(addr, vsec->length); > + if (!vsec->base) { > + xrt_err(vsec->pdev, "map failed"); > + return -EIO; > + } > + > + return 0; > +} > + > +static int xrt_vsec_remove(struct platform_device *pdev) > +{ > + struct xrt_vsec *vsec; > + > + vsec = platform_get_drvdata(pdev); > + > + if (vsec->base) { > + iounmap(vsec->base); > + vsec->base = NULL; > + } > + > + vfree(vsec->metadata); > + > + return 0; > +} > + > +static int xrt_vsec_probe(struct platform_device *pdev) > +{ > + struct xrt_vsec *vsec; > + int ret = 0; > + > + vsec = devm_kzalloc(&pdev->dev, sizeof(*vsec), GFP_KERNEL); > + if (!vsec) > + return -ENOMEM; > + > + vsec->pdev = pdev; > + platform_set_drvdata(pdev, vsec); > + > + ret = xrt_vsec_mapio(vsec); > + if (ret) > + goto failed; > + > + ret = xrt_vsec_create_metadata(vsec); > + if (ret) { > + xrt_err(pdev, "create metadata failed, ret %d", ret); > + goto failed; > + } > + ret = xleaf_create_group(pdev, vsec->metadata); > + if (ret < 0) > + xrt_err(pdev, "create group failed, ret %d", ret); > + else > + ret = 0; why is it just if (ret) fail ? Tom > + > +failed: > + if (ret) > + xrt_vsec_remove(pdev); > + > + return ret; > +} > + > +static struct xrt_subdev_endpoints xrt_vsec_endpoints[] = { > + { > + .xse_names = (struct xrt_subdev_ep_names []){ > + { .ep_name = XRT_MD_NODE_VSEC }, > + { NULL }, > + }, > + .xse_min_ep = 1, > + }, > + { 0 }, > +}; > + > +static struct xrt_subdev_drvdata xrt_vsec_data = { > + .xsd_dev_ops = { > + .xsd_ioctl = xrt_vsec_ioctl, > + }, > +}; > + > +static const struct platform_device_id xrt_vsec_table[] = { > + { XRT_VSEC, (kernel_ulong_t)&xrt_vsec_data }, > + { }, > +}; > + > +static struct platform_driver xrt_vsec_driver = { > + .driver = { > + .name = XRT_VSEC, > + }, > + .probe = xrt_vsec_probe, > + .remove = xrt_vsec_remove, > + .id_table = xrt_vsec_table, > +}; > + > +void vsec_leaf_init_fini(bool init) > +{ > + if (init) > + xleaf_register_driver(XRT_SUBDEV_VSEC, &xrt_vsec_driver, xrt_vsec_endpoints); > + else > + xleaf_unregister_driver(XRT_SUBDEV_VSEC); > +}
Hi Tom， On 02/28/2021 08:54 AM, Tom Rix wrote: > CAUTION: This message has originated from an External Source. Please use proper judgment and caution when opening attachments, clicking links, or responding to this email. > > > On 2/26/21 1:23 PM, Lizhi Hou wrote: >> Hi Tom, >> >> > snip > >>> I also do not see a pragma pack, usually this is set of 1 so the compiler does not shuffle elements, increase size etc. >> This data structure is shared with other tools. And the structure is well defined with reasonable alignment. It is compatible with all compilers we have tested. So pragma pack is not necessary. > You can not have possibly tested all the configurations since the kernel supports many arches and compilers. > > If the tested existing alignment is ok, pragma pack should be a noop on your tested configurations. > > And help cover the untested configurations. Got it. I will add pragma pack(1). Lizhi > > Tom >
On Mon, Mar 01, 2021 at 04:25:37PM -0800, Lizhi Hou wrote: > Hi Tom， > > > On 02/28/2021 08:54 AM, Tom Rix wrote: > > CAUTION: This message has originated from an External Source. Please use proper judgment and caution when opening attachments, clicking links, or responding to this email. > > > > > > On 2/26/21 1:23 PM, Lizhi Hou wrote: > > > Hi Tom, > > > > > > > > snip > > > > > > I also do not see a pragma pack, usually this is set of 1 so the compiler does not shuffle elements, increase size etc. > > > This data structure is shared with other tools. And the structure is well defined with reasonable alignment. It is compatible with all compilers we have tested. So pragma pack is not necessary. > > You can not have possibly tested all the configurations since the kernel supports many arches and compilers. > > > > If the tested existing alignment is ok, pragma pack should be a noop on your tested configurations. > > > > And help cover the untested configurations. > Got it. I will add pragma pack(1). Please do not use pragma pack(), add __packed to the structs in question. - Moritz
On 2/17/21 10:40 PM, Lizhi Hou wrote: > Add UCS driver. UCS is a hardware function discovered by walking xclbin What does UCS stand for ? add to commit log > metadata. A platform device node will be created for it. > UCS enables/disables the dynamic region clocks. > > Signed-off-by: Sonal Santan <sonal.santan@xilinx.com> > Signed-off-by: Max Zhen <max.zhen@xilinx.com> > Signed-off-by: Lizhi Hou <lizhih@xilinx.com> > --- > drivers/fpga/xrt/include/xleaf/ucs.h | 24 +++ > drivers/fpga/xrt/lib/xleaf/ucs.c | 235 +++++++++++++++++++++++++++ > 2 files changed, 259 insertions(+) > create mode 100644 drivers/fpga/xrt/include/xleaf/ucs.h > create mode 100644 drivers/fpga/xrt/lib/xleaf/ucs.c > > diff --git a/drivers/fpga/xrt/include/xleaf/ucs.h b/drivers/fpga/xrt/include/xleaf/ucs.h > new file mode 100644 > index 000000000000..a5ef0e100e12 > --- /dev/null > +++ b/drivers/fpga/xrt/include/xleaf/ucs.h This header is only used by ucs.c, so is it needed ? could the enum be defined in ucs.c ? > @@ -0,0 +1,24 @@ > +/* SPDX-License-Identifier: GPL-2.0 */ > +/* > + * Header file for XRT UCS Leaf Driver > + * > + * Copyright (C) 2020-2021 Xilinx, Inc. > + * > + * Authors: > + * Lizhi Hou <Lizhi.Hou@xilinx.com> > + */ > + > +#ifndef _XRT_UCS_H_ > +#define _XRT_UCS_H_ > + > +#include "xleaf.h" > + > +/* > + * UCS driver IOCTL calls. > + */ > +enum xrt_ucs_ioctl_cmd { > + XRT_UCS_CHECK = XRT_XLEAF_CUSTOM_BASE, /* See comments in xleaf.h */ > + XRT_UCS_ENABLE, no disable ? > +}; > + > +#endif /* _XRT_UCS_H_ */ > diff --git a/drivers/fpga/xrt/lib/xleaf/ucs.c b/drivers/fpga/xrt/lib/xleaf/ucs.c > new file mode 100644 > index 000000000000..ae762c8fddbb > --- /dev/null > +++ b/drivers/fpga/xrt/lib/xleaf/ucs.c > @@ -0,0 +1,235 @@ > +// SPDX-License-Identifier: GPL-2.0 > +/* > + * Xilinx Alveo FPGA UCS Driver > + * > + * Copyright (C) 2020-2021 Xilinx, Inc. > + * > + * Authors: > + * Lizhi Hou<Lizhi.Hou@xilinx.com> > + */ > + > +#include <linux/mod_devicetable.h> > +#include <linux/platform_device.h> > +#include <linux/delay.h> > +#include <linux/device.h> > +#include <linux/io.h> > +#include "metadata.h" > +#include "xleaf.h" > +#include "xleaf/ucs.h" > +#include "xleaf/clock.h" > + > +#define UCS_ERR(ucs, fmt, arg...) \ > + xrt_err((ucs)->pdev, fmt "\n", ##arg) > +#define UCS_WARN(ucs, fmt, arg...) \ > + xrt_warn((ucs)->pdev, fmt "\n", ##arg) > +#define UCS_INFO(ucs, fmt, arg...) \ > + xrt_info((ucs)->pdev, fmt "\n", ##arg) > +#define UCS_DBG(ucs, fmt, arg...) \ > + xrt_dbg((ucs)->pdev, fmt "\n", ##arg) > + > +#define XRT_UCS "xrt_ucs" > + > +#define CHANNEL1_OFFSET 0 > +#define CHANNEL2_OFFSET 8 > + > +#define CLK_MAX_VALUE 6400 > + > +struct ucs_control_status_ch1 { > + unsigned int shutdown_clocks_latched:1; > + unsigned int reserved1:15; > + unsigned int clock_throttling_average:14; > + unsigned int reserved2:2; > +}; Likely needs to be packed and/or the unsigned int changed to u32 > + > +struct xrt_ucs { > + struct platform_device *pdev; > + void __iomem *ucs_base; > + struct mutex ucs_lock; /* ucs dev lock */ > +}; > + > +static inline u32 reg_rd(struct xrt_ucs *ucs, u32 offset) > +{ > + return ioread32(ucs->ucs_base + offset); > +} > + > +static inline void reg_wr(struct xrt_ucs *ucs, u32 val, u32 offset) > +{ > + iowrite32(val, ucs->ucs_base + offset); > +} > + > +static void xrt_ucs_event_cb(struct platform_device *pdev, void *arg) > +{ > + struct platform_device *leaf; > + struct xrt_event *evt = (struct xrt_event *)arg; > + enum xrt_events e = evt->xe_evt; > + enum xrt_subdev_id id = evt->xe_subdev.xevt_subdev_id; > + int instance = evt->xe_subdev.xevt_subdev_instance; > + > + switch (e) { > + case XRT_EVENT_POST_CREATION: > + break; > + default: > + xrt_dbg(pdev, "ignored event %d", e); > + return; > + } this switch is a noop, remove > + > + if (id != XRT_SUBDEV_CLOCK) > + return; > + > + leaf = xleaf_get_leaf_by_id(pdev, XRT_SUBDEV_CLOCK, instance); > + if (!leaf) { > + xrt_err(pdev, "does not get clock subdev"); > + return; > + } > + > + xleaf_ioctl(leaf, XRT_CLOCK_VERIFY, NULL); > + xleaf_put_leaf(pdev, leaf); > +} > + > +static void ucs_check(struct xrt_ucs *ucs, bool *latched) > +{ checking but not returning status, change to returning int. this function is called but xrt_ucs_leaf_ioctl which does return status. > + struct ucs_control_status_ch1 *ucs_status_ch1; > + u32 status; > + > + mutex_lock(&ucs->ucs_lock); > + status = reg_rd(ucs, CHANNEL1_OFFSET); > + ucs_status_ch1 = (struct ucs_control_status_ch1 *)&status; > + if (ucs_status_ch1->shutdown_clocks_latched) { > + UCS_ERR(ucs, > + "Critical temperature or power event, kernel clocks have been stopped."); > + UCS_ERR(ucs, > + "run 'xbutil valiate -q' to continue. See AR 73398 for more details."); This error message does not seem like it would be useful, please review. > + /* explicitly indicate reset should be latched */ > + *latched = true; > + } else if (ucs_status_ch1->clock_throttling_average > > + CLK_MAX_VALUE) { > + UCS_ERR(ucs, "kernel clocks %d exceeds expected maximum value %d.", > + ucs_status_ch1->clock_throttling_average, > + CLK_MAX_VALUE); > + } else if (ucs_status_ch1->clock_throttling_average) { > + UCS_ERR(ucs, "kernel clocks throttled at %d%%.", > + (ucs_status_ch1->clock_throttling_average / > + (CLK_MAX_VALUE / 100))); > + } > + mutex_unlock(&ucs->ucs_lock); > +} > + > +static void ucs_enable(struct xrt_ucs *ucs) > +{ > + reg_wr(ucs, 1, CHANNEL2_OFFSET); lock ? > +} > + > +static int > +xrt_ucs_leaf_ioctl(struct platform_device *pdev, u32 cmd, void *arg) > +{ > + struct xrt_ucs *ucs; > + int ret = 0; > + > + ucs = platform_get_drvdata(pdev); > + > + switch (cmd) { > + case XRT_XLEAF_EVENT: > + xrt_ucs_event_cb(pdev, arg); > + break; > + case XRT_UCS_CHECK: { brace not needed here > + ucs_check(ucs, (bool *)arg); > + break; > + } > + case XRT_UCS_ENABLE: > + ucs_enable(ucs); > + break; > + default: > + xrt_err(pdev, "unsupported cmd %d", cmd); > + return -EINVAL; > + } > + > + return ret; > +} > + > +static int ucs_remove(struct platform_device *pdev) > +{ > + struct xrt_ucs *ucs; > + > + ucs = platform_get_drvdata(pdev); > + if (!ucs) { is this possible ? Tom > + xrt_err(pdev, "driver data is NULL"); > + return -EINVAL; > + } > + > + if (ucs->ucs_base) > + iounmap(ucs->ucs_base); > + > + platform_set_drvdata(pdev, NULL); > + devm_kfree(&pdev->dev, ucs); > + > + return 0; > +} > + > +static int ucs_probe(struct platform_device *pdev) > +{ > + struct xrt_ucs *ucs = NULL; > + struct resource *res; > + int ret; > + > + ucs = devm_kzalloc(&pdev->dev, sizeof(*ucs), GFP_KERNEL); > + if (!ucs) > + return -ENOMEM; > + > + platform_set_drvdata(pdev, ucs); > + ucs->pdev = pdev; > + mutex_init(&ucs->ucs_lock); > + > + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); > + ucs->ucs_base = ioremap(res->start, res->end - res->start + 1); > + if (!ucs->ucs_base) { > + UCS_ERR(ucs, "map base %pR failed", res); > + ret = -EFAULT; > + goto failed; > + } > + ucs_enable(ucs); > + > + return 0; > + > +failed: > + ucs_remove(pdev); > + return ret; > +} > + > +static struct xrt_subdev_endpoints xrt_ucs_endpoints[] = { > + { > + .xse_names = (struct xrt_subdev_ep_names[]) { > + { .ep_name = XRT_MD_NODE_UCS_CONTROL_STATUS }, > + { NULL }, > + }, > + .xse_min_ep = 1, > + }, > + { 0 }, > +}; > + > +static struct xrt_subdev_drvdata xrt_ucs_data = { > + .xsd_dev_ops = { > + .xsd_ioctl = xrt_ucs_leaf_ioctl, > + }, > +}; > + > +static const struct platform_device_id xrt_ucs_table[] = { > + { XRT_UCS, (kernel_ulong_t)&xrt_ucs_data }, > + { }, > +}; > + > +static struct platform_driver xrt_ucs_driver = { > + .driver = { > + .name = XRT_UCS, > + }, > + .probe = ucs_probe, > + .remove = ucs_remove, > + .id_table = xrt_ucs_table, > +}; > + > +void ucs_leaf_init_fini(bool init) > +{ > + if (init) > + xleaf_register_driver(XRT_SUBDEV_UCS, &xrt_ucs_driver, xrt_ucs_endpoints); > + else > + xleaf_unregister_driver(XRT_SUBDEV_UCS); > +}
Hi Moritz, On 02/21/2021 12:24 PM, Moritz Fischer wrote: > On Wed, Feb 17, 2021 at 10:40:13PM -0800, Lizhi Hou wrote: >> Add ICAP driver. ICAP is a hardware function discovered by walking >> firmware metadata. A platform device node will be created for it. >> FPGA bitstream is written to hardware through ICAP. >> >> Signed-off-by: Sonal Santan <sonal.santan@xilinx.com> >> Signed-off-by: Max Zhen <max.zhen@xilinx.com> >> Signed-off-by: Lizhi Hou <lizhih@xilinx.com> >> --- >> drivers/fpga/xrt/include/xleaf/icap.h | 29 +++ >> drivers/fpga/xrt/lib/xleaf/icap.c | 317 ++++++++++++++++++++++++++ >> 2 files changed, 346 insertions(+) >> create mode 100644 drivers/fpga/xrt/include/xleaf/icap.h >> create mode 100644 drivers/fpga/xrt/lib/xleaf/icap.c >> >> diff --git a/drivers/fpga/xrt/include/xleaf/icap.h b/drivers/fpga/xrt/include/xleaf/icap.h >> new file mode 100644 >> index 000000000000..a14fc0ffa78f >> --- /dev/null >> +++ b/drivers/fpga/xrt/include/xleaf/icap.h >> @@ -0,0 +1,29 @@ >> +/* SPDX-License-Identifier: GPL-2.0 */ >> +/* >> + * Header file for XRT ICAP Leaf Driver >> + * >> + * Copyright (C) 2020-2021 Xilinx, Inc. >> + * >> + * Authors: >> + * Lizhi Hou <Lizhi.Hou@xilinx.com> >> + */ >> + >> +#ifndef _XRT_ICAP_H_ >> +#define _XRT_ICAP_H_ >> + >> +#include "xleaf.h" >> + >> +/* >> + * ICAP driver IOCTL calls. >> + */ >> +enum xrt_icap_ioctl_cmd { >> + XRT_ICAP_WRITE = XRT_XLEAF_CUSTOM_BASE, /* See comments in xleaf.h */ >> + XRT_ICAP_IDCODE, >> +}; >> + >> +struct xrt_icap_ioctl_wr { >> + void *xiiw_bit_data; >> + u32 xiiw_data_len; >> +}; >> + >> +#endif /* _XRT_ICAP_H_ */ >> diff --git a/drivers/fpga/xrt/lib/xleaf/icap.c b/drivers/fpga/xrt/lib/xleaf/icap.c >> new file mode 100644 >> index 000000000000..0500a97bdef9 >> --- /dev/null >> +++ b/drivers/fpga/xrt/lib/xleaf/icap.c >> @@ -0,0 +1,317 @@ >> +// SPDX-License-Identifier: GPL-2.0 >> +/* >> + * Xilinx Alveo FPGA ICAP Driver >> + * >> + * Copyright (C) 2020-2021 Xilinx, Inc. >> + * >> + * Authors: >> + * Lizhi Hou<Lizhi.Hou@xilinx.com> >> + * Sonal Santan <sonals@xilinx.com> >> + * Max Zhen <maxz@xilinx.com> >> + */ >> + >> +#include <linux/mod_devicetable.h> >> +#include <linux/platform_device.h> >> +#include <linux/delay.h> >> +#include <linux/device.h> >> +#include <linux/io.h> >> +#include "metadata.h" >> +#include "xleaf.h" >> +#include "xleaf/icap.h" >> +#include "xclbin-helper.h" >> + >> +#define XRT_ICAP "xrt_icap" >> + >> +#define ICAP_ERR(icap, fmt, arg...) \ >> + xrt_err((icap)->pdev, fmt "\n", ##arg) >> +#define ICAP_WARN(icap, fmt, arg...) \ >> + xrt_warn((icap)->pdev, fmt "\n", ##arg) >> +#define ICAP_INFO(icap, fmt, arg...) \ >> + xrt_info((icap)->pdev, fmt "\n", ##arg) >> +#define ICAP_DBG(icap, fmt, arg...) \ >> + xrt_dbg((icap)->pdev, fmt "\n", ##arg) > Do we really need two layers of indirection here? What's wrong with > dev_{info,dbg,...} ? In case that we would change the massage 'fmt' in the future we can change it at one place. And it does not expose any interface or introduce performance issue. Could we just keep these Macros? >> + >> +/* >> + * AXI-HWICAP IP register layout >> + */ >> +struct icap_reg { >> + u32 ir_rsvd1[7]; >> + u32 ir_gier; >> + u32 ir_isr; >> + u32 ir_rsvd2; >> + u32 ir_ier; >> + u32 ir_rsvd3[53]; >> + u32 ir_wf; >> + u32 ir_rf; >> + u32 ir_sz; >> + u32 ir_cr; >> + u32 ir_sr; >> + u32 ir_wfv; >> + u32 ir_rfo; >> + u32 ir_asr; >> +} __packed; > Can we make those #define and just use writel/readl() ? If you want more > abstraction, use regmap.... Sure, we will use #define as below and use writel/readl to access them. #define ICAP_REG_ISR(base) ((base) + 0x20) .... >> + >> +struct icap { >> + struct platform_device *pdev; >> + struct icap_reg *icap_regs; >> + struct mutex icap_lock; /* icap dev lock */ >> + >> + unsigned int idcode; >> +}; >> + >> +static inline u32 reg_rd(void __iomem *reg) >> +{ >> + if (!reg) >> + return -1; >> + >> + return ioread32(reg); >> +} >> + >> +static inline void reg_wr(void __iomem *reg, u32 val) >> +{ >> + if (!reg) >> + return; >> + >> + iowrite32(val, reg); >> +} >> + >> +static int wait_for_done(struct icap *icap) >> +{ >> + u32 w; >> + int i = 0; >> + >> + WARN_ON(!mutex_is_locked(&icap->icap_lock)); >> + for (i = 0; i < 10; i++) { >> + udelay(5); >> + w = reg_rd(&icap->icap_regs->ir_sr); >> + ICAP_INFO(icap, "XHWICAP_SR: %x", w); >> + if (w & 0x5) >> + return 0; >> + } >> + >> + ICAP_ERR(icap, "bitstream download timeout"); >> + return -ETIMEDOUT; >> +} >> + >> +static int icap_write(struct icap *icap, const u32 *word_buf, int size) >> +{ >> + int i; >> + u32 value = 0; >> + >> + for (i = 0; i < size; i++) { >> + value = be32_to_cpu(word_buf[i]); >> + reg_wr(&icap->icap_regs->ir_wf, value); >> + } >> + >> + reg_wr(&icap->icap_regs->ir_cr, 0x1); >> + >> + for (i = 0; i < 20; i++) { >> + value = reg_rd(&icap->icap_regs->ir_cr); >> + if ((value & 0x1) == 0) >> + return 0; >> + ndelay(50); >> + } >> + >> + ICAP_ERR(icap, "writing %d dwords timeout", size); >> + return -EIO; >> +} >> + >> +static int bitstream_helper(struct icap *icap, const u32 *word_buffer, >> + u32 word_count) >> +{ >> + u32 remain_word; >> + u32 word_written = 0; >> + int wr_fifo_vacancy = 0; >> + int err = 0; >> + >> + WARN_ON(!mutex_is_locked(&icap->icap_lock)); >> + for (remain_word = word_count; remain_word > 0; >> + remain_word -= word_written, word_buffer += word_written) { >> + wr_fifo_vacancy = reg_rd(&icap->icap_regs->ir_wfv); >> + if (wr_fifo_vacancy <= 0) { >> + ICAP_ERR(icap, "no vacancy: %d", wr_fifo_vacancy); >> + err = -EIO; >> + break; >> + } >> + word_written = (wr_fifo_vacancy < remain_word) ? >> + wr_fifo_vacancy : remain_word; >> + if (icap_write(icap, word_buffer, word_written) != 0) { >> + ICAP_ERR(icap, "write failed remain %d, written %d", >> + remain_word, word_written); >> + err = -EIO; >> + break; >> + } >> + } >> + >> + return err; >> +} >> + >> +static int icap_download(struct icap *icap, const char *buffer, >> + unsigned long length) >> +{ >> + u32 num_chars_read = DMA_HWICAP_BITFILE_BUFFER_SIZE; >> + u32 byte_read; >> + int err = 0; >> + >> + mutex_lock(&icap->icap_lock); >> + for (byte_read = 0; byte_read < length; byte_read += num_chars_read) { >> + num_chars_read = length - byte_read; >> + if (num_chars_read > DMA_HWICAP_BITFILE_BUFFER_SIZE) >> + num_chars_read = DMA_HWICAP_BITFILE_BUFFER_SIZE; >> + >> + err = bitstream_helper(icap, (u32 *)buffer, num_chars_read / sizeof(u32)); >> + if (err) >> + goto failed; >> + buffer += num_chars_read; >> + } >> + >> + err = wait_for_done(icap); >> + >> +failed: >> + mutex_unlock(&icap->icap_lock); >> + >> + return err; >> +} >> + >> +/* >> + * Run the following sequence of canned commands to obtain IDCODE of the FPGA >> + */ >> +static void icap_probe_chip(struct icap *icap) >> +{ >> + u32 w; >> + >> + w = reg_rd(&icap->icap_regs->ir_sr); >> + w = reg_rd(&icap->icap_regs->ir_sr); >> + reg_wr(&icap->icap_regs->ir_gier, 0x0); >> + w = reg_rd(&icap->icap_regs->ir_wfv); >> + reg_wr(&icap->icap_regs->ir_wf, 0xffffffff); >> + reg_wr(&icap->icap_regs->ir_wf, 0xaa995566); >> + reg_wr(&icap->icap_regs->ir_wf, 0x20000000); >> + reg_wr(&icap->icap_regs->ir_wf, 0x20000000); >> + reg_wr(&icap->icap_regs->ir_wf, 0x28018001); >> + reg_wr(&icap->icap_regs->ir_wf, 0x20000000); >> + reg_wr(&icap->icap_regs->ir_wf, 0x20000000); >> + w = reg_rd(&icap->icap_regs->ir_cr); >> + reg_wr(&icap->icap_regs->ir_cr, 0x1); >> + w = reg_rd(&icap->icap_regs->ir_cr); >> + w = reg_rd(&icap->icap_regs->ir_cr); >> + w = reg_rd(&icap->icap_regs->ir_sr); >> + w = reg_rd(&icap->icap_regs->ir_cr); >> + w = reg_rd(&icap->icap_regs->ir_sr); >> + reg_wr(&icap->icap_regs->ir_sz, 0x1); >> + w = reg_rd(&icap->icap_regs->ir_cr); >> + reg_wr(&icap->icap_regs->ir_cr, 0x2); >> + w = reg_rd(&icap->icap_regs->ir_rfo); >> + icap->idcode = reg_rd(&icap->icap_regs->ir_rf); >> + w = reg_rd(&icap->icap_regs->ir_cr); >> + (void)w; > ?! Right. 'w' does not make sense here. We will remove 'w'. Thanks, Lizhi >> +} >> + >> +static int >> +xrt_icap_leaf_ioctl(struct platform_device *pdev, u32 cmd, void *arg) >> +{ >> + struct xrt_icap_ioctl_wr *wr_arg = arg; >> + struct icap *icap; >> + int ret = 0; >> + >> + icap = platform_get_drvdata(pdev); >> + >> + switch (cmd) { >> + case XRT_XLEAF_EVENT: >> + /* Does not handle any event. */ >> + break; >> + case XRT_ICAP_WRITE: >> + ret = icap_download(icap, wr_arg->xiiw_bit_data, >> + wr_arg->xiiw_data_len); >> + break; >> + case XRT_ICAP_IDCODE: >> + *(u64 *)arg = icap->idcode; >> + break; >> + default: >> + ICAP_ERR(icap, "unknown command %d", cmd); >> + return -EINVAL; >> + } >> + >> + return ret; >> +} >> + >> +static int xrt_icap_remove(struct platform_device *pdev) >> +{ >> + struct icap *icap; >> + >> + icap = platform_get_drvdata(pdev); >> + >> + platform_set_drvdata(pdev, NULL); >> + devm_kfree(&pdev->dev, icap); >> + >> + return 0; >> +} >> + >> +static int xrt_icap_probe(struct platform_device *pdev) >> +{ >> + struct icap *icap; >> + int ret = 0; >> + struct resource *res; >> + >> + icap = devm_kzalloc(&pdev->dev, sizeof(*icap), GFP_KERNEL); >> + if (!icap) >> + return -ENOMEM; >> + >> + icap->pdev = pdev; >> + platform_set_drvdata(pdev, icap); >> + mutex_init(&icap->icap_lock); >> + >> + xrt_info(pdev, "probing"); >> + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); >> + if (res) { >> + icap->icap_regs = ioremap(res->start, res->end - res->start + 1); >> + if (!icap->icap_regs) { >> + xrt_err(pdev, "map base failed %pR", res); >> + ret = -EIO; >> + goto failed; >> + } >> + } >> + >> + icap_probe_chip(icap); >> +failed: >> + return ret; >> +} >> + >> +static struct xrt_subdev_endpoints xrt_icap_endpoints[] = { >> + { >> + .xse_names = (struct xrt_subdev_ep_names[]) { >> + { .ep_name = XRT_MD_NODE_FPGA_CONFIG }, >> + { NULL }, >> + }, >> + .xse_min_ep = 1, >> + }, >> + { 0 }, >> +}; >> + >> +static struct xrt_subdev_drvdata xrt_icap_data = { >> + .xsd_dev_ops = { >> + .xsd_ioctl = xrt_icap_leaf_ioctl, >> + }, >> +}; >> + >> +static const struct platform_device_id xrt_icap_table[] = { >> + { XRT_ICAP, (kernel_ulong_t)&xrt_icap_data }, >> + { }, >> +}; >> + >> +static struct platform_driver xrt_icap_driver = { >> + .driver = { >> + .name = XRT_ICAP, >> + }, >> + .probe = xrt_icap_probe, >> + .remove = xrt_icap_remove, >> + .id_table = xrt_icap_table, >> +}; >> + >> +void icap_leaf_init_fini(bool init) >> +{ >> + if (init) >> + xleaf_register_driver(XRT_SUBDEV_ICAP, &xrt_icap_driver, xrt_icap_endpoints); >> + else >> + xleaf_unregister_driver(XRT_SUBDEV_ICAP); >> +} >> -- >> 2.18.4 >> > - Moritz
On Sun, 2021-02-21 at 12:43 -0800, Moritz Fischer wrote: > On Wed, Feb 17, 2021 at 10:40:01PM -0800, Lizhi Hou wrote: > > This is V3 of patch series which adds management physical function driver for Xilinx > > Alveo PCIe accelerator cards, https://www.xilinx.com/products/boards-and-kits/alveo.html > > This driver is part of Xilinx Runtime (XRT) open source stack. [] > Please fix the indents all across this patchset. Doesn't checkpatch with > --strict complain about this? I glanced at a couple bits of these patches and didn't notice any of what I consider poor indentation style. What indent is wrong here?
On 2/17/21 10:40 PM, Lizhi Hou wrote: > Add ICAP driver. ICAP is a hardware function discovered by walking What does ICAP stand for ? > firmware metadata. A platform device node will be created for it. > FPGA bitstream is written to hardware through ICAP. > > Signed-off-by: Sonal Santan <sonal.santan@xilinx.com> > Signed-off-by: Max Zhen <max.zhen@xilinx.com> > Signed-off-by: Lizhi Hou <lizhih@xilinx.com> > --- > drivers/fpga/xrt/include/xleaf/icap.h | 29 +++ > drivers/fpga/xrt/lib/xleaf/icap.c | 317 ++++++++++++++++++++++++++ > 2 files changed, 346 insertions(+) > create mode 100644 drivers/fpga/xrt/include/xleaf/icap.h > create mode 100644 drivers/fpga/xrt/lib/xleaf/icap.c > > diff --git a/drivers/fpga/xrt/include/xleaf/icap.h b/drivers/fpga/xrt/include/xleaf/icap.h > new file mode 100644 > index 000000000000..a14fc0ffa78f > --- /dev/null > +++ b/drivers/fpga/xrt/include/xleaf/icap.h > @@ -0,0 +1,29 @@ > +/* SPDX-License-Identifier: GPL-2.0 */ > +/* > + * Header file for XRT ICAP Leaf Driver > + * > + * Copyright (C) 2020-2021 Xilinx, Inc. > + * > + * Authors: > + * Lizhi Hou <Lizhi.Hou@xilinx.com> > + */ > + > +#ifndef _XRT_ICAP_H_ > +#define _XRT_ICAP_H_ > + > +#include "xleaf.h" > + > +/* > + * ICAP driver IOCTL calls. > + */ > +enum xrt_icap_ioctl_cmd { > + XRT_ICAP_WRITE = XRT_XLEAF_CUSTOM_BASE, /* See comments in xleaf.h */ maybe XRT_ICAP_GET_IDCODE > + XRT_ICAP_IDCODE, > +}; > + > +struct xrt_icap_ioctl_wr { > + void *xiiw_bit_data; > + u32 xiiw_data_len; > +}; > + > +#endif /* _XRT_ICAP_H_ */ > diff --git a/drivers/fpga/xrt/lib/xleaf/icap.c b/drivers/fpga/xrt/lib/xleaf/icap.c > new file mode 100644 > index 000000000000..0500a97bdef9 > --- /dev/null > +++ b/drivers/fpga/xrt/lib/xleaf/icap.c > @@ -0,0 +1,317 @@ > +// SPDX-License-Identifier: GPL-2.0 > +/* > + * Xilinx Alveo FPGA ICAP Driver > + * > + * Copyright (C) 2020-2021 Xilinx, Inc. > + * > + * Authors: > + * Lizhi Hou<Lizhi.Hou@xilinx.com> > + * Sonal Santan <sonals@xilinx.com> > + * Max Zhen <maxz@xilinx.com> > + */ > + > +#include <linux/mod_devicetable.h> > +#include <linux/platform_device.h> > +#include <linux/delay.h> > +#include <linux/device.h> > +#include <linux/io.h> > +#include "metadata.h" > +#include "xleaf.h" > +#include "xleaf/icap.h" > +#include "xclbin-helper.h" > + > +#define XRT_ICAP "xrt_icap" > + > +#define ICAP_ERR(icap, fmt, arg...) \ > + xrt_err((icap)->pdev, fmt "\n", ##arg) > +#define ICAP_WARN(icap, fmt, arg...) \ > + xrt_warn((icap)->pdev, fmt "\n", ##arg) > +#define ICAP_INFO(icap, fmt, arg...) \ > + xrt_info((icap)->pdev, fmt "\n", ##arg) > +#define ICAP_DBG(icap, fmt, arg...) \ > + xrt_dbg((icap)->pdev, fmt "\n", ##arg) > + > +/* > + * AXI-HWICAP IP register layout > + */ > +struct icap_reg { > + u32 ir_rsvd1[7]; > + u32 ir_gier; > + u32 ir_isr; > + u32 ir_rsvd2; > + u32 ir_ier; > + u32 ir_rsvd3[53]; > + u32 ir_wf; > + u32 ir_rf; > + u32 ir_sz; > + u32 ir_cr; > + u32 ir_sr; > + u32 ir_wfv; > + u32 ir_rfo; > + u32 ir_asr; > +} __packed; > + > +struct icap { > + struct platform_device *pdev; > + struct icap_reg *icap_regs; > + struct mutex icap_lock; /* icap dev lock */ > + > + unsigned int idcode; returned as a 64 bit value, but could be stored as 32 bit > +}; > + > +static inline u32 reg_rd(void __iomem *reg) > +{ > + if (!reg) > + return -1; > + > + return ioread32(reg); Look at converting the io access to using regmap* api > +} > + > +static inline void reg_wr(void __iomem *reg, u32 val) > +{ > + if (!reg) > + return; > + > + iowrite32(val, reg); > +} > + > +static int wait_for_done(struct icap *icap) > +{ > + u32 w; > + int i = 0; > + > + WARN_ON(!mutex_is_locked(&icap->icap_lock)); is this needed ? wait_for_done is only called in one place. > + for (i = 0; i < 10; i++) { > + udelay(5); comment on delay. > + w = reg_rd(&icap->icap_regs->ir_sr); > + ICAP_INFO(icap, "XHWICAP_SR: %x", w); > + if (w & 0x5) 0x5 is a magic number, should be #defined > + return 0; > + } > + > + ICAP_ERR(icap, "bitstream download timeout"); > + return -ETIMEDOUT; > +} > + > +static int icap_write(struct icap *icap, const u32 *word_buf, int size) > +{ > + int i; > + u32 value = 0; > + > + for (i = 0; i < size; i++) { > + value = be32_to_cpu(word_buf[i]); > + reg_wr(&icap->icap_regs->ir_wf, value); > + } > + > + reg_wr(&icap->icap_regs->ir_cr, 0x1); > + > + for (i = 0; i < 20; i++) { > + value = reg_rd(&icap->icap_regs->ir_cr); > + if ((value & 0x1) == 0) > + return 0; > + ndelay(50); > + } > + > + ICAP_ERR(icap, "writing %d dwords timeout", size); > + return -EIO; > +} > + > +static int bitstream_helper(struct icap *icap, const u32 *word_buffer, > + u32 word_count) > +{ > + u32 remain_word; > + u32 word_written = 0; > + int wr_fifo_vacancy = 0; > + int err = 0; > + > + WARN_ON(!mutex_is_locked(&icap->icap_lock)); > + for (remain_word = word_count; remain_word > 0; > + remain_word -= word_written, word_buffer += word_written) { > + wr_fifo_vacancy = reg_rd(&icap->icap_regs->ir_wfv); > + if (wr_fifo_vacancy <= 0) { > + ICAP_ERR(icap, "no vacancy: %d", wr_fifo_vacancy); > + err = -EIO; > + break; > + } > + word_written = (wr_fifo_vacancy < remain_word) ? > + wr_fifo_vacancy : remain_word; > + if (icap_write(icap, word_buffer, word_written) != 0) { > + ICAP_ERR(icap, "write failed remain %d, written %d", > + remain_word, word_written); > + err = -EIO; > + break; > + } > + } > + > + return err; > +} > + > +static int icap_download(struct icap *icap, const char *buffer, > + unsigned long length) > +{ > + u32 num_chars_read = DMA_HWICAP_BITFILE_BUFFER_SIZE; > + u32 byte_read; > + int err = 0; > + > + mutex_lock(&icap->icap_lock); > + for (byte_read = 0; byte_read < length; byte_read += num_chars_read) { > + num_chars_read = length - byte_read; > + if (num_chars_read > DMA_HWICAP_BITFILE_BUFFER_SIZE) > + num_chars_read = DMA_HWICAP_BITFILE_BUFFER_SIZE; > + > + err = bitstream_helper(icap, (u32 *)buffer, num_chars_read / sizeof(u32)); assumption that num_chars_read % 4 == 0 Add a check, or handle. > + if (err) > + goto failed; > + buffer += num_chars_read; > + } > + > + err = wait_for_done(icap); timeout is not handled > + > +failed: > + mutex_unlock(&icap->icap_lock); > + > + return err; > +} > + > +/* > + * Run the following sequence of canned commands to obtain IDCODE of the FPGA > + */ > +static void icap_probe_chip(struct icap *icap) > +{ > + u32 w; De magic this. If this is a documented startup sequence, please add a link to the document. Else add a comment about what you are doing here. Where possible, convert the hex values to #defines. Tom > + > + w = reg_rd(&icap->icap_regs->ir_sr); > + w = reg_rd(&icap->icap_regs->ir_sr); > + reg_wr(&icap->icap_regs->ir_gier, 0x0); > + w = reg_rd(&icap->icap_regs->ir_wfv); > + reg_wr(&icap->icap_regs->ir_wf, 0xffffffff); > + reg_wr(&icap->icap_regs->ir_wf, 0xaa995566); > + reg_wr(&icap->icap_regs->ir_wf, 0x20000000); > + reg_wr(&icap->icap_regs->ir_wf, 0x20000000); > + reg_wr(&icap->icap_regs->ir_wf, 0x28018001); > + reg_wr(&icap->icap_regs->ir_wf, 0x20000000); > + reg_wr(&icap->icap_regs->ir_wf, 0x20000000); > + w = reg_rd(&icap->icap_regs->ir_cr); > + reg_wr(&icap->icap_regs->ir_cr, 0x1); > + w = reg_rd(&icap->icap_regs->ir_cr); > + w = reg_rd(&icap->icap_regs->ir_cr); > + w = reg_rd(&icap->icap_regs->ir_sr); > + w = reg_rd(&icap->icap_regs->ir_cr); > + w = reg_rd(&icap->icap_regs->ir_sr); > + reg_wr(&icap->icap_regs->ir_sz, 0x1); > + w = reg_rd(&icap->icap_regs->ir_cr); > + reg_wr(&icap->icap_regs->ir_cr, 0x2); > + w = reg_rd(&icap->icap_regs->ir_rfo); > + icap->idcode = reg_rd(&icap->icap_regs->ir_rf); > + w = reg_rd(&icap->icap_regs->ir_cr); > + (void)w; > +} > + > +static int > +xrt_icap_leaf_ioctl(struct platform_device *pdev, u32 cmd, void *arg) > +{ > + struct xrt_icap_ioctl_wr *wr_arg = arg; > + struct icap *icap; > + int ret = 0; > + > + icap = platform_get_drvdata(pdev); > + > + switch (cmd) { > + case XRT_XLEAF_EVENT: > + /* Does not handle any event. */ > + break; > + case XRT_ICAP_WRITE: > + ret = icap_download(icap, wr_arg->xiiw_bit_data, > + wr_arg->xiiw_data_len); > + break; > + case XRT_ICAP_IDCODE: > + *(u64 *)arg = icap->idcode; > + break; > + default: > + ICAP_ERR(icap, "unknown command %d", cmd); > + return -EINVAL; > + } > + > + return ret; > +} > + > +static int xrt_icap_remove(struct platform_device *pdev) > +{ > + struct icap *icap; > + > + icap = platform_get_drvdata(pdev); > + > + platform_set_drvdata(pdev, NULL); > + devm_kfree(&pdev->dev, icap); > + > + return 0; > +} > + > +static int xrt_icap_probe(struct platform_device *pdev) > +{ > + struct icap *icap; > + int ret = 0; > + struct resource *res; > + > + icap = devm_kzalloc(&pdev->dev, sizeof(*icap), GFP_KERNEL); > + if (!icap) > + return -ENOMEM; > + > + icap->pdev = pdev; > + platform_set_drvdata(pdev, icap); > + mutex_init(&icap->icap_lock); > + > + xrt_info(pdev, "probing"); > + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); > + if (res) { > + icap->icap_regs = ioremap(res->start, res->end - res->start + 1); > + if (!icap->icap_regs) { > + xrt_err(pdev, "map base failed %pR", res); > + ret = -EIO; > + goto failed; > + } > + } > + > + icap_probe_chip(icap); > +failed: > + return ret; > +} > + > +static struct xrt_subdev_endpoints xrt_icap_endpoints[] = { > + { > + .xse_names = (struct xrt_subdev_ep_names[]) { > + { .ep_name = XRT_MD_NODE_FPGA_CONFIG }, > + { NULL }, > + }, > + .xse_min_ep = 1, > + }, > + { 0 }, > +}; > + > +static struct xrt_subdev_drvdata xrt_icap_data = { > + .xsd_dev_ops = { > + .xsd_ioctl = xrt_icap_leaf_ioctl, > + }, > +}; > + > +static const struct platform_device_id xrt_icap_table[] = { > + { XRT_ICAP, (kernel_ulong_t)&xrt_icap_data }, > + { }, > +}; > + > +static struct platform_driver xrt_icap_driver = { > + .driver = { > + .name = XRT_ICAP, > + }, > + .probe = xrt_icap_probe, > + .remove = xrt_icap_remove, > + .id_table = xrt_icap_table, > +}; > + > +void icap_leaf_init_fini(bool init) > +{ > + if (init) > + xleaf_register_driver(XRT_SUBDEV_ICAP, &xrt_icap_driver, xrt_icap_endpoints); > + else > + xleaf_unregister_driver(XRT_SUBDEV_ICAP); > +}
On Tue, Mar 02, 2021 at 10:49:43PM -0800, Joe Perches wrote: > On Sun, 2021-02-21 at 12:43 -0800, Moritz Fischer wrote: > > On Wed, Feb 17, 2021 at 10:40:01PM -0800, Lizhi Hou wrote: > > > This is V3 of patch series which adds management physical function driver for Xilinx > > > Alveo PCIe accelerator cards, https://www.xilinx.com/products/boards-and-kits/alveo.html > > > This driver is part of Xilinx Runtime (XRT) open source stack. > [] > > Please fix the indents all across this patchset. Doesn't checkpatch with > > --strict complain about this? > > I glanced at a couple bits of these patches and didn't > notice any of what I consider poor indentation style. > > What indent is wrong here? Maybe I dreamed it, or confused it with the CamelCase issues instead? Sorry for the noise in that case, - Moritz
Hi Tom, On 02/28/2021 08:36 AM, Tom Rix wrote: > > On 2/17/21 10:40 PM, Lizhi Hou wrote: >> fpga-mgr and region implementation for xclbin download which will be >> called from main platform driver >> >> Signed-off-by: Sonal Santan <sonal.santan@xilinx.com> >> Signed-off-by: Max Zhen <max.zhen@xilinx.com> >> Signed-off-by: Lizhi Hou <lizhih@xilinx.com> >> --- >> drivers/fpga/xrt/mgmt/fmgr-drv.c | 187 +++++++++++ >> drivers/fpga/xrt/mgmt/fmgr.h | 28 ++ >> drivers/fpga/xrt/mgmt/main-region.c | 471 ++++++++++++++++++++++++++++ >> 3 files changed, 686 insertions(+) >> create mode 100644 drivers/fpga/xrt/mgmt/fmgr-drv.c >> create mode 100644 drivers/fpga/xrt/mgmt/fmgr.h >> create mode 100644 drivers/fpga/xrt/mgmt/main-region.c >> >> diff --git a/drivers/fpga/xrt/mgmt/fmgr-drv.c b/drivers/fpga/xrt/mgmt/fmgr-drv.c >> new file mode 100644 >> index 000000000000..a44d35ecdb60 >> --- /dev/null >> +++ b/drivers/fpga/xrt/mgmt/fmgr-drv.c >> @@ -0,0 +1,187 @@ >> +// SPDX-License-Identifier: GPL-2.0 >> +/* >> + * FPGA Manager Support for Xilinx Alveo Management Function Driver >> + * >> + * Copyright (C) 2020-2021 Xilinx, Inc. >> + * >> + * Authors: Sonal.Santan@xilinx.com >> + */ >> + >> +#include <linux/cred.h> >> +#include <linux/efi.h> >> +#include <linux/fpga/fpga-mgr.h> >> +#include <linux/platform_device.h> >> +#include <linux/module.h> >> +#include <linux/vmalloc.h> >> + >> +#include "xclbin-helper.h" >> +#include "xleaf.h" >> +#include "fmgr.h" >> +#include "xleaf/axigate.h" >> +#include "xleaf/icap.h" >> +#include "main-impl.h" >> + >> +struct xfpga_class { >> + const struct platform_device *pdev; >> + char name[64]; >> +}; >> + >> +/* >> + * xclbin download plumbing -- find the download subsystem, ICAP and >> + * pass the xclbin for heavy lifting >> + */ >> +static int xmgmt_download_bitstream(struct platform_device *pdev, >> + const struct axlf *xclbin) >> + >> +{ >> + struct hw_icap_bit_header bit_header = { 0 }; >> + struct platform_device *icap_leaf = NULL; >> + struct xrt_icap_ioctl_wr arg; >> + char *bitstream = NULL; >> + u64 bit_len; >> + int ret; >> + >> + ret = xrt_xclbin_get_section(xclbin, BITSTREAM, (void **)&bitstream, &bit_len); >> + if (ret || !bitstream) { > !bitstream check is unneeded Will fix. >> + xrt_err(pdev, "bitstream not found"); >> + return -ENOENT; >> + } >> + ret = xrt_xclbin_parse_bitstream_header(bitstream, >> + DMA_HWICAP_BITFILE_BUFFER_SIZE, >> + &bit_header); >> + if (ret) { >> + ret = -EINVAL; >> + xrt_err(pdev, "invalid bitstream header"); >> + goto done; >> + } >> + if (bit_header.header_length + bit_header.bitstream_length > bit_len) { >> + ret = -EINVAL; >> + xrt_err(pdev, "invalid bitstream length. header %d, bitstream %d, section len %lld", >> + bit_header.header_length, bit_header.bitstream_length, bit_len); >> + goto done; >> + } >> + >> + icap_leaf = xleaf_get_leaf_by_id(pdev, XRT_SUBDEV_ICAP, PLATFORM_DEVID_NONE); >> + if (!icap_leaf) { >> + ret = -ENODEV; >> + xrt_err(pdev, "icap does not exist"); >> + xrt_xclbin_free_header(&bit_header); >> + goto done; >> + } >> + arg.xiiw_bit_data = bitstream + bit_header.header_length; >> + arg.xiiw_data_len = bit_header.bitstream_length; >> + ret = xleaf_ioctl(icap_leaf, XRT_ICAP_WRITE, &arg); >> + if (ret) >> + xrt_err(pdev, "write bitstream failed, ret = %d", ret); >> + >> + xrt_xclbin_free_header(&bit_header); > memory leak when something fails and goto done's Based on comments of previous patch, it does not need allocating extra memory in header parsing function. xrt_xclbin_free_header() will be removed. >> +done: > previous general problem, use mutliple label in error handling blocks Will fix this. >> + if (icap_leaf) >> + xleaf_put_leaf(pdev, icap_leaf); >> + vfree(bitstream); >> + >> + return ret; >> +} >> + >> +/* >> + * There is no HW prep work we do here since we need the full >> + * xclbin for its sanity check. >> + */ >> +static int xmgmt_pr_write_init(struct fpga_manager *mgr, >> + struct fpga_image_info *info, >> + const char *buf, size_t count) >> +{ >> + const struct axlf *bin = (const struct axlf *)buf; >> + struct xfpga_class *obj = mgr->priv; >> + >> + if (!(info->flags & FPGA_MGR_PARTIAL_RECONFIG)) { >> + xrt_info(obj->pdev, "%s only supports partial reconfiguration\n", obj->name); >> + return -EINVAL; >> + } >> + >> + if (count < sizeof(struct axlf)) >> + return -EINVAL; >> + >> + if (count > bin->m_header.m_length) >> + return -EINVAL; >> + >> + xrt_info(obj->pdev, "Prepare download of xclbin %pUb of length %lld B", >> + &bin->m_header.uuid, bin->m_header.m_length); >> + >> + return 0; >> +} >> + >> +/* >> + * The implementation requries full xclbin image before we can start >> + * programming the hardware via ICAP subsystem. Full image is required > The full image Will fix this. >> + * for checking the validity of xclbin and walking the sections to >> + * discover the bitstream. >> + */ >> +static int xmgmt_pr_write(struct fpga_manager *mgr, >> + const char *buf, size_t count) >> +{ >> + const struct axlf *bin = (const struct axlf *)buf; >> + struct xfpga_class *obj = mgr->priv; >> + >> + if (bin->m_header.m_length != count) >> + return -EINVAL; >> + >> + return xmgmt_download_bitstream((void *)obj->pdev, bin); >> +} >> + >> +static int xmgmt_pr_write_complete(struct fpga_manager *mgr, >> + struct fpga_image_info *info) >> +{ >> + const struct axlf *bin = (const struct axlf *)info->buf; >> + struct xfpga_class *obj = mgr->priv; >> + >> + xrt_info(obj->pdev, "Finished download of xclbin %pUb", >> + &bin->m_header.uuid); >> + return 0; >> +} >> + >> +static enum fpga_mgr_states xmgmt_pr_state(struct fpga_manager *mgr) >> +{ >> + return FPGA_MGR_STATE_UNKNOWN; > why just this state ? This is copied from fme_mgr_state(). I think we can defer this and return more status when we need them? >> +} >> + >> +static const struct fpga_manager_ops xmgmt_pr_ops = { >> + .initial_header_size = sizeof(struct axlf), >> + .write_init = xmgmt_pr_write_init, >> + .write = xmgmt_pr_write, >> + .write_complete = xmgmt_pr_write_complete, >> + .state = xmgmt_pr_state, >> +}; >> + >> +struct fpga_manager *xmgmt_fmgr_probe(struct platform_device *pdev) >> +{ >> + struct xfpga_class *obj = devm_kzalloc(DEV(pdev), sizeof(struct xfpga_class), >> + GFP_KERNEL); >> + struct fpga_manager *fmgr = NULL; >> + int ret = 0; >> + >> + if (!obj) >> + return ERR_PTR(-ENOMEM); >> + >> + snprintf(obj->name, sizeof(obj->name), "Xilinx Alveo FPGA Manager"); >> + obj->pdev = pdev; >> + fmgr = fpga_mgr_create(&pdev->dev, >> + obj->name, >> + &xmgmt_pr_ops, >> + obj); >> + if (!fmgr) >> + return ERR_PTR(-ENOMEM); >> + >> + ret = fpga_mgr_register(fmgr); >> + if (ret) { >> + fpga_mgr_free(fmgr); >> + return ERR_PTR(ret); >> + } >> + return fmgr; >> +} >> + >> +int xmgmt_fmgr_remove(struct fpga_manager *fmgr) >> +{ >> + fpga_mgr_unregister(fmgr); >> + return 0; >> +} >> diff --git a/drivers/fpga/xrt/mgmt/fmgr.h b/drivers/fpga/xrt/mgmt/fmgr.h >> new file mode 100644 >> index 000000000000..e1fc033e2542 >> --- /dev/null >> +++ b/drivers/fpga/xrt/mgmt/fmgr.h >> @@ -0,0 +1,28 @@ >> +/* SPDX-License-Identifier: GPL-2.0 */ >> +/* >> + * Header file for Xilinx Alveo Management Function Driver >> + * >> + * Copyright (C) 2020-2021 Xilinx, Inc. >> + * >> + * Authors: Sonal.Santan@xilinx.com >> + */ >> + >> +#ifndef _XMGMT_FMGR_H_ >> +#define _XMGMT_FMGR_H_ >> + >> +#include <linux/fpga/fpga-mgr.h> >> +#include <linux/mutex.h> >> + >> +#include <linux/xrt/xclbin.h> >> + >> +enum xfpga_sec_level { >> + XFPGA_SEC_NONE = 0, >> + XFPGA_SEC_DEDICATE, >> + XFPGA_SEC_SYSTEM, >> + XFPGA_SEC_MAX = XFPGA_SEC_SYSTEM, >> +}; > This enum is not used, remove. Will remove. >> + >> +struct fpga_manager *xmgmt_fmgr_probe(struct platform_device *pdev); >> +int xmgmt_fmgr_remove(struct fpga_manager *fmgr); >> + >> +#endif >> diff --git a/drivers/fpga/xrt/mgmt/main-region.c b/drivers/fpga/xrt/mgmt/main-region.c >> new file mode 100644 >> index 000000000000..9779693fe7ae >> --- /dev/null >> +++ b/drivers/fpga/xrt/mgmt/main-region.c >> @@ -0,0 +1,471 @@ >> +// SPDX-License-Identifier: GPL-2.0 >> +/* >> + * FPGA Region Support for Xilinx Alveo Management Function Driver >> + * >> + * Copyright (C) 2020-2021 Xilinx, Inc. >> + * Bulk of the code borrowed from XRT mgmt driver file, fmgr.c >> + * >> + * Authors: Lizhi.Hou@xilinx.com >> + */ >> + >> +#include <linux/uuid.h> >> +#include <linux/fpga/fpga-bridge.h> >> +#include <linux/fpga/fpga-region.h> >> +#include "metadata.h" >> +#include "xleaf.h" >> +#include "xleaf/axigate.h" >> +#include "xclbin-helper.h" >> +#include "main-impl.h" >> + >> +struct xmgmt_bridge { >> + struct platform_device *pdev; >> + const char *axigate_name; > axigate ? > > this element could just be 'name' > > it seems like 'axigate' means 'bridge', why not use 'bridge' ? Will change to 'bridge' > >> +}; >> + >> +struct xmgmt_region { >> + struct platform_device *pdev; >> + struct fpga_region *fregion; >> + uuid_t intf_uuid; >> + struct fpga_bridge *fbridge; >> + int grp_inst; >> + uuid_t dep_uuid; >> + struct list_head list; > clean up element names > > fregion -> region > > grp_inst -> group_instance > > ect. Will fix this. > >> +}; >> + >> +struct xmgmt_region_match_arg { >> + struct platform_device *pdev; >> + uuid_t *uuids; >> + u32 uuid_num; >> +}; >> + >> +static int xmgmt_br_enable_set(struct fpga_bridge *bridge, bool enable) >> +{ >> + struct xmgmt_bridge *br_data = (struct xmgmt_bridge *)bridge->priv; >> + struct platform_device *axigate_leaf; >> + int rc; >> + >> + axigate_leaf = xleaf_get_leaf_by_epname(br_data->pdev, br_data->axigate_name); >> + if (!axigate_leaf) { >> + xrt_err(br_data->pdev, "failed to get leaf %s", >> + br_data->axigate_name); >> + return -ENOENT; >> + } >> + >> + if (enable) >> + rc = xleaf_ioctl(axigate_leaf, XRT_AXIGATE_FREE, NULL); >> + else >> + rc = xleaf_ioctl(axigate_leaf, XRT_AXIGATE_FREEZE, NULL); >> + >> + if (rc) { >> + xrt_err(br_data->pdev, "failed to %s gate %s, rc %d", >> + (enable ? "free" : "freeze"), br_data->axigate_name, >> + rc); >> + } >> + >> + xleaf_put_leaf(br_data->pdev, axigate_leaf); >> + >> + return rc; >> +} >> + >> +const struct fpga_bridge_ops xmgmt_bridge_ops = { >> + .enable_set = xmgmt_br_enable_set >> +}; >> + >> +static void xmgmt_destroy_bridge(struct fpga_bridge *br) >> +{ >> + struct xmgmt_bridge *br_data = br->priv; >> + >> + if (!br_data) >> + return; >> + >> + xrt_info(br_data->pdev, "destroy fpga bridge %s", br_data->axigate_name); >> + fpga_bridge_unregister(br); >> + >> + devm_kfree(DEV(br_data->pdev), br_data); >> + >> + fpga_bridge_free(br); >> +} >> + >> +static struct fpga_bridge *xmgmt_create_bridge(struct platform_device *pdev, >> + char *dtb) >> +{ >> + struct xmgmt_bridge *br_data; >> + struct fpga_bridge *br = NULL; >> + const char *gate; >> + int rc; >> + >> + br_data = devm_kzalloc(DEV(pdev), sizeof(*br_data), GFP_KERNEL); >> + if (!br_data) >> + return NULL; >> + br_data->pdev = pdev; >> + >> + br_data->axigate_name = XRT_MD_NODE_GATE_ULP; >> + rc = xrt_md_find_endpoint(&pdev->dev, dtb, XRT_MD_NODE_GATE_ULP, >> + NULL, &gate); >> + if (rc) { >> + br_data->axigate_name = XRT_MD_NODE_GATE_PLP; >> + rc = xrt_md_find_endpoint(&pdev->dev, dtb, XRT_MD_NODE_GATE_PLP, >> + NULL, &gate); >> + } >> + if (rc) { >> + xrt_err(pdev, "failed to get axigate, rc %d", rc); >> + goto failed; >> + } >> + >> + br = fpga_bridge_create(DEV(pdev), br_data->axigate_name, >> + &xmgmt_bridge_ops, br_data); >> + if (!br) { >> + xrt_err(pdev, "failed to create bridge"); >> + goto failed; >> + } >> + >> + rc = fpga_bridge_register(br); >> + if (rc) { >> + xrt_err(pdev, "failed to register bridge, rc %d", rc); >> + goto failed; >> + } >> + >> + xrt_info(pdev, "created fpga bridge %s", br_data->axigate_name); >> + >> + return br; >> + >> +failed: >> + if (br) >> + fpga_bridge_free(br); >> + if (br_data) >> + devm_kfree(DEV(pdev), br_data); >> + >> + return NULL; >> +} >> + >> +static void xmgmt_destroy_region(struct fpga_region *re) > re, to me means regular expression. > > can you use 'region' instead ? Will change this. > >> +{ >> + struct xmgmt_region *r_data = re->priv; >> + >> + xrt_info(r_data->pdev, "destroy fpga region %llx%llx", > need a sperator here ? between %llx%llx Will add '.' in between. >> + re->compat_id->id_l, re->compat_id->id_h); >> + >> + fpga_region_unregister(re); >> + >> + if (r_data->grp_inst > 0) >> + xleaf_destroy_group(r_data->pdev, r_data->grp_inst); >> + >> + if (r_data->fbridge) >> + xmgmt_destroy_bridge(r_data->fbridge); >> + >> + if (r_data->fregion->info) { >> + fpga_image_info_free(r_data->fregion->info); >> + r_data->fregion->info = NULL; >> + } >> + >> + fpga_region_free(re); >> + >> + devm_kfree(DEV(r_data->pdev), r_data); >> +} >> + >> +static int xmgmt_region_match(struct device *dev, const void *data) >> +{ >> + const struct xmgmt_region_match_arg *arg = data; >> + const struct fpga_region *match_re; >> + int i; >> + >> + if (dev->parent != &arg->pdev->dev) >> + return false; >> + >> + match_re = to_fpga_region(dev); >> + /* >> + * The device tree provides both parent and child uuids for an >> + * xclbin in one array. Here we try both uuids to see if it matches >> + * with target region's compat_id. Strictly speaking we should >> + * only match xclbin's parent uuid with target region's compat_id >> + * but given the uuids by design are unique comparing with both >> + * does not hurt. >> + */ >> + for (i = 0; i < arg->uuid_num; i++) { >> + if (!memcmp(match_re->compat_id, &arg->uuids[i], >> + sizeof(*match_re->compat_id))) >> + return true; >> + } >> + >> + return false; >> +} >> + >> +static int xmgmt_region_match_base(struct device *dev, const void *data) >> +{ >> + const struct xmgmt_region_match_arg *arg = data; >> + const struct fpga_region *match_re; >> + const struct xmgmt_region *r_data; >> + >> + if (dev->parent != &arg->pdev->dev) >> + return false; >> + >> + match_re = to_fpga_region(dev); > me getting confused thinking match_re is 'match regular expression' Will change to 'match_region'. >> + r_data = match_re->priv; >> + if (uuid_is_null(&r_data->dep_uuid)) >> + return true; >> + >> + return false; >> +} >> + >> +static int xmgmt_region_match_by_depuuid(struct device *dev, const void *data) > what is a dep uuid ? A region could be on top of another base region. 'dep uuid' means base region uuid it depends on. > > should add a '_' so function name is xmgmt_region_match_by_dep_uuid() > > this is quite long. Will change to xmgmt_region_match_by_uuid(). > >> +{ >> + const struct xmgmt_region_match_arg *arg = data; >> + const struct fpga_region *match_re; >> + const struct xmgmt_region *r_data; >> + >> + if (dev->parent != &arg->pdev->dev) >> + return false; >> + >> + match_re = to_fpga_region(dev); >> + r_data = match_re->priv; >> + if (!memcmp(&r_data->dep_uuid, arg->uuids, sizeof(uuid_t))) > arg->uuids is an array > > arg->uuid_num is its extent. > > should be a loop or check on uuid_num == 1 or both. Will add check on uuid_num == 1. > >> + return true; >> + >> + return false; >> +} >> + >> +static void xmgmt_region_cleanup(struct fpga_region *re) >> +{ >> + struct xmgmt_region *r_data = re->priv, *temp; >> + struct platform_device *pdev = r_data->pdev; >> + struct fpga_region *match_re = NULL; >> + struct device *start_dev = NULL; >> + struct xmgmt_region_match_arg arg; >> + LIST_HEAD(free_list); >> + >> + list_add_tail(&r_data->list, &free_list); >> + arg.pdev = pdev; >> + arg.uuid_num = 1; >> + >> + while (!r_data) { >> + arg.uuids = (uuid_t *)r_data->fregion->compat_id; >> + match_re = fpga_region_class_find(start_dev, &arg, >> + xmgmt_region_match_by_depuuid); >> + if (match_re) { >> + r_data = match_re->priv; > This setting of r_data and continuing is strange, add a comment. > > or if you intend to do a pair of operations, do the pair within the if block and remove the strangeness. Thanks for pointing it out. This is poor implementation. I will re-implement the loop and add comment. > >> + list_add_tail(&r_data->list, &free_list); >> + start_dev = &match_re->dev; >> + put_device(&match_re->dev); >> + continue; >> + } >> + >> + r_data = list_is_last(&r_data->list, &free_list) ? NULL : >> + list_next_entry(r_data, list); >> + start_dev = NULL; >> + } >> + >> + list_for_each_entry_safe_reverse(r_data, temp, &free_list, list) { >> + if (list_is_first(&r_data->list, &free_list)) { >> + if (r_data->grp_inst > 0) { >> + xleaf_destroy_group(pdev, r_data->grp_inst); >> + r_data->grp_inst = -1; >> + } >> + if (r_data->fregion->info) { >> + fpga_image_info_free(r_data->fregion->info); >> + r_data->fregion->info = NULL; >> + } >> + continue; > add a comment, why is a continue needed here ? Will remove the continue and pop the first node before the loop. >> + } >> + xmgmt_destroy_region(r_data->fregion); >> + } >> +} >> + >> +void xmgmt_region_cleanup_all(struct platform_device *pdev) >> +{ >> + struct fpga_region *base_re; >> + struct xmgmt_region_match_arg arg; >> + >> + arg.pdev = pdev; >> + >> + for (base_re = fpga_region_class_find(NULL, &arg, xmgmt_region_match_base); >> + base_re; >> + base_re = fpga_region_class_find(NULL, &arg, xmgmt_region_match_base)) { > convert to a while > > while (base_region = ... ) { Will convert. > >> + put_device(&base_re->dev); >> + >> + xmgmt_region_cleanup(base_re); >> + xmgmt_destroy_region(base_re); >> + } >> +} >> + >> +/* >> + * Program a given region with given xclbin image. Bring up the subdevs and the > Program a region with a xclbin image. Will fix this. >> + * group object to contain the subdevs. >> + */ >> +static int xmgmt_region_program(struct fpga_region *re, const void *xclbin, char *dtb) >> +{ >> + struct xmgmt_region *r_data = re->priv; >> + struct platform_device *pdev = r_data->pdev; >> + struct fpga_image_info *info; >> + const struct axlf *xclbin_obj = xclbin; >> + int rc; >> + >> + info = fpga_image_info_alloc(&pdev->dev); >> + if (!info) >> + return -ENOMEM; >> + >> + info->buf = xclbin; >> + info->count = xclbin_obj->m_header.m_length; >> + info->flags |= FPGA_MGR_PARTIAL_RECONFIG; >> + re->info = info; >> + rc = fpga_region_program_fpga(re); >> + if (rc) { >> + xrt_err(pdev, "programming xclbin failed, rc %d", rc); >> + return rc; >> + } > free info ? info will be freed outside by xmgmt_destroy_region(). >> + >> + /* free bridges to allow reprogram */ >> + if (re->get_bridges) >> + fpga_bridges_put(&re->bridge_list); >> + >> + /* >> + * Next bringup the subdevs for this region which will be managed by >> + * its own group object. >> + */ >> + r_data->grp_inst = xleaf_create_group(pdev, dtb); >> + if (r_data->grp_inst < 0) { >> + xrt_err(pdev, "failed to create group, rc %d", >> + r_data->grp_inst); >> + rc = r_data->grp_inst; >> + return rc; >> + } >> + >> + rc = xleaf_wait_for_group_bringup(pdev); >> + if (rc) >> + xrt_err(pdev, "group bringup failed, rc %d", rc); > failed but no error handling, shouldn't the leaves and group be torn down ? Group is torn down outside by xmgmt_destroy_region(). >> + return rc; >> +} >> + >> +static int xmgmt_get_bridges(struct fpga_region *re) >> +{ >> + struct xmgmt_region *r_data = re->priv; >> + struct device *dev = &r_data->pdev->dev; >> + >> + return fpga_bridge_get_to_list(dev, re->info, &re->bridge_list); >> +} >> + >> +/* >> + * Program/create FPGA regions based on input xclbin file. This is key function >> + * stitching the flow together: > 'This is ' .. sentence does not make sense, but is not needed drop it. Will drop it. >> + * 1. Identify a matching existing region for this xclbin >> + * 2. Tear down any previous objects for the found region >> + * 3. Program this region with input xclbin >> + * 4. Iterate over this region's interface uuids to determine if it defines any >> + * child region. Create fpga_region for the child region. >> + */ >> +int xmgmt_process_xclbin(struct platform_device *pdev, >> + struct fpga_manager *fmgr, >> + const struct axlf *xclbin, >> + enum provider_kind kind) >> +{ >> + struct fpga_region *re, *compat_re = NULL; >> + struct xmgmt_region_match_arg arg; > should initialize to { 0 } Will fix this and few other places. >> + struct xmgmt_region *r_data; >> + char *dtb = NULL; >> + int rc, i; >> + >> + rc = xrt_xclbin_get_metadata(DEV(pdev), xclbin, &dtb); >> + if (rc) { >> + xrt_err(pdev, "failed to get dtb: %d", rc); >> + goto failed; >> + } >> + >> + xrt_md_get_intf_uuids(DEV(pdev), dtb, &arg.uuid_num, NULL); > should also check return and return that error code, it isn't always -EINVAL Will fix this. >> + if (arg.uuid_num == 0) { >> + xrt_err(pdev, "failed to get intf uuid"); >> + rc = -EINVAL; >> + goto failed; >> + } >> + arg.uuids = vzalloc(sizeof(uuid_t) * arg.uuid_num); >> + if (!arg.uuids) { >> + rc = -ENOMEM; >> + goto failed; >> + } >> + arg.pdev = pdev; >> + >> + xrt_md_get_intf_uuids(DEV(pdev), dtb, &arg.uuid_num, arg.uuids); > This can still fail, check this return and check the expected num of uuid's has not changed. Will fix this. >> + >> + /* if this is not base firmware, search for a compatible region */ >> + if (kind != XMGMT_BLP) { >> + compat_re = fpga_region_class_find(NULL, &arg, >> + xmgmt_region_match); >> + if (!compat_re) { >> + xrt_err(pdev, "failed to get compatible region"); >> + rc = -ENOENT; >> + goto failed; >> + } >> + >> + xmgmt_region_cleanup(compat_re); >> + >> + rc = xmgmt_region_program(compat_re, xclbin, dtb); >> + if (rc) { >> + xrt_err(pdev, "failed to program region"); >> + goto failed; >> + } >> + } >> + >> + /* create all the new regions contained in this xclbin */ >> + for (i = 0; i < arg.uuid_num; i++) { >> + if (compat_re && !memcmp(compat_re->compat_id, &arg.uuids[i], >> + sizeof(*compat_re->compat_id))) >> + /* region for this interface already exists */ >> + continue; >> + re = fpga_region_create(DEV(pdev), fmgr, xmgmt_get_bridges); >> + if (!re) { >> + xrt_err(pdev, "failed to create fpga region"); >> + rc = -EFAULT; >> + goto failed; >> + } >> + r_data = devm_kzalloc(DEV(pdev), sizeof(*r_data), GFP_KERNEL); >> + if (!r_data) { >> + rc = -ENOMEM; >> + fpga_region_free(re); >> + goto failed; > Failed in a loop but no cleanup of previous iterations. Will fix this. Thanks, Lizhi > > Tom > >> + } >> + r_data->pdev = pdev; >> + r_data->fregion = re; >> + r_data->grp_inst = -1; >> + memcpy(&r_data->intf_uuid, &arg.uuids[i], >> + sizeof(r_data->intf_uuid)); >> + if (compat_re) { >> + memcpy(&r_data->dep_uuid, compat_re->compat_id, >> + sizeof(r_data->intf_uuid)); >> + } >> + r_data->fbridge = xmgmt_create_bridge(pdev, dtb); >> + if (!r_data->fbridge) { >> + xrt_err(pdev, "failed to create fpga bridge"); >> + rc = -EFAULT; >> + devm_kfree(DEV(pdev), r_data); >> + fpga_region_free(re); >> + goto failed; >> + } >> + >> + re->compat_id = (struct fpga_compat_id *)&r_data->intf_uuid; >> + re->priv = r_data; >> + >> + rc = fpga_region_register(re); >> + if (rc) { >> + xrt_err(pdev, "failed to register fpga region"); >> + xmgmt_destroy_bridge(r_data->fbridge); >> + fpga_region_free(re); >> + devm_kfree(DEV(pdev), r_data); >> + goto failed; >> + } >> + >> + xrt_info(pdev, "created fpga region %llx%llx", >> + re->compat_id->id_l, re->compat_id->id_h); >> + } >> + >> +failed: >> + if (compat_re) >> + put_device(&compat_re->dev); >> + >> + if (rc) { >> + if (compat_re) >> + xmgmt_region_cleanup(compat_re); >> + } >> + >> + if (dtb) >> + vfree(dtb); >> + >> + return rc; >> +}
Hi Moritz, On 03/02/2021 07:14 AM, Moritz Fischer wrote: > > On Mon, Mar 01, 2021 at 04:25:37PM -0800, Lizhi Hou wrote: >> Hi Tom， >> >> >> On 02/28/2021 08:54 AM, Tom Rix wrote: >>> CAUTION: This message has originated from an External Source. Please use proper judgment and caution when opening attachments, clicking links, or responding to this email. >>> >>> >>> On 2/26/21 1:23 PM, Lizhi Hou wrote: >>>> Hi Tom, >>>> >>>> >>> snip >>> >>>>> I also do not see a pragma pack, usually this is set of 1 so the compiler does not shuffle elements, increase size etc. >>>> This data structure is shared with other tools. And the structure is well defined with reasonable alignment. It is compatible with all compilers we have tested. So pragma pack is not necessary. >>> You can not have possibly tested all the configurations since the kernel supports many arches and compilers. >>> >>> If the tested existing alignment is ok, pragma pack should be a noop on your tested configurations. >>> >>> And help cover the untested configurations. >> Got it. I will add pragma pack(1). > Please do not use pragma pack(), add __packed to the structs in > question. Ok, I will use __packed. Thanks, Lizhi > > - Moritz
Hi Tom, On 03/01/2021 11:01 AM, Tom Rix wrote: > On 2/17/21 10:40 PM, Lizhi Hou wrote: >> Add VSEC driver. VSEC is a hardware function discovered by walking >> PCI Express configure space. A platform device node will be created >> for it. VSEC provides board logic UUID and few offset of other hardware >> functions. > Is this vsec walking infra or is a general find a list of mmio regions that need to be mapped in and do the mapping in as a set of platform drivers ? vsec is pointed by PCIe vender-specific capability. And vsec itself locates on PCI BAR. vsec has a list of minimum IPs (mmio regions) required for driver to load firmware and communicate with the other pcie function. After firmware is loaded, xrt will look into the fireware metadata to get the information of rest IPs. vsec driver notifies the root driver for the list of minimum IPs been discovered. Then the root driver will create platform device nodes and bring up drivers based on vsec's notification. >> Signed-off-by: Sonal Santan <sonal.santan@xilinx.com> >> Signed-off-by: Max Zhen <max.zhen@xilinx.com> >> Signed-off-by: Lizhi Hou <lizhih@xilinx.com> >> --- >> drivers/fpga/xrt/lib/xleaf/vsec.c | 359 ++++++++++++++++++++++++++++++ >> 1 file changed, 359 insertions(+) >> create mode 100644 drivers/fpga/xrt/lib/xleaf/vsec.c >> >> diff --git a/drivers/fpga/xrt/lib/xleaf/vsec.c b/drivers/fpga/xrt/lib/xleaf/vsec.c >> new file mode 100644 >> index 000000000000..8e5cb22522ec >> --- /dev/null >> +++ b/drivers/fpga/xrt/lib/xleaf/vsec.c >> @@ -0,0 +1,359 @@ >> +// SPDX-License-Identifier: GPL-2.0 >> +/* >> + * Xilinx Alveo FPGA VSEC Driver >> + * >> + * Copyright (C) 2020-2021 Xilinx, Inc. >> + * >> + * Authors: >> + * Lizhi Hou<Lizhi.Hou@xilinx.com> >> + */ >> + >> +#include <linux/platform_device.h> >> +#include "metadata.h" >> +#include "xleaf.h" >> + >> +#define XRT_VSEC "xrt_vsec" >> + >> +#define VSEC_TYPE_UUID 0x50 >> +#define VSEC_TYPE_FLASH 0x51 >> +#define VSEC_TYPE_PLATINFO 0x52 >> +#define VSEC_TYPE_MAILBOX 0x53 >> +#define VSEC_TYPE_END 0xff > Type of devices, this list can not grow much. Because vsec only contains minimum required IPs for loading firmware and communication. The list will only change when there is major hardware change. >> + >> +#define VSEC_UUID_LEN 16 >> + >> +struct xrt_vsec_header { >> + u32 format; >> + u32 length; >> + u32 entry_sz; >> + u32 rsvd; >> +} __packed; >> + >> +#define head_rd(g, r) \ >> + ioread32((void *)(g)->base + offsetof(struct xrt_vsec_header, r)) >> + >> +#define GET_BAR(entry) (((entry)->bar_rev >> 4) & 0xf) >> +#define GET_BAR_OFF(_entry) \ >> + ({ typeof(_entry) entry = (_entry); \ >> + ((entry)->off_lo | ((u64)(entry)->off_hi << 16)); }) > A 48 bit value stored in xrt_md_endpoint.bar_off (long) > > bar_off should be u64 Will fix this. > >> +#define GET_REV(entry) ((entry)->bar_rev & 0xf) >> + > I prefer functions over macros. Will change to inline function. >> +struct xrt_vsec_entry { >> + u8 type; >> + u8 bar_rev; >> + u16 off_lo; >> + u32 off_hi; >> + u8 ver_type; >> + u8 minor; >> + u8 major; >> + u8 rsvd0; >> + u32 rsvd1; >> +} __packed; >> + >> +#define read_entry(g, i, e) \ >> + do { \ >> + u32 *p = (u32 *)((g)->base + \ >> + sizeof(struct xrt_vsec_header) + \ >> + (i) * sizeof(struct xrt_vsec_entry)); \ >> + u32 off; \ >> + for (off = 0; \ >> + off < sizeof(struct xrt_vsec_entry) / 4; \ >> + off++) \ >> + *((u32 *)(e) + off) = ioread32(p + off);\ >> + } while (0) > This could be a static inline func. Will change to inline function. >> + >> +struct vsec_device { >> + u8 type; >> + char *ep_name; >> + ulong size; >> + char *regmap; >> +}; >> + >> +static struct vsec_device vsec_devs[] = { >> + { >> + .type = VSEC_TYPE_UUID, >> + .ep_name = XRT_MD_NODE_BLP_ROM, >> + .size = VSEC_UUID_LEN, >> + .regmap = "vsec-uuid", >> + }, >> + { >> + .type = VSEC_TYPE_FLASH, >> + .ep_name = XRT_MD_NODE_FLASH_VSEC, >> + .size = 4096, >> + .regmap = "vsec-flash", >> + }, >> + { >> + .type = VSEC_TYPE_PLATINFO, >> + .ep_name = XRT_MD_NODE_PLAT_INFO, >> + .size = 4, >> + .regmap = "vsec-platinfo", >> + }, >> + { >> + .type = VSEC_TYPE_MAILBOX, >> + .ep_name = XRT_MD_NODE_MAILBOX_VSEC, >> + .size = 48, >> + .regmap = "vsec-mbx", >> + }, > This is a static list, how would a new type be added to this ? Because the list will only change when there is major hardware change, the list will be update manually if hardware introduces a new type. >> +}; >> + >> +struct xrt_vsec { >> + struct platform_device *pdev; >> + void *base; >> + ulong length; >> + >> + char *metadata; >> + char uuid[VSEC_UUID_LEN]; >> +}; >> + >> +static char *type2epname(u32 type) >> +{ >> + int i; >> + >> + for (i = 0; i < ARRAY_SIZE(vsec_devs); i++) { >> + if (vsec_devs[i].type == type) >> + return (vsec_devs[i].ep_name); >> + } >> + >> + return NULL; >> +} >> + >> +static ulong type2size(u32 type) >> +{ >> + int i; >> + >> + for (i = 0; i < ARRAY_SIZE(vsec_devs); i++) { >> + if (vsec_devs[i].type == type) >> + return (vsec_devs[i].size); >> + } >> + >> + return 0; >> +} >> + >> +static char *type2regmap(u32 type) >> +{ >> + int i; >> + >> + for (i = 0; i < ARRAY_SIZE(vsec_devs); i++) { >> + if (vsec_devs[i].type == type) >> + return (vsec_devs[i].regmap); >> + } >> + >> + return NULL; >> +} >> + >> +static int xrt_vsec_add_node(struct xrt_vsec *vsec, >> + void *md_blob, struct xrt_vsec_entry *p_entry) >> +{ >> + struct xrt_md_endpoint ep; >> + char regmap_ver[64]; >> + int ret; >> + >> + if (!type2epname(p_entry->type)) >> + return -EINVAL; >> + >> + /* >> + * VSEC may have more than 1 mailbox instance for the card >> + * which has more than 1 physical function. >> + * This is not supported for now. Assuming only one mailbox >> + */ > are multiple uuid types allowed ? No. And there will be only one uuid in vsec list. > > this says assume 1, but logic will recreate 1+ > > can you check if a mbx ep exists before creating ? Maybe the comment is confusing. All current Alveo boards only have one mailbox in vsec list. In theory, there could be more than 1 mailboxes in the future. And how it will present in vsec list is undetermined. > >> + >> + snprintf(regmap_ver, sizeof(regmap_ver) - 1, "%d-%d.%d.%d", >> + p_entry->ver_type, p_entry->major, p_entry->minor, >> + GET_REV(p_entry)); >> + ep.ep_name = type2epname(p_entry->type); >> + ep.bar = GET_BAR(p_entry); >> + ep.bar_off = GET_BAR_OFF(p_entry); > here is the bar_off type overlow Will fix it. >> + ep.size = type2size(p_entry->type); >> + ep.regmap = type2regmap(p_entry->type); >> + ep.regmap_ver = regmap_ver; >> + ret = xrt_md_add_endpoint(DEV(vsec->pdev), vsec->metadata, &ep); >> + if (ret) { >> + xrt_err(vsec->pdev, "add ep failed, ret %d", ret); >> + goto failed; >> + } >> + >> +failed: >> + return ret; >> +} >> + >> +static int xrt_vsec_create_metadata(struct xrt_vsec *vsec) >> +{ >> + struct xrt_vsec_entry entry; >> + int i, ret; >> + >> + ret = xrt_md_create(&vsec->pdev->dev, &vsec->metadata); >> + if (ret) { >> + xrt_err(vsec->pdev, "create metadata failed"); >> + return ret; >> + } >> + >> + for (i = 0; i * sizeof(entry) < vsec->length - >> + sizeof(struct xrt_vsec_header); i++) { >> + read_entry(vsec, i, &entry); >> + xrt_vsec_add_node(vsec, vsec->metadata, &entry); > This can fail. Will add check. >> + } >> + >> + return 0; >> +} >> + >> +static int xrt_vsec_ioctl(struct platform_device *pdev, u32 cmd, void *arg) >> +{ >> + int ret = 0; >> + >> + switch (cmd) { >> + case XRT_XLEAF_EVENT: >> + /* Does not handle any event. */ >> + break; >> + default: >> + ret = -EINVAL; >> + xrt_err(pdev, "should never been called"); >> + break; >> + } > This function looks like a noop. Is anything going to be added to this later ? It could be. And there are broadcast events can reach to this handler. I think it is harmless to ignore and return. >> + >> + return ret; >> +} >> + >> +static int xrt_vsec_mapio(struct xrt_vsec *vsec) >> +{ >> + struct xrt_subdev_platdata *pdata = DEV_PDATA(vsec->pdev); >> + const u32 *bar; >> + const u64 *bar_off; >> + struct resource *res = NULL; >> + ulong addr; >> + int ret; >> + >> + if (!pdata || xrt_md_size(DEV(vsec->pdev), pdata->xsp_dtb) == XRT_MD_INVALID_LENGTH) { >> + xrt_err(vsec->pdev, "empty metadata"); >> + return -EINVAL; >> + } >> + >> + ret = xrt_md_get_prop(DEV(vsec->pdev), pdata->xsp_dtb, XRT_MD_NODE_VSEC, >> + NULL, XRT_MD_PROP_BAR_IDX, (const void **)&bar, NULL); >> + if (ret) { >> + xrt_err(vsec->pdev, "failed to get bar idx, ret %d", ret); >> + return -EINVAL; >> + } >> + >> + ret = xrt_md_get_prop(DEV(vsec->pdev), pdata->xsp_dtb, XRT_MD_NODE_VSEC, >> + NULL, XRT_MD_PROP_OFFSET, (const void **)&bar_off, NULL); >> + if (ret) { >> + xrt_err(vsec->pdev, "failed to get bar off, ret %d", ret); >> + return -EINVAL; >> + } >> + >> + xrt_info(vsec->pdev, "Map vsec at bar %d, offset 0x%llx", >> + be32_to_cpu(*bar), be64_to_cpu(*bar_off)); >> + >> + xleaf_get_barres(vsec->pdev, &res, be32_to_cpu(*bar)); >> + if (!res) { >> + xrt_err(vsec->pdev, "failed to get bar addr"); >> + return -EINVAL; >> + } >> + >> + addr = res->start + (ulong)be64_to_cpu(*bar_off); > review this type, addr is ulong and bar_off is not. Will use u64. >> + >> + vsec->base = ioremap(addr, sizeof(struct xrt_vsec_header)); >> + if (!vsec->base) { >> + xrt_err(vsec->pdev, "Map header failed"); >> + return -EIO; >> + } > why the double call on ioremap ? > > just do the last one. The first ioremap only maps in the header and read out the length of the body (mmio list). Then the next ioremap maps in the body based on the length. > >> + >> + vsec->length = head_rd(vsec, length); >> + iounmap(vsec->base); >> + vsec->base = ioremap(addr, vsec->length); >> + if (!vsec->base) { >> + xrt_err(vsec->pdev, "map failed"); >> + return -EIO; >> + } >> + >> + return 0; >> +} >> + >> +static int xrt_vsec_remove(struct platform_device *pdev) >> +{ >> + struct xrt_vsec *vsec; >> + >> + vsec = platform_get_drvdata(pdev); >> + >> + if (vsec->base) { >> + iounmap(vsec->base); >> + vsec->base = NULL; >> + } >> + >> + vfree(vsec->metadata); >> + >> + return 0; >> +} >> + >> +static int xrt_vsec_probe(struct platform_device *pdev) >> +{ >> + struct xrt_vsec *vsec; >> + int ret = 0; >> + >> + vsec = devm_kzalloc(&pdev->dev, sizeof(*vsec), GFP_KERNEL); >> + if (!vsec) >> + return -ENOMEM; >> + >> + vsec->pdev = pdev; >> + platform_set_drvdata(pdev, vsec); >> + >> + ret = xrt_vsec_mapio(vsec); >> + if (ret) >> + goto failed; >> + >> + ret = xrt_vsec_create_metadata(vsec); >> + if (ret) { >> + xrt_err(pdev, "create metadata failed, ret %d", ret); >> + goto failed; >> + } >> + ret = xleaf_create_group(pdev, vsec->metadata); >> + if (ret < 0) >> + xrt_err(pdev, "create group failed, ret %d", ret); >> + else >> + ret = 0; > why is it just > > if (ret) > > fail ? xleaf_create_group() returns 0 or positive id on success. I will change to if (ret < 0) goto fail; return 0 fail: Thanks, Lizhi > > Tom > >> + >> +failed: >> + if (ret) >> + xrt_vsec_remove(pdev); >> + >> + return ret; >> +} >> + >> +static struct xrt_subdev_endpoints xrt_vsec_endpoints[] = { >> + { >> + .xse_names = (struct xrt_subdev_ep_names []){ >> + { .ep_name = XRT_MD_NODE_VSEC }, >> + { NULL }, >> + }, >> + .xse_min_ep = 1, >> + }, >> + { 0 }, >> +}; >> + >> +static struct xrt_subdev_drvdata xrt_vsec_data = { >> + .xsd_dev_ops = { >> + .xsd_ioctl = xrt_vsec_ioctl, >> + }, >> +}; >> + >> +static const struct platform_device_id xrt_vsec_table[] = { >> + { XRT_VSEC, (kernel_ulong_t)&xrt_vsec_data }, >> + { }, >> +}; >> + >> +static struct platform_driver xrt_vsec_driver = { >> + .driver = { >> + .name = XRT_VSEC, >> + }, >> + .probe = xrt_vsec_probe, >> + .remove = xrt_vsec_remove, >> + .id_table = xrt_vsec_table, >> +}; >> + >> +void vsec_leaf_init_fini(bool init) >> +{ >> + if (init) >> + xleaf_register_driver(XRT_SUBDEV_VSEC, &xrt_vsec_driver, xrt_vsec_endpoints); >> + else >> + xleaf_unregister_driver(XRT_SUBDEV_VSEC); >> +}
Hi Moritz, On 02/21/2021 10:33 AM, Moritz Fischer wrote: > On Sun, Feb 21, 2021 at 09:12:37AM -0800, Tom Rix wrote: >> On 2/17/21 10:40 PM, Lizhi Hou wrote: >>> Alveo FPGA firmware and partial reconfigure file are in xclbin format. >> This code enumerates and extracts >>> Add >>> code to enumerate and extract sections from xclbin files. xclbin.h is cross >>> platform and used across all platforms and OS >>> >>> Signed-off-by: Sonal Santan <sonal.santan@xilinx.com> >>> Signed-off-by: Max Zhen <max.zhen@xilinx.com> >>> Signed-off-by: Lizhi Hou <lizhih@xilinx.com> >>> --- >>> drivers/fpga/xrt/include/xclbin-helper.h | 52 +++ >>> drivers/fpga/xrt/lib/xclbin.c | 394 ++++++++++++++++++++++ >>> include/uapi/linux/xrt/xclbin.h | 408 +++++++++++++++++++++++ >>> 3 files changed, 854 insertions(+) >>> create mode 100644 drivers/fpga/xrt/include/xclbin-helper.h >>> create mode 100644 drivers/fpga/xrt/lib/xclbin.c >>> create mode 100644 include/uapi/linux/xrt/xclbin.h >>> >>> diff --git a/drivers/fpga/xrt/include/xclbin-helper.h b/drivers/fpga/xrt/include/xclbin-helper.h >>> new file mode 100644 >>> index 000000000000..68218efc9d0b >>> --- /dev/null >>> +++ b/drivers/fpga/xrt/include/xclbin-helper.h >>> @@ -0,0 +1,52 @@ >>> +/* SPDX-License-Identifier: GPL-2.0 */ >>> +/* >>> + * Header file for Xilinx Runtime (XRT) driver >>> + * >>> + * Copyright (C) 2020-2021 Xilinx, Inc. >>> + * >>> + * Authors: >>> + * David Zhang <davidzha@xilinx.com> >>> + * Sonal Santan <sonal.santan@xilinx.com> >>> + */ >>> + >>> +#ifndef _XRT_XCLBIN_H >>> +#define _XRT_XCLBIN_H >> The header guard should match the filename. >> >>> + >>> +#include <linux/types.h> >>> +#include <linux/device.h> >>> +#include <linux/xrt/xclbin.h> >>> + >>> +#define ICAP_XCLBIN_V2 "xclbin2" >>> +#define DMA_HWICAP_BITFILE_BUFFER_SIZE 1024 >>> +#define MAX_XCLBIN_SIZE (1024 * 1024 * 1024) /* Assuming xclbin <= 1G, always */ >> #defines should have a prefix, maybe XRT_ or XCLBIN_ >>> + >>> +enum axlf_section_kind; >>> +struct axlf; >>> + >>> +/** >>> + * Bitstream header information as defined by Xilinx tools. >>> + * Please note that this struct definition is not owned by the driver. >>> + */ >>> +struct hw_icap_bit_header { >> File headers usually have fixed length fields like uint32_t >> >> Is this a structure the real header is converted into ? >> >>> + unsigned int header_length; /* Length of header in 32 bit words */ >>> + unsigned int bitstream_length; /* Length of bitstream to read in bytes*/ >>> + unsigned char *design_name; /* Design name get from bitstream */ >>> + unsigned char *part_name; /* Part name read from bitstream */ >>> + unsigned char *date; /* Date read from bitstream header */ >>> + unsigned char *time; /* Bitstream creation time */ >>> + unsigned int magic_length; /* Length of the magic numbers */ >>> + unsigned char *version; /* Version string */ >>> +}; >>> + >>> +const char *xrt_xclbin_kind_to_string(enum axlf_section_kind kind); >> Only add decl's that are using in multiple files. >> >> This is only defined in xclbin.c, why does it need to be in the header ? >> >>> +int xrt_xclbin_get_section(const struct axlf *xclbin, >>> + enum axlf_section_kind kind, void **data, >>> + uint64_t *len); >>> +int xrt_xclbin_get_metadata(struct device *dev, const struct axlf *xclbin, char **dtb); >>> +int xrt_xclbin_parse_bitstream_header(const unsigned char *data, >>> + unsigned int size, >>> + struct hw_icap_bit_header *header); >>> +void xrt_xclbin_free_header(struct hw_icap_bit_header *header); >>> +const char *xrt_clock_type2epname(enum CLOCK_TYPE type); >> CLOCK_TYPE needs a prefix, something like XCLBIN_CLOCK_TYPE >>> + >>> +#endif /* _XRT_XCLBIN_H */ >>> diff --git a/drivers/fpga/xrt/lib/xclbin.c b/drivers/fpga/xrt/lib/xclbin.c >>> new file mode 100644 >>> index 000000000000..47dc6ca25c1b >>> --- /dev/null >>> +++ b/drivers/fpga/xrt/lib/xclbin.c >>> @@ -0,0 +1,394 @@ >>> +// SPDX-License-Identifier: GPL-2.0 >>> +/* >>> + * Xilinx Alveo FPGA Driver XCLBIN parser >>> + * >>> + * Copyright (C) 2020-2021 Xilinx, Inc. >>> + * >>> + * Authors: David Zhang <davidzha@xilinx.com> >>> + */ >>> + >>> +#include <asm/errno.h> >>> +#include <linux/vmalloc.h> >>> +#include <linux/device.h> >>> +#include "xclbin-helper.h" >>> +#include "metadata.h" >>> + >> What is XHI ? Maybe expand this, at the lease should comment >>> +/* Used for parsing bitstream header */ >>> +#define XHI_EVEN_MAGIC_BYTE 0x0f >>> +#define XHI_ODD_MAGIC_BYTE 0xf0 >>> + >>> +/* Extra mode for IDLE */ >>> +#define XHI_OP_IDLE -1 >>> +#define XHI_BIT_HEADER_FAILURE -1 >>> + >>> +/* The imaginary module length register */ >>> +#define XHI_MLR 15 >>> + >>> +static inline unsigned char xhi_data_and_inc(const unsigned char *d, int *i, int sz) >> could move to the *.h >>> +{_ >>> + unsigned char data; >>> + >>> + if (*i >= sz) >>> + return -1; >> The return value of this funtion is not always checked, at the least add a dev_err here >>> + >>> + data = d[*i]; >>> + (*i)++; >>> + >>> + return data; >>> +} >>> + >>> +static const struct axlf_section_header * >>> +xrt_xclbin_get_section_hdr(const struct axlf *xclbin, >>> + enum axlf_section_kind kind) >>> +{ >>> + int i = 0; >>> + >>> + for (i = 0; i < xclbin->m_header.m_numSections; i++) { >>> + if (xclbin->m_sections[i].m_sectionKind == kind) >>> + return &xclbin->m_sections[i]; >>> + } >>> + >>> + return NULL; >>> +} >>> + >>> +static int >>> +xrt_xclbin_check_section_hdr(const struct axlf_section_header *header, >>> + u64 xclbin_len) >>> +{ >>> + int ret; >>> + >>> + ret = (header->m_sectionOffset + header->m_sectionSize) > xclbin_len ? -EINVAL : 0; >> Tristate is harder to read, consider replacing with if() >> >> int ret = 0 >> >> if () >> >> ret = > Why not just: > > if (header->m_section_offset + header->m_section_size) > return -EINVAL; > > return 0; > > Also please fix the camelCase throughout the entire patchset. Will fix both. >> >>> + >>> + return ret; >>> +} >>> + >>> +static int xrt_xclbin_section_info(const struct axlf *xclbin, >>> + enum axlf_section_kind kind, >>> + u64 *offset, u64 *size) >>> +{ >>> + const struct axlf_section_header *mem_header = NULL; >>> + u64 xclbin_len; >>> + int err = 0; >>> + >>> + mem_header = xrt_xclbin_get_section_hdr(xclbin, kind); >>> + if (!mem_header) >>> + return -EINVAL; >>> + >>> + xclbin_len = xclbin->m_header.m_length; >>> + if (xclbin_len > MAX_XCLBIN_SIZE) >>> + return -EINVAL; >> This check can be added to the function call.. >> >> or the sanity checking added to the earier call to *get_section_hdr >> >> There a number of small functions that can be combined. >> >>> + >>> + err = xrt_xclbin_check_section_hdr(mem_header, xclbin_len); >>> + if (err) >>> + return err; >>> + >>> + *offset = mem_header->m_sectionOffset; >>> + *size = mem_header->m_sectionSize; >>> + >>> + return 0; >>> +} >>> + >>> +/* caller should free the allocated memory for **data */ >> must free >> >> This comment also needs to be with the *.h decl >> >>> +int xrt_xclbin_get_section(const struct axlf *buf, >>> + enum axlf_section_kind kind, >>> + void **data, u64 *len) >>> +{ >>> + const struct axlf *xclbin = (const struct axlf *)buf; >>> + void *section = NULL; >>> + int err = 0; >>> + u64 offset = 0; >>> + u64 size = 0; >>> + >>> + err = xrt_xclbin_section_info(xclbin, kind, &offset, &size); >>> + if (err) >>> + return err; >>> + >>> + section = vmalloc(size); >>> + if (!section) >>> + return -ENOMEM; >>> + >>> + memcpy(section, ((const char *)xclbin) + offset, size); >>> + >>> + *data = section; >> a general comment >> >> for exported function checking the validity of the inputs in more important. >> >> here you assume **data is valid, really you should check. >> >>> + if (len) >>> + *len = size; >> len setting being optional, needs to be in the *.h comment >>> + >>> + return 0; >>> +} >>> +EXPORT_SYMBOL_GPL(xrt_xclbin_get_section); >>> + >> Instead of allocating new memory and making copies of bits of *data >> >> why not have the points reference data ? >> >> The size operations look like translating big endian data to little endian. >> >> This will break on a big endian host. >> >>> +/* parse bitstream header */ >>> +int xrt_xclbin_parse_bitstream_header(const unsigned char *data, >>> + unsigned int size, >>> + struct hw_icap_bit_header *header) >>> +{ >>> + unsigned int index; >>> + unsigned int len; >>> + unsigned int tmp; >>> + unsigned int i; >>> + >>> + memset(header, 0, sizeof(*header)); >>> + /* Start Index at start of bitstream */ >>> + index = 0; >>> + >>> + /* Initialize HeaderLength. If header returned early inidicates >>> + * failure. >> This side effect should be documented in the *.h comment. >> >> Also the multi line comment is a bit weird, not sure if it is ok >> >>> + */ >>> + header->header_length = XHI_BIT_HEADER_FAILURE; >>> + >>> + /* Get "Magic" length */ >>> + header->magic_length = xhi_data_and_inc(data, &index, size); >>> + header->magic_length = (header->magic_length << 8) | xhi_data_and_inc(data, &index, size); >>> + >>> + /* Read in "magic" */ >>> + for (i = 0; i < header->magic_length - 1; i++) { >>> + tmp = xhi_data_and_inc(data, &index, size); >>> + if (i % 2 == 0 && tmp != XHI_EVEN_MAGIC_BYTE) > if !(i % 2) ... Will change it. >>> + return -1; /* INVALID_FILE_HEADER_ERROR */ >>> + >>> + if (i % 2 == 1 && tmp != XHI_ODD_MAGIC_BYTE) >>> + return -1; /* INVALID_FILE_HEADER_ERROR */ >>> + } >>> + >>> + /* Read null end of magic data. */ >>> + tmp = xhi_data_and_inc(data, &index, size); >>> + >>> + /* Read 0x01 (short) */ >>> + tmp = xhi_data_and_inc(data, &index, size); >>> + tmp = (tmp << 8) | xhi_data_and_inc(data, &index, size); >>> + >>> + /* Check the "0x01" half word */ >>> + if (tmp != 0x01) >>> + return -1; /* INVALID_FILE_HEADER_ERROR */ >>> + >>> + /* Read 'a' */ >>> + tmp = xhi_data_and_inc(data, &index, size); >>> + if (tmp != 'a') >>> + return -1; /* INVALID_FILE_HEADER_ERROR */ >>> + >>> + /* Get Design Name length */ >>> + len = xhi_data_and_inc(data, &index, size); >>> + len = (len << 8) | xhi_data_and_inc(data, &index, size); >>> + >>> + /* allocate space for design name and final null character. */ >>> + header->design_name = vmalloc(len); >>> + if (!header->design_name) >>> + return -ENOMEM; >>> + >>> + /* Read in Design Name */ >>> + for (i = 0; i < len; i++) >>> + header->design_name[i] = xhi_data_and_inc(data, &index, size); >>> + >>> + if (header->design_name[len - 1] != '\0') >>> + return -1; >>> + >>> + header->version = strstr(header->design_name, "Version=") + strlen("Version="); >>> + >>> + /* Read 'b' */ >>> + tmp = xhi_data_and_inc(data, &index, size); >>> + if (tmp != 'b') >>> + return -1; /* INVALID_FILE_HEADER_ERROR */ >>> + >>> + /* Get Part Name length */ >>> + len = xhi_data_and_inc(data, &index, size); >>> + len = (len << 8) | xhi_data_and_inc(data, &index, size); >>> + >>> + /* allocate space for part name and final null character. */ >>> + header->part_name = vmalloc(len); >>> + if (!header->part_name) >>> + return -ENOMEM; >>> + >>> + /* Read in part name */ >>> + for (i = 0; i < len; i++) >>> + header->part_name[i] = xhi_data_and_inc(data, &index, size); >>> + >>> + if (header->part_name[len - 1] != '\0') >>> + return -1; >>> + >>> + /* Read 'c' */ >>> + tmp = xhi_data_and_inc(data, &index, size); >>> + if (tmp != 'c') >>> + return -1; /* INVALID_FILE_HEADER_ERROR */ >>> + >>> + /* Get date length */ >>> + len = xhi_data_and_inc(data, &index, size); >>> + len = (len << 8) | xhi_data_and_inc(data, &index, size); >>> + >>> + /* allocate space for date and final null character. */ >>> + header->date = vmalloc(len); >>> + if (!header->date) >>> + return -ENOMEM; >>> + >>> + /* Read in date name */ >>> + for (i = 0; i < len; i++) >>> + header->date[i] = xhi_data_and_inc(data, &index, size); >>> + >>> + if (header->date[len - 1] != '\0') >>> + return -1; >> generally -EINVAL is more meaningful than -1 >>> + >>> + /* Read 'd' */ >>> + tmp = xhi_data_and_inc(data, &index, size); >>> + if (tmp != 'd') >>> + return -1; /* INVALID_FILE_HEADER_ERROR */ >>> + >>> + /* Get time length */ >>> + len = xhi_data_and_inc(data, &index, size); >>> + len = (len << 8) | xhi_data_and_inc(data, &index, size); >>> + >>> + /* allocate space for time and final null character. */ >>> + header->time = vmalloc(len); >>> + if (!header->time) >>> + return -ENOMEM; >>> + >>> + /* Read in time name */ >>> + for (i = 0; i < len; i++) >>> + header->time[i] = xhi_data_and_inc(data, &index, size); >>> + >>> + if (header->time[len - 1] != '\0') >>> + return -1; >>> + >>> + /* Read 'e' */ >>> + tmp = xhi_data_and_inc(data, &index, size); >>> + if (tmp != 'e') >>> + return -1; /* INVALID_FILE_HEADER_ERROR */ >>> + >>> + /* Get byte length of bitstream */ >>> + header->bitstream_length = xhi_data_and_inc(data, &index, size); >>> + header->bitstream_length = (header->bitstream_length << 8) | >>> + xhi_data_and_inc(data, &index, size); >>> + header->bitstream_length = (header->bitstream_length << 8) | >>> + xhi_data_and_inc(data, &index, size); >>> + header->bitstream_length = (header->bitstream_length << 8) | >>> + xhi_data_and_inc(data, &index, size); >> generally a problem >> >> This is confusing, collect the bytes in a temp[] and construct the header->bitstream_length in on statement. >> >> This is a case where xhi_data_and_inc return is not checked and if it failed could blow up later. >> >>> + >>> + header->header_length = index; >> index is not a good variable name if it going to be stored as a length. >> >> consider changing it to something like current_length. >> >>> + >>> + return 0; >>> +} >>> +EXPORT_SYMBOL_GPL(xrt_xclbin_parse_bitstream_header); >>> + >>> +void xrt_xclbin_free_header(struct hw_icap_bit_header *header) >>> +{ >>> + vfree(header->design_name); >>> + vfree(header->part_name); >>> + vfree(header->date); >>> + vfree(header->time); >> missing header->version >>> +} >>> +EXPORT_SYMBOL_GPL(xrt_xclbin_free_header); >>> + >>> +struct xrt_clock_desc { >>> + char *clock_ep_name; >>> + u32 clock_xclbin_type; >>> + char *clkfreq_ep_name; >>> +} clock_desc[] = { >>> + { >>> + .clock_ep_name = XRT_MD_NODE_CLK_KERNEL1, >>> + .clock_xclbin_type = CT_DATA, >>> + .clkfreq_ep_name = XRT_MD_NODE_CLKFREQ_K1, >>> + }, >>> + { >>> + .clock_ep_name = XRT_MD_NODE_CLK_KERNEL2, >>> + .clock_xclbin_type = CT_KERNEL, >>> + .clkfreq_ep_name = XRT_MD_NODE_CLKFREQ_K2, >>> + }, >>> + { >>> + .clock_ep_name = XRT_MD_NODE_CLK_KERNEL3, >>> + .clock_xclbin_type = CT_SYSTEM, >>> + .clkfreq_ep_name = XRT_MD_NODE_CLKFREQ_HBM, >>> + }, >>> +}; >>> + >>> +const char *xrt_clock_type2epname(enum CLOCK_TYPE type) >>> +{ >>> + int i; >>> + >>> + for (i = 0; i < ARRAY_SIZE(clock_desc); i++) { >>> + if (clock_desc[i].clock_xclbin_type == type) >>> + return clock_desc[i].clock_ep_name; >>> + } >>> + return NULL; >>> +} >>> +EXPORT_SYMBOL_GPL(xrt_clock_type2epname); >> What is clock stuff doing in xclbin ? >> >> I think clock needs its own file >> >>> + >>> +static const char *clock_type2clkfreq_name(u32 type) >>> +{ >>> + int i; >>> + >>> + for (i = 0; i < ARRAY_SIZE(clock_desc); i++) { >>> + if (clock_desc[i].clock_xclbin_type == type) >>> + return clock_desc[i].clkfreq_ep_name; >>> + } >>> + return NULL; >>> +} >>> + >>> +static int xrt_xclbin_add_clock_metadata(struct device *dev, >>> + const struct axlf *xclbin, >>> + char *dtb) >>> +{ >>> + int i; >>> + u16 freq; >>> + struct clock_freq_topology *clock_topo; >>> + int rc = xrt_xclbin_get_section(xclbin, CLOCK_FREQ_TOPOLOGY, >>> + (void **)&clock_topo, NULL); >>> + >>> + if (rc) >>> + return 0; >> failing is ok ? >>> + >>> + for (i = 0; i < clock_topo->m_count; i++) { >>> + u8 type = clock_topo->m_clock_freq[i].m_type; >>> + const char *ep_name = xrt_clock_type2epname(type); >>> + const char *counter_name = clock_type2clkfreq_name(type); >>> + >>> + if (!ep_name || !counter_name) >>> + continue; >>> + >>> + freq = cpu_to_be16(clock_topo->m_clock_freq[i].m_freq_Mhz); >>> + rc = xrt_md_set_prop(dev, dtb, ep_name, NULL, XRT_MD_PROP_CLK_FREQ, >>> + &freq, sizeof(freq)); >>> + if (rc) >>> + break; >>> + >>> + rc = xrt_md_set_prop(dev, dtb, ep_name, NULL, XRT_MD_PROP_CLK_CNT, >>> + counter_name, strlen(counter_name) + 1); >>> + if (rc) >>> + break; >> Failing in a loop, why isn't there some cleanup of the *set_prop() calls ? >>> + } >>> + >>> + vfree(clock_topo); >>> + >>> + return rc; >>> +} >>> + >>> +int xrt_xclbin_get_metadata(struct device *dev, const struct axlf *xclbin, char **dtb) >>> +{ >>> + char *md = NULL, *newmd = NULL; >>> + u64 len; >> *dtb = NULL; >>> + int rc = xrt_xclbin_get_section(xclbin, PARTITION_METADATA, >>> + (void **)&md, &len); >>> + >>> + if (rc) >>> + goto done; >>> + >>> + /* Sanity check the dtb section. */ >>> + if (xrt_md_size(dev, md) > len) { >>> + rc = -EINVAL; >>> + goto done; >>> + } >>> + >>> + newmd = xrt_md_dup(dev, md); >>> + if (!newmd) { >>> + rc = -EFAULT; >>> + goto done; >>> + } >>> + /* Convert various needed xclbin sections into dtb. */ >>> + rc = xrt_xclbin_add_clock_metadata(dev, xclbin, newmd); >> newmd is only valid here, but the above error handling jump here. change this to >> >> if (!rc) >> >> *dtb = newmd >> >> else >> >> vfree(newmd) >> >> done: >> >> vfree(md) >> >> return rc; >> >>> + >>> +done: >>> + if (rc == 0) >>> + *dtb = newmd; >>> + else >>> + vfree(newmd); >>> + vfree(md); >>> + return rc; >>> +} >>> +EXPORT_SYMBOL_GPL(xrt_xclbin_get_metadata); >>> diff --git a/include/uapi/linux/xrt/xclbin.h b/include/uapi/linux/xrt/xclbin.h >>> new file mode 100644 >>> index 000000000000..53f140123ef1 >>> --- /dev/null >>> +++ b/include/uapi/linux/xrt/xclbin.h >>> @@ -0,0 +1,408 @@ >>> +/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */ >>> +/* >>> + * Xilinx FPGA compiled binary container format >>> + * >>> + * Copyright (C) 2015-2021, Xilinx Inc >>> + */ >>> + >>> +#ifndef _XCLBIN_H_ >>> +#define _XCLBIN_H_ >>> + >>> +#ifdef _WIN32 >> WIN32 ? >> >> Only 1 other header has this ifdef >> >>> + #include <cstdint> >>> + #include <algorithm> >> c++ is being assumed for windows >>> + #include "windows/uuid.h" >> thank you for not including windows.h ;) >>> +#else >>> + #if defined(__KERNEL__) >>> + #include <linux/types.h> >>> + #include <linux/uuid.h> >>> + #include <linux/version.h> >>> + #elif defined(__cplusplus) >>> + #include <cstdlib> >>> + #include <cstdint> >>> + #include <algorithm> >>> + #include <uuid/uuid.h> >>> + #else >>> + #include <stdlib.h> >>> + #include <stdint.h> >>> + #include <uuid/uuid.h> >>> + #endif >>> +#endif > Tbh, not a big fan of this ... We will remove WIN32 and keep __cplusplus >>> + >> Review these includes, some could be convenience includes. >> >> ex/ linux/version.h with no obvious use of version macros. >> >> struct axlf_header { >> + uint64_t m_length; /* Total size of the xclbin file */ >> .. snip .. >> + union { >> + char m_next_axlf[16]; /* Name of next xclbin file */ >> + /* in the daisy chain */ >> + uuid_t uuid; /* uuid of this xclbin*/ >> + }; >> >> As mentioned in an earlier patch, if uuid_t is larger than 16 bytes, axlf_header breaks. >> while it is convenient to have this type here, it would be better this access was handled in another way. >> Maybe a host specific function. >> >> I also do not see a pragma pack, usually this is set of 1 so the compiler does not shuffle elements, increase size etc. >> >>> +#ifdef __cplusplus >>> +extern "C" { >>> +#endif >>> + >>> +/** >>> + * DOC: Container format for Xilinx FPGA images >>> + * The container stores bitstreams, metadata and firmware images. >>> + * xclbin/xsabin is ELF-like binary container format. It is structured >> is an ELF-like file format. It is a structured >>> + * series of sections. There is a file header followed by several section >>> + * headers which is followed by sections. A section header points to an >>> + * actual section. There is an optional signature at the end. The >>> + * following figure illustrates a typical xclbin: >>> + * >>> + * +---------------------+ >>> + * | | >>> + * | HEADER | >>> + * +---------------------+ >>> + * | SECTION HEADER | >>> + * | | >>> + * +---------------------+ >>> + * | ... | >>> + * | | >>> + * +---------------------+ >>> + * | SECTION HEADER | >>> + * | | >>> + * +---------------------+ >>> + * | SECTION | >>> + * | | >>> + * +---------------------+ >>> + * | ... | >>> + * | | >>> + * +---------------------+ >>> + * | SECTION | >>> + * | | >>> + * +---------------------+ >>> + * | SIGNATURE | >>> + * | (OPTIONAL) | >>> + * +---------------------+ >> This ascii art is a mixture of tabs and spaces, for someone with tab = 2 spaces, this will look messed up. >> >> convert the tabs to spaces >> >>> + */ >>> + >>> +enum XCLBIN_MODE { >>> + XCLBIN_FLAT, >> generally >> >> all enums used in a file format should be initialized. >> >> This likely should be >> >> XCLBIN_FLAT = 0, >> >>> + XCLBIN_PR, >>> + XCLBIN_TANDEM_STAGE2, >>> + XCLBIN_TANDEM_STAGE2_WITH_PR, >>> + XCLBIN_HW_EMU, >>> + XCLBIN_SW_EMU, >>> + XCLBIN_MODE_MAX >>> +}; >>> + >>> +enum axlf_section_kind { >>> + BITSTREAM = 0, >>> + CLEARING_BITSTREAM, >>> + EMBEDDED_METADATA, >>> + FIRMWARE, >>> + DEBUG_DATA, >>> + SCHED_FIRMWARE, >>> + MEM_TOPOLOGY, >>> + CONNECTIVITY, >>> + IP_LAYOUT, >>> + DEBUG_IP_LAYOUT, >>> + DESIGN_CHECK_POINT, >>> + CLOCK_FREQ_TOPOLOGY, >>> + MCS, >>> + BMC, >>> + BUILD_METADATA, >>> + KEYVALUE_METADATA, >>> + USER_METADATA, >>> + DNA_CERTIFICATE, >>> + PDI, >>> + BITSTREAM_PARTIAL_PDI, >>> + PARTITION_METADATA, >>> + EMULATION_DATA, >>> + SYSTEM_METADATA, >>> + SOFT_KERNEL, >>> + ASK_FLASH, >>> + AIE_METADATA, >>> + ASK_GROUP_TOPOLOGY, >>> + ASK_GROUP_CONNECTIVITY >>> +}; >>> + >>> +enum MEM_TYPE { >>> + MEM_DDR3, >>> + MEM_DDR4, >>> + MEM_DRAM, >>> + MEM_STREAMING, >>> + MEM_PREALLOCATED_GLOB, >>> + MEM_ARE, >>> + MEM_HBM, >>> + MEM_BRAM, >>> + MEM_URAM, >>> + MEM_STREAMING_CONNECTION >>> +}; >>> + >>> +enum IP_TYPE { >>> + IP_MB = 0, >>> + IP_KERNEL, >>> + IP_DNASC, >>> + IP_DDR4_CONTROLLER, >>> + IP_MEM_DDR4, >>> + IP_MEM_HBM >>> +}; >>> + >>> +struct axlf_section_header { >>> + uint32_t m_sectionKind; /* Section type */ >>> + char m_sectionName[16]; /* Examples: "stage2", "clear1", */ >>> + /* "clear2", "ocl1", "ocl2, */ >>> + /* "ublaze", "sched" */ >>> + uint64_t m_sectionOffset; /* File offset of section data */ >>> + uint64_t m_sectionSize; /* Size of section data */ >>> +}; >>> + >>> +struct axlf_header { >>> + uint64_t m_length; /* Total size of the xclbin file */ >>> + uint64_t m_timeStamp; /* Number of seconds since epoch */ >>> + /* when xclbin was created */ >>> + uint64_t m_featureRomTimeStamp; /* TimeSinceEpoch of the featureRom */ >>> + uint16_t m_versionPatch; /* Patch Version */ >>> + uint8_t m_versionMajor; /* Major Version - Version: 2.1.0*/ >> i did not see the version checked earlier, which one is expected ? >>> + uint8_t m_versionMinor; /* Minor Version */ >>> + uint32_t m_mode; /* XCLBIN_MODE */ >>> + union { >>> + struct { >>> + uint64_t m_platformId; /* 64 bit platform ID: */ >>> + /* vendor-device-subvendor-subdev */ >>> + uint64_t m_featureId; /* 64 bit feature id */ >>> + } rom; >>> + unsigned char rom_uuid[16]; /* feature ROM UUID for which */ >>> + /* this xclbin was generated */ >>> + }; >>> + unsigned char m_platformVBNV[64]; /* e.g. */ >> what is VBNV? >>> + /* xilinx:xil-accel-rd-ku115:4ddr-xpr:3.4: null terminated */ >>> + union { >>> + char m_next_axlf[16]; /* Name of next xclbin file */ >>> + /* in the daisy chain */ >>> + uuid_t uuid; /* uuid of this xclbin*/ >>> + }; >>> + char m_debug_bin[16]; /* Name of binary with debug */ >>> + /* information */ >>> + uint32_t m_numSections; /* Number of section headers */ >>> +}; >>> + >>> +struct axlf { >>> + char m_magic[8]; /* Should be "xclbin2\0" */ >>> + int32_t m_signature_length; /* Length of the signature. */ >>> + /* -1 indicates no signature */ >>> + unsigned char reserved[28]; /* Note: Initialized to 0xFFs */ >>> + >>> + unsigned char m_keyBlock[256]; /* Signature for validation */ >>> + /* of binary */ >>> + uint64_t m_uniqueId; /* axlf's uniqueId, use it to */ >>> + /* skip redownload etc */ >>> + struct axlf_header m_header; /* Inline header */ >>> + struct axlf_section_header m_sections[1]; /* One or more section */ >>> + /* headers follow */ >>> +}; >>> + >>> +/* bitstream information */ >>> +struct xlnx_bitstream { >>> + uint8_t m_freq[8]; >>> + char bits[1]; >>> +}; >>> + >>> +/**** MEMORY TOPOLOGY SECTION ****/ >>> +struct mem_data { >>> + uint8_t m_type; /* enum corresponding to mem_type. */ >>> + uint8_t m_used; /* if 0 this bank is not present */ >>> + union { >>> + uint64_t m_size; /* if mem_type DDR, then size in KB; */ >>> + uint64_t route_id; /* if streaming then "route_id" */ >>> + }; >>> + union { >>> + uint64_t m_base_address;/* if DDR then the base address; */ >>> + uint64_t flow_id; /* if streaming then "flow id" */ >>> + }; >>> + unsigned char m_tag[16]; /* DDR: BANK0,1,2,3, has to be null */ >>> + /* terminated; if streaming then stream0, 1 etc */ >>> +}; >>> + >>> +struct mem_topology { >>> + int32_t m_count; /* Number of mem_data */ >>> + struct mem_data m_mem_data[1]; /* Should be sorted on mem_type */ >>> +}; >>> + >>> +/**** CONNECTIVITY SECTION ****/ >>> +/* Connectivity of each argument of Kernel. It will be in terms of argument >> This section does not make sense. >> >> Likely you mean some algorithm kernel, rather than the linux kernel. >> >>> + * index associated. For associating kernel instances with arguments and >>> + * banks, start at the connectivity section. Using the m_ip_layout_index >>> + * access the ip_data.m_name. Now we can associate this kernel instance >>> + * with its original kernel name and get the connectivity as well. This >>> + * enables us to form related groups of kernel instances. >>> + */ >>> + >>> +struct connection { >>> + int32_t arg_index; /* From 0 to n, may not be contiguous as scalars */ >>> + /* skipped */ >>> + int32_t m_ip_layout_index; /* index into the ip_layout section. */ >>> + /* ip_layout.m_ip_data[index].m_type == IP_KERNEL */ >>> + int32_t mem_data_index; /* index of the m_mem_data . Flag error is */ >>> + /* m_used false. */ >>> +}; >>> + >>> +struct connectivity { >>> + int32_t m_count; >>> + struct connection m_connection[1]; >>> +}; >>> + >>> +/**** IP_LAYOUT SECTION ****/ >>> + >>> +/* IP Kernel */ >>> +#define IP_INT_ENABLE_MASK 0x0001 >>> +#define IP_INTERRUPT_ID_MASK 0x00FE >>> +#define IP_INTERRUPT_ID_SHIFT 0x1 >>> + >>> +enum IP_CONTROL { >>> + AP_CTRL_HS = 0, >>> + AP_CTRL_CHAIN = 1, >>> + AP_CTRL_NONE = 2, >>> + AP_CTRL_ME = 3, >>> + ACCEL_ADAPTER = 4 >> assigning beyond the first is not necessary unless there are dups or gaps >>> +}; >>> + >>> +#define IP_CONTROL_MASK 0xFF00 >>> +#define IP_CONTROL_SHIFT 0x8 >>> + >>> +/* IPs on AXI lite - their types, names, and base addresses.*/ >>> +struct ip_data { >>> + uint32_t m_type; /* map to IP_TYPE enum */ >>> + union { >>> + uint32_t properties; /* Default: 32-bits to indicate ip */ >>> + /* specific property. */ >>> + /* m_type: IP_KERNEL >>> + * m_int_enable : Bit - 0x0000_0001; >>> + * m_interrupt_id : Bits - 0x0000_00FE; >>> + * m_ip_control : Bits = 0x0000_FF00; >>> + */ >>> + struct { /* m_type: IP_MEM_* */ >>> + uint16_t m_index; >>> + uint8_t m_pc_index; >>> + uint8_t unused; >>> + } indices; >>> + }; >>> + uint64_t m_base_address; >>> + uint8_t m_name[64]; /* eg Kernel name corresponding to KERNEL */ >>> + /* instance, can embed CU name in future. */ >>> +}; >>> + >>> +struct ip_layout { >>> + int32_t m_count; >>> + struct ip_data m_ip_data[1]; /* All the ip_data needs to be sorted */ >>> + /* by m_base_address. */ >> general >> >> doing the bla[1] for c++ ? >> >> Tom >> >>> +}; >>> + >>> +/*** Debug IP section layout ****/ >>> +enum DEBUG_IP_TYPE { >>> + UNDEFINED = 0, >>> + LAPC, >>> + ILA, >>> + AXI_MM_MONITOR, >>> + AXI_TRACE_FUNNEL, >>> + AXI_MONITOR_FIFO_LITE, >>> + AXI_MONITOR_FIFO_FULL, >>> + ACCEL_MONITOR, >>> + AXI_STREAM_MONITOR, >>> + AXI_STREAM_PROTOCOL_CHECKER, >>> + TRACE_S2MM, >>> + AXI_DMA, >>> + TRACE_S2MM_FULL >>> +}; >>> + >>> +struct debug_ip_data { >>> + uint8_t m_type; /* type of enum DEBUG_IP_TYPE */ >>> + uint8_t m_index_lowbyte; >>> + uint8_t m_properties; >>> + uint8_t m_major; >>> + uint8_t m_minor; >>> + uint8_t m_index_highbyte; >>> + uint8_t m_reserved[2]; >>> + uint64_t m_base_address; >>> + char m_name[128]; >>> +}; >>> + >>> +struct debug_ip_layout { >>> + uint16_t m_count; >>> + struct debug_ip_data m_debug_ip_data[1]; >>> +}; >>> + >>> +/* Supported clock frequency types */ >>> +enum CLOCK_TYPE { >>> + CT_UNUSED = 0, /* Initialized value */ >>> + CT_DATA = 1, /* Data clock */ >>> + CT_KERNEL = 2, /* Kernel clock */ >>> + CT_SYSTEM = 3 /* System Clock */ >>> +}; >>> + >>> +/* Clock Frequency Entry */ >>> +struct clock_freq { >>> + uint16_t m_freq_Mhz; /* Frequency in MHz */ >>> + uint8_t m_type; /* Clock type (enum CLOCK_TYPE) */ >>> + uint8_t m_unused[5]; /* Not used - padding */ >>> + char m_name[128]; /* Clock Name */ >>> +}; >>> + >>> +/* Clock frequency section */ >>> +struct clock_freq_topology { >>> + int16_t m_count; /* Number of entries */ >>> + struct clock_freq m_clock_freq[1]; /* Clock array */ >>> +}; >>> + >>> +/* Supported MCS file types */ >>> +enum MCS_TYPE { >>> + MCS_UNKNOWN = 0, /* Initialized value */ >>> + MCS_PRIMARY = 1, /* The primary mcs file data */ >>> + MCS_SECONDARY = 2, /* The secondary mcs file data */ >>> +}; >>> + >>> +/* One chunk of MCS data */ >>> +struct mcs_chunk { >>> + uint8_t m_type; /* MCS data type */ > just call them type, unused, offset. Drop the m_* Will remove all 'm_' Thanks, Lizhi >>> + uint8_t m_unused[7]; /* padding */ >>> + uint64_t m_offset; /* data offset from the start of */ >>> + /* the section */ >>> + uint64_t m_size; /* data size */ >>> +}; >>> + >>> +/* MCS data section */ >>> +struct mcs { >>> + int8_t m_count; /* Number of chunks */ >>> + int8_t m_unused[7]; /* padding */ >>> + struct mcs_chunk m_chunk[1]; /* MCS chunks followed by data */ >>> +}; >>> + >>> +/* bmc data section */ >>> +struct bmc { >>> + uint64_t m_offset; /* data offset from the start of */ >>> + /* the section */ >>> + uint64_t m_size; /* data size (bytes) */ >>> + char m_image_name[64]; /* Name of the image */ >>> + /* (e.g., MSP432P401R) */ >>> + char m_device_name[64]; /* Device ID (e.g., VCU1525) */ >>> + char m_version[64]; >>> + char m_md5value[33]; /* MD5 Expected Value */ >>> + /* (e.g., 56027182079c0bd621761b7dab5a27ca)*/ >>> + char m_padding[7]; /* Padding */ >>> +}; >>> + >>> +/* soft kernel data section, used by classic driver */ >>> +struct soft_kernel { >>> + /** Prefix Syntax: >>> + * mpo - member, pointer, offset >>> + * This variable represents a zero terminated string >>> + * that is offseted from the beginning of the section. >>> + * The pointer to access the string is initialized as follows: >>> + * char * pCharString = (address_of_section) + (mpo value) >>> + */ >>> + uint32_t mpo_name; /* Name of the soft kernel */ >>> + uint32_t m_image_offset; /* Image offset */ >>> + uint32_t m_image_size; /* Image size */ >>> + uint32_t mpo_version; /* Version */ >>> + uint32_t mpo_md5_value; /* MD5 checksum */ >>> + uint32_t mpo_symbol_name; /* Symbol name */ >>> + uint32_t m_num_instances; /* Number of instances */ >>> + uint8_t padding[36]; /* Reserved for future use */ >>> + uint8_t reservedExt[16]; /* Reserved for future extended data */ >>> +}; >>> + >>> +enum CHECKSUM_TYPE { >>> + CST_UNKNOWN = 0, >>> + CST_SDBM = 1, >>> + CST_LAST >>> +}; >>> + >>> +#ifdef __cplusplus >>> +} >>> +#endif >>> + >>> +#endif > I'll take a closer look, these were just random things I bumped into. > > - Moritz
On 2/17/21 10:40 PM, Lizhi Hou wrote: > Add partition isolation platform driver. partition isolation is > a hardware function discovered by walking firmware metadata. > A platform device node will be created for it. Partition isolation > function isolate the different fpga regions > > Signed-off-by: Sonal Santan <sonal.santan@xilinx.com> > Signed-off-by: Max Zhen <max.zhen@xilinx.com> > Signed-off-by: Lizhi Hou <lizhih@xilinx.com> > --- > drivers/fpga/xrt/include/xleaf/axigate.h | 25 ++ > drivers/fpga/xrt/lib/xleaf/axigate.c | 298 +++++++++++++++++++++++ > 2 files changed, 323 insertions(+) > create mode 100644 drivers/fpga/xrt/include/xleaf/axigate.h > create mode 100644 drivers/fpga/xrt/lib/xleaf/axigate.c > > diff --git a/drivers/fpga/xrt/include/xleaf/axigate.h b/drivers/fpga/xrt/include/xleaf/axigate.h > new file mode 100644 > index 000000000000..2cef71e13b30 > --- /dev/null > +++ b/drivers/fpga/xrt/include/xleaf/axigate.h > @@ -0,0 +1,25 @@ > +/* SPDX-License-Identifier: GPL-2.0 */ > +/* > + * Header file for XRT Axigate Leaf Driver > + * > + * Copyright (C) 2020-2021 Xilinx, Inc. > + * > + * Authors: > + * Lizhi Hou <Lizhi.Hou@xilinx.com> > + */ > + > +#ifndef _XRT_AXIGATE_H_ > +#define _XRT_AXIGATE_H_ > + > +#include "xleaf.h" > +#include "metadata.h" > + > +/* > + * AXIGATE driver IOCTL calls. > + */ > +enum xrt_axigate_ioctl_cmd { > + XRT_AXIGATE_FREEZE = XRT_XLEAF_CUSTOM_BASE, /* See comments in xleaf.h */ > + XRT_AXIGATE_FREE, These are substrings, could change suffix to make it harder for developer to mix up. > +}; > + > +#endif /* _XRT_AXIGATE_H_ */ > diff --git a/drivers/fpga/xrt/lib/xleaf/axigate.c b/drivers/fpga/xrt/lib/xleaf/axigate.c > new file mode 100644 > index 000000000000..382969f9925f > --- /dev/null > +++ b/drivers/fpga/xrt/lib/xleaf/axigate.c > @@ -0,0 +1,298 @@ > +// SPDX-License-Identifier: GPL-2.0 > +/* > + * Xilinx Alveo FPGA AXI Gate Driver > + * > + * Copyright (C) 2020-2021 Xilinx, Inc. > + * > + * Authors: > + * Lizhi Hou<Lizhi.Hou@xilinx.com> > + */ > + > +#include <linux/mod_devicetable.h> > +#include <linux/platform_device.h> > +#include <linux/delay.h> > +#include <linux/device.h> > +#include <linux/io.h> > +#include "metadata.h" > +#include "xleaf.h" > +#include "xleaf/axigate.h" > + > +#define XRT_AXIGATE "xrt_axigate" > + > +struct axigate_regs { > + u32 iag_wr; > + u32 iag_rvsd; > + u32 iag_rd; > +} __packed; similar to other patches, prefix of element is not needed. > + > +struct xrt_axigate { > + struct platform_device *pdev; > + void *base; > + struct mutex gate_lock; /* gate dev lock */ > + > + void *evt_hdl; > + const char *ep_name; > + > + bool gate_freezed; > +}; > + > +/* the ep names are in the order of hardware layers */ > +static const char * const xrt_axigate_epnames[] = { > + XRT_MD_NODE_GATE_PLP, > + XRT_MD_NODE_GATE_ULP, what are plp, ulp ? it is helpful to comment or expand acronyms > + NULL > +}; > + > +#define reg_rd(g, r) \ > + ioread32((void *)(g)->base + offsetof(struct axigate_regs, r)) > +#define reg_wr(g, v, r) \ > + iowrite32(v, (void *)(g)->base + offsetof(struct axigate_regs, r)) > + > +static inline void freeze_gate(struct xrt_axigate *gate) > +{ > + reg_wr(gate, 0, iag_wr); The values written here and below are magic, the need to have #defines > + ndelay(500); > + reg_rd(gate, iag_rd); > +} > + > +static inline void free_gate(struct xrt_axigate *gate) > +{ > + reg_wr(gate, 0x2, iag_wr); > + ndelay(500); > + (void)reg_rd(gate, iag_rd); > + reg_wr(gate, 0x3, iag_wr); > + ndelay(500); > + reg_rd(gate, iag_rd); > +} > + > +static int xrt_axigate_epname_idx(struct platform_device *pdev) > +{ > + int i; > + int ret; int i, ret; > + struct resource *res; > + > + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); > + if (!res) { > + xrt_err(pdev, "Empty Resource!"); > + return -EINVAL; > + } > + > + for (i = 0; xrt_axigate_epnames[i]; i++) { null guarded array is useful with the size isn't know, in this case it is, so covert loop to using ARRAY_SIZE > + ret = strncmp(xrt_axigate_epnames[i], res->name, > + strlen(xrt_axigate_epnames[i]) + 1); needs a strlen check in case res->name is just a substring > + if (!ret) > + break; > + } > + > + ret = (xrt_axigate_epnames[i]) ? i : -EINVAL; > + return ret; > +} > + > +static void xrt_axigate_freeze(struct platform_device *pdev) > +{ > + struct xrt_axigate *gate; > + u32 freeze = 0; > + > + gate = platform_get_drvdata(pdev); > + > + mutex_lock(&gate->gate_lock); > + freeze = reg_rd(gate, iag_rd); > + if (freeze) { /* gate is opened */ > + xleaf_broadcast_event(pdev, XRT_EVENT_PRE_GATE_CLOSE, false); > + freeze_gate(gate); > + } > + > + gate->gate_freezed = true; Looks like freeze could be 0, so is setting gate_freeze = true correct all the time ? > + mutex_unlock(&gate->gate_lock); > + > + xrt_info(pdev, "freeze gate %s", gate->ep_name); > +} > + > +static void xrt_axigate_free(struct platform_device *pdev) > +{ > + struct xrt_axigate *gate; > + u32 freeze; > + > + gate = platform_get_drvdata(pdev); > + > + mutex_lock(&gate->gate_lock); > + freeze = reg_rd(gate, iag_rd); > + if (!freeze) { /* gate is closed */ > + free_gate(gate); > + xleaf_broadcast_event(pdev, XRT_EVENT_POST_GATE_OPEN, true); > + /* xrt_axigate_free() could be called in event cb, thus > + * we can not wait for the completes > + */ > + } > + > + gate->gate_freezed = false; freezed is not a word, the element name should be 'gate_frozen' > + mutex_unlock(&gate->gate_lock); > + > + xrt_info(pdev, "free gate %s", gate->ep_name); > +} > + > +static void xrt_axigate_event_cb(struct platform_device *pdev, void *arg) > +{ > + struct platform_device *leaf; > + struct xrt_event *evt = (struct xrt_event *)arg; > + enum xrt_events e = evt->xe_evt; > + enum xrt_subdev_id id = evt->xe_subdev.xevt_subdev_id; > + int instance = evt->xe_subdev.xevt_subdev_instance; > + struct xrt_axigate *gate = platform_get_drvdata(pdev); > + struct resource *res; > + > + switch (e) { > + case XRT_EVENT_POST_CREATION: > + break; > + default: > + return; > + } convert switch() to if () > + > + if (id != XRT_SUBDEV_AXIGATE) > + return; > + > + leaf = xleaf_get_leaf_by_id(pdev, id, instance); > + if (!leaf) > + return; > + > + res = platform_get_resource(leaf, IORESOURCE_MEM, 0); > + if (!res || !strncmp(res->name, gate->ep_name, strlen(res->name) + 1)) { > + (void)xleaf_put_leaf(pdev, leaf); > + return; > + } > + > + /* > + * higher level axigate instance created, > + * make sure the gate is openned. This covers 1RP flow which is openned -> is opened what is 1RP ? Tom > + * has plp gate as well. > + */ > + if (xrt_axigate_epname_idx(leaf) > xrt_axigate_epname_idx(pdev)) > + xrt_axigate_free(pdev); > + else > + xleaf_ioctl(leaf, XRT_AXIGATE_FREE, NULL); > + > + (void)xleaf_put_leaf(pdev, leaf); > +} > + > +static int > +xrt_axigate_leaf_ioctl(struct platform_device *pdev, u32 cmd, void *arg) > +{ > + switch (cmd) { > + case XRT_XLEAF_EVENT: > + xrt_axigate_event_cb(pdev, arg); > + break; > + case XRT_AXIGATE_FREEZE: > + xrt_axigate_freeze(pdev); > + break; > + case XRT_AXIGATE_FREE: > + xrt_axigate_free(pdev); > + break; > + default: > + xrt_err(pdev, "unsupported cmd %d", cmd); > + return -EINVAL; > + } > + > + return 0; > +} > + > +static int xrt_axigate_remove(struct platform_device *pdev) > +{ > + struct xrt_axigate *gate; > + > + gate = platform_get_drvdata(pdev); > + > + if (gate->base) > + iounmap(gate->base); > + > + platform_set_drvdata(pdev, NULL); > + devm_kfree(&pdev->dev, gate); > + > + return 0; > +} > + > +static int xrt_axigate_probe(struct platform_device *pdev) > +{ > + struct xrt_axigate *gate; > + struct resource *res; > + int ret; > + > + gate = devm_kzalloc(&pdev->dev, sizeof(*gate), GFP_KERNEL); > + if (!gate) > + return -ENOMEM; > + > + gate->pdev = pdev; > + platform_set_drvdata(pdev, gate); > + > + xrt_info(pdev, "probing..."); > + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); > + if (!res) { > + xrt_err(pdev, "Empty resource 0"); > + ret = -EINVAL; > + goto failed; > + } > + > + gate->base = ioremap(res->start, res->end - res->start + 1); > + if (!gate->base) { > + xrt_err(pdev, "map base iomem failed"); > + ret = -EFAULT; > + goto failed; > + } > + > + gate->ep_name = res->name; > + > + mutex_init(&gate->gate_lock); > + > + return 0; > + > +failed: > + xrt_axigate_remove(pdev); > + return ret; > +} > + > +static struct xrt_subdev_endpoints xrt_axigate_endpoints[] = { > + { > + .xse_names = (struct xrt_subdev_ep_names[]) { > + { .ep_name = "ep_pr_isolate_ulp_00" }, > + { NULL }, > + }, > + .xse_min_ep = 1, > + }, > + { > + .xse_names = (struct xrt_subdev_ep_names[]) { > + { .ep_name = "ep_pr_isolate_plp_00" }, > + { NULL }, > + }, > + .xse_min_ep = 1, > + }, > + { 0 }, > +}; > + > +static struct xrt_subdev_drvdata xrt_axigate_data = { > + .xsd_dev_ops = { > + .xsd_ioctl = xrt_axigate_leaf_ioctl, > + }, > +}; > + > +static const struct platform_device_id xrt_axigate_table[] = { > + { XRT_AXIGATE, (kernel_ulong_t)&xrt_axigate_data }, > + { }, > +}; > + > +static struct platform_driver xrt_axigate_driver = { > + .driver = { > + .name = XRT_AXIGATE, > + }, > + .probe = xrt_axigate_probe, > + .remove = xrt_axigate_remove, > + .id_table = xrt_axigate_table, > +}; > + > +void axigate_leaf_init_fini(bool init) > +{ > + if (init) { > + xleaf_register_driver(XRT_SUBDEV_AXIGATE, > + &xrt_axigate_driver, xrt_axigate_endpoints); > + } else { > + xleaf_unregister_driver(XRT_SUBDEV_AXIGATE); > + } > +}
On Mon, Mar 01, 2021 at 06:48:46AM +0000, Sonal Santan wrote: > Hello Tom, > > > -----Original Message----- > > From: Tom Rix <trix@redhat.com> > > Sent: Friday, February 19, 2021 2:26 PM > > To: Lizhi Hou <lizhih@xilinx.com>; linux-kernel@vger.kernel.org > > Cc: Lizhi Hou <lizhih@xilinx.com>; linux-fpga@vger.kernel.org; Max Zhen > > <maxz@xilinx.com>; Sonal Santan <sonals@xilinx.com>; Michal Simek > > <michals@xilinx.com>; Stefano Stabellini <stefanos@xilinx.com>; > > devicetree@vger.kernel.org; mdf@kernel.org; robh@kernel.org; Max Zhen > > <maxz@xilinx.com> > > Subject: Re: [PATCH V3 XRT Alveo 01/18] Documentation: fpga: Add a > > document describing XRT Alveo drivers > > > > From the documentation, there are a couple of big questions and a bunch of > > word smithing. > > > > pseudo-bus : do we need a bus ? > We are looking for guidance here. > > > > xrt-lib real platform devices that aren't fpga, do they need to move to another > > subsystem ? > > > > Drivers for the IPs that show up in the Alveo shell are not generic enough. They > fit into the framework that XRT uses. Is the idea that that they can be used in a > different context? > > > Overall looks good, love the ascii art! > > > > On 2/17/21 10:40 PM, Lizhi Hou wrote: > > > Describe XRT driver architecture and provide basic overview of Xilinx > > > Alveo platform. > > > > > > Signed-off-by: Sonal Santan <sonal.santan@xilinx.com> > > > Signed-off-by: Max Zhen <max.zhen@xilinx.com> > > > Signed-off-by: Lizhi Hou <lizhih@xilinx.com> > > > --- > > > Documentation/fpga/index.rst | 1 + > > > Documentation/fpga/xrt.rst | 842 > > +++++++++++++++++++++++++++++++++++ > > > 2 files changed, 843 insertions(+) > > > create mode 100644 Documentation/fpga/xrt.rst > > > > > > diff --git a/Documentation/fpga/index.rst > > > b/Documentation/fpga/index.rst index f80f95667ca2..30134357b70d 100644 > > > --- a/Documentation/fpga/index.rst > > > +++ b/Documentation/fpga/index.rst > > > @@ -8,6 +8,7 @@ fpga > > > :maxdepth: 1 > > > > > > dfl > > > + xrt > > > > > > .. only:: subproject and html > > > > > > diff --git a/Documentation/fpga/xrt.rst b/Documentation/fpga/xrt.rst > > > new file mode 100644 index 000000000000..9bc2d2785cb9 > > > --- /dev/null > > > +++ b/Documentation/fpga/xrt.rst > > > @@ -0,0 +1,842 @@ > > > +.. SPDX-License-Identifier: GPL-2.0 > > > + > > > +================================== > > > +XRTV2 Linux Kernel Driver Overview > > > +================================== > > > + > > > +Authors: > > > + > > > +* Sonal Santan <sonal.santan@xilinx.com> > > > +* Max Zhen <max.zhen@xilinx.com> > > > +* Lizhi Hou <lizhi.hou@xilinx.com> > > > + > > > +XRTV2 drivers are second generation `XRT > > > +<https://github.com/Xilinx/XRT>`_ drivers which support `Alveo > > > +<https://www.xilinx.com/products/boards-and-kits/alveo.html>`_ > > > +PCIe platforms from Xilinx. > > > + > > > +XRTV2 drivers support *subsystem* style data driven platforms where > > > +driver's > > where the driver's > > > +configuration and behavior is determined by meta data provided by the > > > +platform (in *device tree* format). Primary management physical > > > +function (MPF) driver is called **xmgmt**. Primary user physical > > > +function (UPF) driver is called > > > +**xuser** and is under development. xrt driver framework and HW > > > +subsystem drivers are packaged into a library module called > > > +**xrt-lib**, which is shared by **xmgmt** and **xuser** (under > > > +development). The xrt driver framework > > xuser still under development ? > > > +implements a pseudo-bus which is used to discover HW subsystems and > > > +facilitate > > > > A pseudo-bus. > > > > It would be good if this was close to what was done for dfl here > > > > https://lore.kernel.org/linux-fpga/1605159759-3439-1-git-send-email- > > yilun.xu@intel.com/ > > > > I am wondering if we can phase in the migration to formal bus architecture > based on struct bus_type as a follow on set of patches? I'd rather have it done early on. If we know there's a better way of doing something and we don't the code should go into staging. This gives us an out if it doesn't happen, otherwise the kernel community would depend on corporate goodwill to appropriately staff it. Note, I'm not trying to say there's any ill will anywhere, Xilinx has been traditionally good about this :) > > > > +inter HW subsystem interaction. > > > + > > > +Driver Modules > > > +============== > > > + > > > +xrt-lib.ko > > > +---------- > > > + > > > +Repository of all subsystem drivers and pure software modules that > > > +can potentially > > > > subsystem drivers > > > > drivers in fpga/ should be for managing just the fpganess of the fpga. > > > > soft devices ex/ a soft tty should go to their respective subsystem location > > > > Are there any in this patchset you think might move ? > > We have already shrunk the patch to only include FPGA centric pieces > necessary to get the bitstream download implemented. Should we explore > the question of subsystem drivers when we add support for more features of > the Alveo shell? > > > > > Maybe we can defer reviewing those now. > > > > > +be shared between xmgmt and xuser. All these drivers are structured > > > +as Linux *platform driver* and are instantiated by xmgmt (or xuser > > > +under development) based on meta data associated with hardware. The > > > +metadata is in the form of device tree > > > > with the hardware > > > > form of a device tree > > > > Will change > > > > +as mentioned before. Each platform driver statically defines a > > > +subsystem node array by using node name or a string in its > > > +``compatible`` property. And this array is eventually translated to IOMEM > > resources of the platform device. > > > + > > > +The xrt-lib core infrastructure provides hooks to platform drivers > > > +for device node management, user file operations and ioctl callbacks. > > > +The core also provides pseudo-bus functionality for platform driver > > > +registration, discovery and inter platform driver ioctl calls. > > > > core infrastructure. > > > > Will update. > > > The interfaces to the infrastructure are not in include/linux/fpga/ > > > > Maybe this needs to change. > > > > Were you thinking of moving XRT infrastructure header files from > drivers/fpga/xrt/include to include/linux/fpga? > > > > + > > > +.. note:: > > > + See code in ``include/xleaf.h`` > > > + > > > + > > > +xmgmt.ko > > > +-------- > > > + > > > +The xmgmt driver is a PCIe device driver driving MPF found on > > > +Xilinx's Alveo PCIE device. It consists of one *root* driver, one or > > > +more *group* drivers and one or more *xleaf* drivers. The root and > > > +MPF specific xleaf drivers are in xmgmt.ko. The group driver and other xleaf > > drivers are in xrt-lib.ko. > > I am not sure if *.ko is correct, these will also be intree. > > > + > > > +The instantiation of specific group driver or xleaf driver is > > > +completely data > > of a specific > > > +driven based on meta data (mostly in device tree format) found > > > +through VSEC > > mostly ? what is the deviation from device tree ? > > > +capability and inside firmware files, such as platform xsabin or user xclbin > > file. > > > +The root driver manages life cycle of multiple group drivers, which, > > > +in turn, > > the life cycle > > > +manages multiple xleaf drivers. This allows a single set of driver > > > +code to support > > > > set of drivers > > > > drop 'code' > > > > Will update > > > > +all kinds of subsystems exposed by different shells. The difference > > > +among all these subsystems will be handled in xleaf drivers with root > > > +and group drivers being part of the infrastructure and provide common > > > +services for all leaves found on all platforms. > > > + > > > +The driver object model looks like the following:: > > > + > > > + +-----------+ > > > + | xroot | > > > + +-----+-----+ > > > + | > > > + +-----------+-----------+ > > > + | | > > > + v v > > > + +-----------+ +-----------+ > > > + | group | ... | group | > > > + +-----+-----+ +------+----+ > > > + | | > > > + | | > > > + +-----+----+ +-----+----+ > > > + | | | | > > > + v v v v > > > + +-------+ +-------+ +-------+ +-------+ > > > + | xleaf |..| xleaf | | xleaf |..| xleaf | > > > + +-------+ +-------+ +-------+ +-------+ > > > + > > > +As an example for Xilinx Alveo U50 before user xclbin download, the > > > +tree looks like the following:: > > > + > > > + +-----------+ > > > + | xmgmt | > > > + +-----+-----+ > > > + | > > > + +-------------------------+--------------------+ > > > + | | | > > > + v v v > > > + +--------+ +--------+ +--------+ > > > + | group0 | | group1 | | group2 | > > > + +----+---+ +----+---+ +---+----+ > > > + | | | > > > + | | | > > > + +-----+-----+ +----+-----+---+ +-----+-----+----+--------+ > > > + | | | | | | | | | > > > + v v | v v | v v | > > > + +------------+ +------+ | +------+ +------+ | +------+ > > > + +------------+ +-----------+ | > > > + | xmgmt_main | | VSEC | | | GPIO | | QSPI | | | CMC | | > > > + | AXI-GATE0 | | > > > + +------------+ +------+ | +------+ +------+ | +------+ > > > + +------------+ +-----------+ | > > > + | +---------+ | +------+ +-----------+ | > > > + +>| MAILBOX | +->| ICAP | | AXI-GATE1 |<+ > > > + +---------+ | +------+ +-----------+ > > > + | +-------+ > > > + +->| CALIB | > > > + +-------+ > > > + > > Nice ascii art! > > > +After an xclbin is download, group3 will be added and the tree looks > > > +like the > > > +following:: > > > + > > > + +-----------+ > > > + | xmgmt | > > > + +-----+-----+ > > > + | > > > + +-------------------------+--------------------+-----------------+ > > > + | | | | > > > + v v v | > > > + +--------+ +--------+ +--------+ | > > > + | group0 | | group1 | | group2 | | > > > + +----+---+ +----+---+ +---+----+ | > > > + | | | | > > > + | | | | > > > + +-----+-----+ +-----+-----+---+ +-----+-----+----+--------+ | > > > + | | | | | | | | | | > > > + v v | v v | v v | | > > > + +------------+ +------+ | +------+ +------+ | +------+ +-----------+ | | > > > + | xmgmt_main | | VSEC | | | GPIO | | QSPI | | | CMC | | AXI-GATE0 | | > > | > > > + +------------+ +------+ | +------+ +------+ | +------+ +-----------+ | | > > > + | +---------+ | +------+ +-----------+ | | > > > + +>| MAILBOX | +->| ICAP | | AXI-GATE1 |<+ | > > > + +---------+ | +------+ +-----------+ | > > > + | +-------+ | > > > + +->| CALIB | | > > > + +-------+ | > > > + +---+----+ | > > > + | group3 |<--------------------------------------------+ > > > + +--------+ > > > + | > > > + | > > > + +-------+--------+---+--+--------+------+-------+ > > > + | | | | | | | > > > + v | v | v | v > > > + +--------+ | +--------+ | +--------+ | +-----+ > > > + | CLOCK0 | | | CLOCK1 | | | CLOCK2 | | | UCS | > > > + +--------+ v +--------+ v +--------+ v +-----+ > > > + +-------------+ +-------------+ +-------------+ > > > + | CLOCK-FREQ0 | | CLOCK-FREQ1 | | CLOCK-FREQ2 | > > > + +-------------+ +-------------+ +-------------+ > > > + > > > + > > > +xmgmt-root > > > +^^^^^^^^^^ > > > + > > > +The xmgmt-root driver is a PCIe device driver attached to MPF. It's > > > +part of the infrastructure of the MPF driver and resides in xmgmt.ko. > > > +This driver > > > + > > > +* manages one or more group drivers > > > +* provides access to functionalities that requires pci_dev, such as > > > +PCIE config > > > + space access, to other xleaf drivers through root calls > > > +* together with group driver, facilities event callbacks for other > > > +xleaf drivers > > > +* together with group driver, facilities inter-leaf driver calls for > > > +other xleaf > > Maybe drop 'together with group driver' > > Will update > > > > + drivers > > > + > > > +When root driver starts, it will explicitly create an initial group > > > +instance, which contains xleaf drivers that will trigger the creation > > > +of other group instances. The root driver will wait for all group and > > > +leaves to be created before it returns from it's probe routine and > > > +claim success of the initialization of the entire xmgmt driver. > > What happens if there a failure in one leaf ? Does the whole board go down ? > > > + > > > +.. note:: > > > + See code in ``lib/xroot.c`` and ``mgmt/root.c`` > > > + > > > + > > > +group > > > +^^^^^ > > > + > > > +The group driver is a platform device driver whose life cycle is > > > +managed by > > Maybe call this a 'pseudo device' > > Will update > > > > +root and does not have real IO mem or IRQ resources. It's part of the > > > +infrastructure of the MPF driver and resides in xrt-lib.ko. This > > > +driver > > > + > > > +* manages one or more xleaf drivers so that multiple leaves can be > > > +managed as a > > > + group > > can drop 'so that multiple leaves can be managed as a group' to me, this is the > > same as 'one or more' > > Will do > > > > +* provides access to root from leaves, so that root calls, event > > > +notifications > > > + and inter-leaf calls can happen > > > + > > > +In xmgmt, an initial group driver instance will be created by root, > > > +which > > by the root > > > +contains leaves that will trigger group instances to be created to > > > +manage groups of leaves found on different partitions on hardware, > > > +such as VSEC, Shell, and User. > > > + > > > +Every *fpga_region* has a group object associated with it. The group > > > +is created when xclbin image is loaded on the fpga_region. The > > > +existing group is destroyed when a new xclbin image is loaded. The > > > +fpga_region persists across xclbin downloads. > > The connection of a 'group' node to a fpga region region is fairly important, > > maybe move this section earlier. 'group' as an fpganess thing would be kept in > > fpga/ subsystem. > > Will update > > > > + > > > +.. note:: > > > + See code in ``lib/group.c`` > > > + > > > + > > > +xleaf > > > +^^^^^ > > > + > > > +The xleaf driver is a platform device driver whose life cycle is > > > +managed by a group driver and may or may not have real IO mem or IRQ > > > +resources. They are the real meat of xmgmt and contains platform > > > +specific code to Shell and User found on a MPF. > > > + > > > > Maybe a split is pseudo device leaves, those without real IO mem, stay in > > fpga/ others go ? > > > > This goes back to the earlier question of what minimal set of platform drivers > should stay in fpga subsystem. There are some like bridge or configuration > engine (also called icap) which have their own IO mem but do not have a life > outside of fpga subsystem. > > > > +A xleaf driver may not have real hardware resources when it merely > > > +acts as a driver that manages certain in-memory states for xmgmt. > > > +These in-memory states could be shared by multiple other leaves. > > > + > > This implies locking and some message passing. > > > +Leaf drivers assigned to specific hardware resources drive specific > > > +subsystem in > > drive a specific > > > +the device. To manipulate the subsystem or carry out a task, a xleaf > > > +driver may ask help from root via root calls and/or from other leaves via > > inter-leaf calls. > > > + > > > +A xleaf can also broadcast events through infrastructure code for > > > +other leaves to process. It can also receive event notification from > > > +infrastructure about certain events, such as post-creation or pre-exit of a > > particular xleaf. > > I would like to see some examples of how the inter node communications work. > > Would update to show an example. > > > > + > > > +.. note:: > > > + See code in ``lib/xleaf/*.c`` > > > + > > > + > > > +FPGA Manager Interaction > > > +======================== > > > + > > > +fpga_manager > > > +------------ > > > + > > > +An instance of fpga_manager is created by xmgmt_main and is used for > > > +xclbin > > for the xclbin > > > +image download. fpga_manager requires the full xclbin image before it > > > +can start programming the FPGA configuration engine via ICAP platform > > driver. > > > > via the ICAP > > > > what is ICAP ? > > Will update. ICAP stands for Internal Configuration Access Port used for configuring > the fpga. > > > > > > + > > > +fpga_region > > > +----------- > > > + > > > +For every interface exposed by currently loaded xclbin/xsabin in the > > > +*parent* > > by the currently > > > +fpga_region a new instance of fpga_region is created like a *child* region. > > fpga_region, > > > +The device tree of the *parent* fpga_region defines the resources for > > > +a new instance of fpga_bridge which isolates the parent from > > and isolates > > > +child fpga_region. This new instance of fpga_bridge will be used when > > > +a xclbin image is loaded on the child fpga_region. After the xclbin > > > +image is downloaded to the fpga_region, an instance of group is > > > +created for the fpga_region using the device tree obtained as part of > > > +xclbin. If this device > > of the xclbin > > > +tree defines any child interfaces then it can trigger the creation of > > interfaces, then > > > +fpga_bridge and fpga_region for the next region in the chain. > > a fpga_bridge and a fpga_region > > > + > > > +fpga_bridge > > > +----------- > > > + > > > +Like fpga_region, matching fpga_bridge is also created by walking the > > > +device > > Like the fpga_region, a matchin > > > +tree of the parent group. > > > + > > > +Driver Interfaces > > > +================= > > > + > > > +xmgmt Driver Ioctls > > > +------------------- > > > + > > > +Ioctls exposed by xmgmt driver to user space are enumerated in the > > > +following > > > +table: > > > + > > > +== ===================== ============================ > > ========================== > > > +# Functionality ioctl request code data format > > > +== ===================== ============================ > > ========================== > > > +1 FPGA image download XMGMT_IOCICAPDOWNLOAD_AXLF > > xmgmt_ioc_bitstream_axlf > > > +== ===================== ============================ > > > +========================== > > > > This data format is described below, maybe swap this section with that so > > > > folks will know what xmgmnt_ioc_bitstream_axlf is before this section. > > > > Will update. > > > > + > > > +User xclbin can be downloaded by using xbmgmt tool from XRT open > > > +source suite. See > > > > A user xclbin > > > > using the xbmgmt > > > > from the XRT > > > > Will update > > > > +example usage below:: > > > + > > > + xbmgmt partition --program --path > > > + /lib/firmware/xilinx/862c7020a250293e32036f19956669e5/test/verify.xc > > > + lbin --force > > > + > > > +xmgmt Driver Sysfs > > > +------------------ > > > + > > > +xmgmt driver exposes a rich set of sysfs interfaces. Subsystem > > > +platform drivers export sysfs node for every platform instance. > > > + > > > +Every partition also exports its UUIDs. See below for examples:: > > > + > > > + /sys/bus/pci/devices/0000:06:00.0/xmgmt_main.0/interface_uuids > > > + /sys/bus/pci/devices/0000:06:00.0/xmgmt_main.0/logic_uuids > > > + > > > + > > > +hwmon > > > +----- > > > + > > > +xmgmt driver exposes standard hwmon interface to report voltage, > > > +current, temperature, power, etc. These can easily be viewed using > > > +*sensors* command line utility. > > > + > > > +Alveo Platform Overview > > > +======================= > > > + > > > +Alveo platforms are architected as two physical FPGA partitions: > > > +*Shell* and *User*. The Shell provides basic infrastructure for the > > > +Alveo platform like PCIe connectivity, board management, Dynamic > > > +Function Exchange (DFX), sensors, clocking, reset, and security. User > > > +partition contains user compiled FPGA > > the user compiled > > > +binary which is loaded by a process called DFX also known as partial > > > +reconfiguration. > > > + > > > +Physical partitions require strict HW compatibility with each other > > > +for DFX to work properly. > > > > swap order > > > > For DFX to work properly physical partitions .. > > > > > > Will update > > > > Every physical partition has two interface UUIDs: *parent* UUID > > > +and *child* UUID. For simple single stage platforms, Shell → User > > > +forms parent child relationship. For complex two stage platforms, > > > +Base → Shell → User forms the parent child relationship chain. > > this bit is confusing. is this related to uuid? > > > + > > > +.. note:: > > > + Partition compatibility matching is key design component of Alveo > > platforms > > > + and XRT. Partitions have child and parent relationship. A loaded > > > +partition > > have a child > > > + exposes child partition UUID to advertise its compatibility > > > + requirement for > > > > the child's > > > > can drop 'for child partition' > > Will update > > > > > > + child partition. When loading a child partition the xmgmt > > > + management driver > > When loading a child partition, > > > + matches parent UUID of the child partition against child UUID exported by > > > + the parent. Parent and child partition UUIDs are stored in the *xclbin* > > > + (for user) or *xsabin* (for base and shell). > > > > this is confusing, is this part of the file image format ? > > > > Maybe save/move till the image layout. > > Yes these IDs are stored in xclbin image format. Will move the sections around > as suggested. > > > > > > Except for root UUID, VSEC, > > > + hardware itself does not know about UUIDs. UUIDs are stored in xsabin > > and > > > + xclbin. > > This is confusing too, not sure how to untangle. > > Will reword. > > > > + > > > + > > > +The physical partitions and their loading is illustrated below:: > > > + > > > + SHELL USER > > > + +-----------+ +-------------------+ > > > + | | | | > > > + | VSEC UUID | CHILD PARENT | LOGIC UUID | > > > + | o------->|<--------o | > > > + | | UUID UUID | | > > > + +-----+-----+ +--------+----------+ > > > + | | > > > + . . > > > + | | > > > + +---+---+ +------+--------+ > > > + | POR | | USER COMPILED | > > > + | FLASH | | XCLBIN | > > > + +-------+ +---------------+ > > > + > > > + > > > +Loading Sequence > > > +---------------- > > > + > > > +The Shell partition is loaded from flash at system boot time. It > > > +establishes the PCIe link and exposes two physical functions to the > > > +BIOS. After OS boot, xmgmt > > the OS boots, the xmgmt > > > +driver attaches to PCIe physical function 0 exposed by the Shell and > > > +then looks for VSEC in PCIe extended configuration space. Using VSEC > > > +it determines the logic > > > > the PCIe > > > > The driver uses VSEC to determine the UUID of Shell. The UUID is also used to > > load a matching ... > > > > Will update > > > > +UUID of Shell and uses the UUID to load matching *xsabin* file from > > > +Linux firmware directory. The xsabin file contains metadata to > > > +discover peripherals that are part of Shell and firmware(s) for any > > embedded soft processors in Shell. > > the firmware needed for any ... > > Will update > > > > + > > > +The Shell exports child interface UUID which is used for > > > +compatibility check when > > > > export a child > > > > for a compatibility check > > > > Will update > > > > +loading user compiled xclbin over the User partition as part of DFX. > > > +When a user requests loading of a specific xclbin the xmgmt > > > +management driver reads the parent > > xclbin, the > > > +interface UUID specified in the xclbin and matches it with child > > > +interface UUID exported by Shell to determine if xclbin is compatible > > > +with the Shell. If match fails loading of xclbin is denied. > > > + > > > +xclbin loading is requested using ICAP_DOWNLOAD_AXLF ioctl command. > > > +When loading xclbin, xmgmt driver performs the following *logical* > > operations: > > > + > > > +1. Copy xclbin from user to kernel memory 2. Sanity check the xclbin > > > +contents 3. Isolate the User partition 4. Download the bitstream > > > +using the FPGA config engine (ICAP) 5. De-isolate the User partition > > > +6. Program the clocks (ClockWiz) driving the User partition > > maybe drop '(ClockWiz)' > > > +7. Wait for memory controller (MIG) calibration > > for the > > > +8. Return the loading status back to the caller > > > + > > > +`Platform Loading Overview > > > +<https://xilinx.github.io/XRT/master/html/platforms_partitions.html>` > > > +_ provides more detailed information on platform loading. > > > + > > the link works. > > > + > > > +xsabin > > > +------ > > > + > > > +Each Alveo platform comes packaged with its own xsabin. The xsabin is > > > +trusted > > is a trusted > > > +component of the platform. For format details refer to > > > +:ref:`xsabin_xclbin_container_format` > > > +below. xsabin contains basic information like UUIDs, platform name > > > +and metadata in the form of device tree. See :ref:`device_tree_usage` > > below for details and example. > > of a device > > > + > > > +xclbin > > > +------ > > > + > > > +xclbin is compiled by end user using > > > +`Vitis > > > +<https://www.xilinx.com/products/design-tools/vitis/vitis-platform.ht > > > +ml>`_ > > this link works, seems reasonable landing > > > +tool set from Xilinx. The xclbin contains sections describing user > > > +compiled acceleration engines/kernels, memory subsystems, clocking > > > +information etc. It also contains bitstream for the user partition, > > > +UUIDs, platform name, etc. xclbin uses > > bitstreams > > > +the same container format as xsabin which is described below. > > > + > > > + > > > +.. _xsabin_xclbin_container_format: > > > + > > > +xsabin/xclbin Container Format > > > +------------------------------ > > > + > > > +xclbin/xsabin is ELF-like binary container format. It is structured > > > +as series of sections. There is a file header followed by several > > > +section headers which is followed by sections. A section header > > > +points to an actual section. There is an optional signature at the end. The > > format is defined by header file ``xclbin.h``. > > > +The following figure illustrates a typical xclbin:: > > > + > > > + > > > + +---------------------+ > > > + | | > > > + | HEADER | > > > + +---------------------+ > > > + | SECTION HEADER | > > > + | | > > > + +---------------------+ > > > + | ... | > > > + | | > > > + +---------------------+ > > > + | SECTION HEADER | > > > + | | > > > + +---------------------+ > > > + | SECTION | > > > + | | > > > + +---------------------+ > > > + | ... | > > > + | | > > > + +---------------------+ > > > + | SECTION | > > > + | | > > > + +---------------------+ > > > + | SIGNATURE | > > > + | (OPTIONAL) | > > > + +---------------------+ > > > + > > > + > > > +xclbin/xsabin files can be packaged, un-packaged and inspected using > > > +XRT utility called **xclbinutil**. xclbinutil is part of XRT open > > > +source software stack. The source code for xclbinutil can be found at > > > +https://github.com/Xilinx/XRT/tree/master/src/runtime_src/tools/xclbi > > > +nutil > > > + > > Works, but maybe the location of a manpage or doc would be better. > > > +For example to enumerate the contents of a xclbin/xsabin use the > > > +*--info* switch as shown below:: > > > + > > > + > > > + xclbinutil --info --input > > > + /opt/xilinx/firmware/u50/gen3x16-xdma/blp/test/bandwidth.xclbin > > > + xclbinutil --info --input > > > + /lib/firmware/xilinx/862c7020a250293e32036f19956669e5/partition.xsab > > > + in > > > + > > > + > > > +.. _device_tree_usage: > > > + > > > +Device Tree Usage > > > +----------------- > > > + > > > +As mentioned previously xsabin stores metadata which advertise HW > > > +subsystems present in a partition. The metadata is stored in device tree > > format with well defined schema. > > > +XRT management driver uses this information to bind *platform > > > +drivers* to the subsystem instantiations. The platform drivers are > > > +found in **xrt-lib.ko** kernel module defined later. > > > + > > > +Logic UUID > > > +^^^^^^^^^^ > > > +A partition is identified uniquely through ``logic_uuid`` property:: > > > + > > > + /dts-v1/; > > > + / { > > > + logic_uuid = "0123456789abcdef0123456789abcdef"; > > > + ... > > > + } > > > + > > > +Schema Version > > > +^^^^^^^^^^^^^^ > > > +Schema version is defined through ``schema_version`` node. And it > > > +contains ``major`` and ``minor`` properties as below:: > > > + > > > + /dts-v1/; > > > + / { > > > + schema_version { > > > + major = <0x01>; > > > + minor = <0x00>; > > > + }; > > > + ... > > > + } > > > + > > > +Partition UUIDs > > > +^^^^^^^^^^^^^^^ > > > +As said earlier, each partition may have parent and child UUIDs. > > > +These UUIDs are defined by ``interfaces`` node and ``interface_uuid`` > > property:: > > > + > > > + /dts-v1/; > > > + / { > > > + interfaces { > > > + @0 { > > > + interface_uuid = "0123456789abcdef0123456789abcdef"; > > > + }; > > > + @1 { > > > + interface_uuid = "fedcba9876543210fedcba9876543210"; > > > + }; > > > + ... > > > + }; > > > + ... > > > + } > > > + > > > + > > > +Subsystem Instantiations > > > +^^^^^^^^^^^^^^^^^^^^^^^^ > > > +Subsystem instantiations are captured as children of > > > +``addressable_endpoints`` > > > +node:: > > > + > > > + /dts-v1/; > > > + / { > > > + addressable_endpoints { > > > + abc { > > > + ... > > > + }; > > > + def { > > > + ... > > > + }; > > > + ... > > > + } > > > + } > > > + > > > +Subnode 'abc' and 'def' are the name of subsystem nodes > > > + > > > +Subsystem Node > > > +^^^^^^^^^^^^^^ > > > +Each subsystem node and its properties define a hardware instance:: > > > + > > > + > > > + addressable_endpoints { > > > + abc { > > > + reg = <0xa 0xb> > > > + pcie_physical_function = <0x0>; > > > + pcie_bar_mapping = <0x2>; > > > + compatible = "abc def"; > > > + firmware { > > > + firmware_product_name = "abc" > > > + firmware_branch_name = "def" > > > + firmware_version_major = <1> > > > + firmware_version_minor = <2> > > > + }; > > > + } > > > + ... > > > + } > > > + > > > +:reg: > > > + Property defines address range. '<0xa 0xb>' is BAR offset and length > > > +pair, both are 64-bit integer. > > > +:pcie_physical_function: > > > + Property specifies which PCIe physical function the subsystem node resides. > > > +:pcie_bar_mapping: > > > + Property specifies which PCIe BAR the subsystem node resides. > > > +'<0x2>' is BAR index and it is 0 if this property is not defined. > > > +:compatible: > > > + Property is a list of strings. The first string in the list > > > +specifies the exact subsystem node. The following strings represent > > > +other devices that the device is compatible with. > > > +:firmware: > > > + Subnode defines the firmware required by this subsystem node. > > > + > > > +Alveo U50 Platform Example > > > +^^^^^^^^^^^^^^^^^^^^^^^^^^ > > > +:: > > > + > > > + /dts-v1/; > > > + > > > + /{ > > > + logic_uuid = "f465b0a3ae8c64f619bc150384ace69b"; > > > + > > > + schema_version { > > > + major = <0x01>; > > > + minor = <0x00>; > > > + }; > > > + > > > + interfaces { > > > + > > > + @0 { > > > + interface_uuid = "862c7020a250293e32036f19956669e5"; > > > + }; > > > + }; > > > + > > > + addressable_endpoints { > > > + > > > + ep_blp_rom_00 { > > > + reg = <0x00 0x1f04000 0x00 0x1000>; > > > + pcie_physical_function = <0x00>; > > > + compatible = "xilinx.com,reg_abs-axi_bram_ctrl- > > 1.0\0axi_bram_ctrl"; > > > + }; > > > + > > > + ep_card_flash_program_00 { > > > + reg = <0x00 0x1f06000 0x00 0x1000>; > > > + pcie_physical_function = <0x00>; > > > + compatible = "xilinx.com,reg_abs-axi_quad_spi- > > 1.0\0axi_quad_spi"; > > > + interrupts = <0x03 0x03>; > > > + }; > > > + > > > + ep_cmc_firmware_mem_00 { > > > + reg = <0x00 0x1e20000 0x00 0x20000>; > > > + pcie_physical_function = <0x00>; > > > + compatible = > > > + "xilinx.com,reg_abs-axi_bram_ctrl-1.0\0axi_bram_ctrl"; > > > + > > > + firmware { > > > + firmware_product_name = "cmc"; > > > + firmware_branch_name = "u50"; > > > + firmware_version_major = <0x01>; > > > + firmware_version_minor = <0x00>; > > > + }; > > > + }; > > > + > > > + ep_cmc_intc_00 { > > > + reg = <0x00 0x1e03000 0x00 0x1000>; > > > + pcie_physical_function = <0x00>; > > > + compatible = "xilinx.com,reg_abs-axi_intc-1.0\0axi_intc"; > > > + interrupts = <0x04 0x04>; > > > + }; > > > + > > > + ep_cmc_mutex_00 { > > > + reg = <0x00 0x1e02000 0x00 0x1000>; > > > + pcie_physical_function = <0x00>; > > > + compatible = "xilinx.com,reg_abs-axi_gpio-1.0\0axi_gpio"; > > > + }; > > > + > > > + ep_cmc_regmap_00 { > > > + reg = <0x00 0x1e08000 0x00 0x2000>; > > > + pcie_physical_function = <0x00>; > > > + compatible = > > > + "xilinx.com,reg_abs-axi_bram_ctrl-1.0\0axi_bram_ctrl"; > > > + > > > + firmware { > > > + firmware_product_name = "sc-fw"; > > > + firmware_branch_name = "u50"; > > > + firmware_version_major = <0x05>; > > > + }; > > > + }; > > > + > > > + ep_cmc_reset_00 { > > > + reg = <0x00 0x1e01000 0x00 0x1000>; > > > + pcie_physical_function = <0x00>; > > > + compatible = "xilinx.com,reg_abs-axi_gpio-1.0\0axi_gpio"; > > > + }; > > > + > > > + ep_ddr_mem_calib_00 { > > > + reg = <0x00 0x63000 0x00 0x1000>; > > > + pcie_physical_function = <0x00>; > > > + compatible = "xilinx.com,reg_abs-axi_gpio-1.0\0axi_gpio"; > > > + }; > > > + > > > + ep_debug_bscan_mgmt_00 { > > > + reg = <0x00 0x1e90000 0x00 0x10000>; > > > + pcie_physical_function = <0x00>; > > > + compatible = "xilinx.com,reg_abs-debug_bridge- > > 1.0\0debug_bridge"; > > > + }; > > > + > > > + ep_ert_base_address_00 { > > > + reg = <0x00 0x21000 0x00 0x1000>; > > > + pcie_physical_function = <0x00>; > > > + compatible = "xilinx.com,reg_abs-axi_gpio-1.0\0axi_gpio"; > > > + }; > > > + > > > + ep_ert_command_queue_mgmt_00 { > > > + reg = <0x00 0x40000 0x00 0x10000>; > > > + pcie_physical_function = <0x00>; > > > + compatible = "xilinx.com,reg_abs-ert_command_queue- > > 1.0\0ert_command_queue"; > > > + }; > > > + > > > + ep_ert_command_queue_user_00 { > > > + reg = <0x00 0x40000 0x00 0x10000>; > > > + pcie_physical_function = <0x01>; > > > + compatible = "xilinx.com,reg_abs-ert_command_queue- > > 1.0\0ert_command_queue"; > > > + }; > > > + > > > + ep_ert_firmware_mem_00 { > > > + reg = <0x00 0x30000 0x00 0x8000>; > > > + pcie_physical_function = <0x00>; > > > + compatible = > > > + "xilinx.com,reg_abs-axi_bram_ctrl-1.0\0axi_bram_ctrl"; > > > + > > > + firmware { > > > + firmware_product_name = "ert"; > > > + firmware_branch_name = "v20"; > > > + firmware_version_major = <0x01>; > > > + }; > > > + }; > > > + > > > + ep_ert_intc_00 { > > > + reg = <0x00 0x23000 0x00 0x1000>; > > > + pcie_physical_function = <0x00>; > > > + compatible = "xilinx.com,reg_abs-axi_intc-1.0\0axi_intc"; > > > + interrupts = <0x05 0x05>; > > > + }; > > > + > > > + ep_ert_reset_00 { > > > + reg = <0x00 0x22000 0x00 0x1000>; > > > + pcie_physical_function = <0x00>; > > > + compatible = "xilinx.com,reg_abs-axi_gpio-1.0\0axi_gpio"; > > > + }; > > > + > > > + ep_ert_sched_00 { > > > + reg = <0x00 0x50000 0x00 0x1000>; > > > + pcie_physical_function = <0x01>; > > > + compatible = "xilinx.com,reg_abs-ert_sched-1.0\0ert_sched"; > > > + interrupts = <0x09 0x0c>; > > > + }; > > > + > > > + ep_fpga_configuration_00 { > > > + reg = <0x00 0x1e88000 0x00 0x8000>; > > > + pcie_physical_function = <0x00>; > > > + compatible = "xilinx.com,reg_abs-axi_hwicap- > > 1.0\0axi_hwicap"; > > > + interrupts = <0x02 0x02>; > > > + }; > > > + > > > + ep_icap_reset_00 { > > > + reg = <0x00 0x1f07000 0x00 0x1000>; > > > + pcie_physical_function = <0x00>; > > > + compatible = "xilinx.com,reg_abs-axi_gpio-1.0\0axi_gpio"; > > > + }; > > > + > > > + ep_msix_00 { > > > + reg = <0x00 0x00 0x00 0x20000>; > > > + pcie_physical_function = <0x00>; > > > + compatible = "xilinx.com,reg_abs-msix-1.0\0msix"; > > > + pcie_bar_mapping = <0x02>; > > > + }; > > > + > > > + ep_pcie_link_mon_00 { > > > + reg = <0x00 0x1f05000 0x00 0x1000>; > > > + pcie_physical_function = <0x00>; > > > + compatible = "xilinx.com,reg_abs-axi_gpio-1.0\0axi_gpio"; > > > + }; > > > + > > > + ep_pr_isolate_plp_00 { > > > + reg = <0x00 0x1f01000 0x00 0x1000>; > > > + pcie_physical_function = <0x00>; > > > + compatible = "xilinx.com,reg_abs-axi_gpio-1.0\0axi_gpio"; > > > + }; > > > + > > > + ep_pr_isolate_ulp_00 { > > > + reg = <0x00 0x1000 0x00 0x1000>; > > > + pcie_physical_function = <0x00>; > > > + compatible = "xilinx.com,reg_abs-axi_gpio-1.0\0axi_gpio"; > > > + }; > > > + > > > + ep_uuid_rom_00 { > > > + reg = <0x00 0x64000 0x00 0x1000>; > > > + pcie_physical_function = <0x00>; > > > + compatible = "xilinx.com,reg_abs-axi_bram_ctrl- > > 1.0\0axi_bram_ctrl"; > > > + }; > > > + > > > + ep_xdma_00 { > > > + reg = <0x00 0x00 0x00 0x10000>; > > > + pcie_physical_function = <0x01>; > > > + compatible = "xilinx.com,reg_abs-xdma-1.0\0xdma"; > > > + pcie_bar_mapping = <0x02>; > > > + }; > > > + }; > > > + > > > + } > > > + > > > + > > > + > > > +Deployment Models > > > +================= > > > + > > > +Baremetal > > > +--------- > > > + > > > +In bare-metal deployments both MPF and UPF are visible and > > > +accessible. xmgmt > > In bare-meta deployments, > > > +driver binds to MPF. xmgmt driver operations are privileged and > > > +available to system administrator. The full stack is illustrated below:: > > > + > > > + HOST > > > + > > > + [XMGMT] [XUSER] > > > + | | > > > + | | > > > + +-----+ +-----+ > > > + | MPF | | UPF | > > > + | | | | > > > + | PF0 | | PF1 | > > > + +--+--+ +--+--+ > > > + ......... ^................. ^.......... > > > + | | > > > + | PCIe DEVICE | > > > + | | > > > + +--+------------------+--+ > > > + | SHELL | > > > + | | > > > + +------------------------+ > > > + | USER | > > > + | | > > > + | | > > > + | | > > > + | | > > > + +------------------------+ > > > + > > > + > > > + > > > +Virtualized > > > +----------- > > > + > > > +In virtualized deployments privileged MPF is assigned to host but > > > +unprivileged > > In virtualized deployments, the > > > +UPF is assigned to guest VM via PCIe pass-through. xmgmt driver in > > > +host binds > > in the host > > > +to MPF. xmgmt driver operations are privileged and only accessible by > > > +hosting > > to the MPF > > > +service provider. The full stack is illustrated below:: > > > + > > > + > > > + ............. > > > + HOST . VM . > > > + . . > > > + [XMGMT] . [XUSER] . > > > + | . | . > > > + | . | . > > > + +-----+ . +-----+ . > > > + | MPF | . | UPF | . > > > + | | . | | . > > > + | PF0 | . | PF1 | . > > > + +--+--+ . +--+--+ . > > > + ......... ^................. ^.......... > > > + | | > > > + | PCIe DEVICE | > > > + | | > > > + +--+------------------+--+ > > > + | SHELL | > > > + | | > > > + +------------------------+ > > > + | USER | > > > + | | > > > + | | > > > + | | > > > + | | > > > + +------------------------+ > > > + > > > + > > > + > > > + > > > + > > > +Platform Security Considerations > > > +================================ > > > + > > > +`Security of Alveo Platform > > > +<https://xilinx.github.io/XRT/master/html/security.html>`_ > > > +discusses the deployment options and security implications in great detail. > > > > This link works and looks great. > > > > Tom > > Thanks for the detailed review of the document. I am working on incorporating the > feedback. One outstanding question is about usage of formal bus in XRT and if we > should phase that in as a follow-on. It would also determine if IP drivers should > move to other subsystems. > > -Sonal - Moritz
Hello Moritz, > -----Original Message----- > From: Moritz Fischer <mdf@kernel.org> > Sent: Saturday, March 6, 2021 9:19 AM > To: Sonal Santan <sonals@xilinx.com> > Cc: Tom Rix <trix@redhat.com>; Lizhi Hou <lizhih@xilinx.com>; linux- > kernel@vger.kernel.org; linux-fpga@vger.kernel.org; Max Zhen > <maxz@xilinx.com>; Michal Simek <michals@xilinx.com>; Stefano Stabellini > <stefanos@xilinx.com>; devicetree@vger.kernel.org; mdf@kernel.org; > robh@kernel.org > Subject: Re: [PATCH V3 XRT Alveo 01/18] Documentation: fpga: Add a > document describing XRT Alveo drivers > > On Mon, Mar 01, 2021 at 06:48:46AM +0000, Sonal Santan wrote: > > Hello Tom, > > > > > -----Original Message----- > > > From: Tom Rix <trix@redhat.com> > > > Sent: Friday, February 19, 2021 2:26 PM > > > To: Lizhi Hou <lizhih@xilinx.com>; linux-kernel@vger.kernel.org > > > Cc: Lizhi Hou <lizhih@xilinx.com>; linux-fpga@vger.kernel.org; Max > > > Zhen <maxz@xilinx.com>; Sonal Santan <sonals@xilinx.com>; Michal > > > Simek <michals@xilinx.com>; Stefano Stabellini > > > <stefanos@xilinx.com>; devicetree@vger.kernel.org; mdf@kernel.org; > > > robh@kernel.org; Max Zhen <maxz@xilinx.com> > > > Subject: Re: [PATCH V3 XRT Alveo 01/18] Documentation: fpga: Add a > > > document describing XRT Alveo drivers > > > > > > From the documentation, there are a couple of big questions and a > > > bunch of word smithing. > > > > > > pseudo-bus : do we need a bus ? > > We are looking for guidance here. > > > > > > xrt-lib real platform devices that aren't fpga, do they need to move > > > to another subsystem ? > > > > > > > Drivers for the IPs that show up in the Alveo shell are not generic > > enough. They fit into the framework that XRT uses. Is the idea that > > that they can be used in a different context? > > > > > Overall looks good, love the ascii art! > > > > > > On 2/17/21 10:40 PM, Lizhi Hou wrote: > > > > Describe XRT driver architecture and provide basic overview of > > > > Xilinx Alveo platform. > > > > > > > > Signed-off-by: Sonal Santan <sonal.santan@xilinx.com> > > > > Signed-off-by: Max Zhen <max.zhen@xilinx.com> > > > > Signed-off-by: Lizhi Hou <lizhih@xilinx.com> > > > > --- > > > > Documentation/fpga/index.rst | 1 + > > > > Documentation/fpga/xrt.rst | 842 > > > +++++++++++++++++++++++++++++++++++ > > > > 2 files changed, 843 insertions(+) create mode 100644 > > > > Documentation/fpga/xrt.rst > > > > > > > > diff --git a/Documentation/fpga/index.rst > > > > b/Documentation/fpga/index.rst index f80f95667ca2..30134357b70d > > > > 100644 > > > > --- a/Documentation/fpga/index.rst > > > > +++ b/Documentation/fpga/index.rst > > > > @@ -8,6 +8,7 @@ fpga > > > > :maxdepth: 1 > > > > > > > > dfl > > > > + xrt > > > > > > > > .. only:: subproject and html > > > > > > > > diff --git a/Documentation/fpga/xrt.rst > > > > b/Documentation/fpga/xrt.rst new file mode 100644 index > > > > 000000000000..9bc2d2785cb9 > > > > --- /dev/null > > > > +++ b/Documentation/fpga/xrt.rst > > > > @@ -0,0 +1,842 @@ > > > > +.. SPDX-License-Identifier: GPL-2.0 > > > > + > > > > +================================== > > > > +XRTV2 Linux Kernel Driver Overview > > > > +================================== > > > > + > > > > +Authors: > > > > + > > > > +* Sonal Santan <sonal.santan@xilinx.com> > > > > +* Max Zhen <max.zhen@xilinx.com> > > > > +* Lizhi Hou <lizhi.hou@xilinx.com> > > > > + > > > > +XRTV2 drivers are second generation `XRT > > > > +<https://github.com/Xilinx/XRT>`_ drivers which support `Alveo > > > > +<https://www.xilinx.com/products/boards-and-kits/alveo.html>`_ > > > > +PCIe platforms from Xilinx. > > > > + > > > > +XRTV2 drivers support *subsystem* style data driven platforms > > > > +where driver's > > > where the driver's > > > > +configuration and behavior is determined by meta data provided by > > > > +the platform (in *device tree* format). Primary management > > > > +physical function (MPF) driver is called **xmgmt**. Primary user > > > > +physical function (UPF) driver is called > > > > +**xuser** and is under development. xrt driver framework and HW > > > > +subsystem drivers are packaged into a library module called > > > > +**xrt-lib**, which is shared by **xmgmt** and **xuser** (under > > > > +development). The xrt driver framework > > > xuser still under development ? > > > > +implements a pseudo-bus which is used to discover HW subsystems > > > > +and facilitate > > > > > > A pseudo-bus. > > > > > > It would be good if this was close to what was done for dfl here > > > > > > https://lore.kernel.org/linux-fpga/1605159759-3439-1-git-send-email- > > > yilun.xu@intel.com/ > > > > > > > I am wondering if we can phase in the migration to formal bus > > architecture based on struct bus_type as a follow on set of patches? > > I'd rather have it done early on. If we know there's a better way of doing > something and we don't the code should go into staging. > > This gives us an out if it doesn't happen, otherwise the kernel community would > depend on corporate goodwill to appropriately staff it. > > Note, I'm not trying to say there's any ill will anywhere, Xilinx has been > traditionally good about this :) Thanks for the suggestion. Since the bus change is a bigger change we will incorporate it into V5 version of the patch series. Meanwhile we will post V4 version of patch series which will addresses other feedback we have received so far. > > > > > > +inter HW subsystem interaction. > > > > + > > > > +Driver Modules > > > > +============== > > > > + > > > > +xrt-lib.ko > > > > +---------- > > > > + > > > > +Repository of all subsystem drivers and pure software modules > > > > +that can potentially > > > > > > subsystem drivers > > > > > > drivers in fpga/ should be for managing just the fpganess of the fpga. > > > > > > soft devices ex/ a soft tty should go to their respective subsystem > > > location > > > > > > Are there any in this patchset you think might move ? > > > > We have already shrunk the patch to only include FPGA centric pieces > > necessary to get the bitstream download implemented. Should we explore > > the question of subsystem drivers when we add support for more > > features of the Alveo shell? > > > > > > > > Maybe we can defer reviewing those now. > > > > > > > +be shared between xmgmt and xuser. All these drivers are > > > > +structured as Linux *platform driver* and are instantiated by > > > > +xmgmt (or xuser under development) based on meta data associated > > > > +with hardware. The metadata is in the form of device tree > > > > > > with the hardware > > > > > > form of a device tree > > > > > > > Will change > > > > > > +as mentioned before. Each platform driver statically defines a > > > > +subsystem node array by using node name or a string in its > > > > +``compatible`` property. And this array is eventually translated > > > > +to IOMEM > > > resources of the platform device. > > > > + > > > > +The xrt-lib core infrastructure provides hooks to platform > > > > +drivers for device node management, user file operations and ioctl > callbacks. > > > > +The core also provides pseudo-bus functionality for platform > > > > +driver registration, discovery and inter platform driver ioctl calls. > > > > > > core infrastructure. > > > > > > > Will update. > > > > > The interfaces to the infrastructure are not in include/linux/fpga/ > > > > > > Maybe this needs to change. > > > > > > > Were you thinking of moving XRT infrastructure header files from > > drivers/fpga/xrt/include to include/linux/fpga? > > > > > > + > > > > +.. note:: > > > > + See code in ``include/xleaf.h`` > > > > + > > > > + > > > > +xmgmt.ko > > > > +-------- > > > > + > > > > +The xmgmt driver is a PCIe device driver driving MPF found on > > > > +Xilinx's Alveo PCIE device. It consists of one *root* driver, one > > > > +or more *group* drivers and one or more *xleaf* drivers. The root > > > > +and MPF specific xleaf drivers are in xmgmt.ko. The group driver > > > > +and other xleaf > > > drivers are in xrt-lib.ko. > > > I am not sure if *.ko is correct, these will also be intree. > > > > + > > > > +The instantiation of specific group driver or xleaf driver is > > > > +completely data > > > of a specific > > > > +driven based on meta data (mostly in device tree format) found > > > > +through VSEC > > > mostly ? what is the deviation from device tree ? > > > > +capability and inside firmware files, such as platform xsabin or > > > > +user xclbin > > > file. > > > > +The root driver manages life cycle of multiple group drivers, > > > > +which, in turn, > > > the life cycle > > > > +manages multiple xleaf drivers. This allows a single set of > > > > +driver code to support > > > > > > set of drivers > > > > > > drop 'code' > > > > > > > Will update > > > > > > +all kinds of subsystems exposed by different shells. The > > > > +difference among all these subsystems will be handled in xleaf > > > > +drivers with root and group drivers being part of the > > > > +infrastructure and provide common services for all leaves found on all > platforms. > > > > + > > > > +The driver object model looks like the following:: > > > > + > > > > + +-----------+ > > > > + | xroot | > > > > + +-----+-----+ > > > > + | > > > > + +-----------+-----------+ > > > > + | | > > > > + v v > > > > + +-----------+ +-----------+ > > > > + | group | ... | group | > > > > + +-----+-----+ +------+----+ > > > > + | | > > > > + | | > > > > + +-----+----+ +-----+----+ > > > > + | | | | > > > > + v v v v > > > > + +-------+ +-------+ +-------+ +-------+ > > > > + | xleaf |..| xleaf | | xleaf |..| xleaf | > > > > + +-------+ +-------+ +-------+ +-------+ > > > > + > > > > +As an example for Xilinx Alveo U50 before user xclbin download, > > > > +the tree looks like the following:: > > > > + > > > > + +-----------+ > > > > + | xmgmt | > > > > + +-----+-----+ > > > > + | > > > > + +-------------------------+--------------------+ > > > > + | | | > > > > + v v v > > > > + +--------+ +--------+ +--------+ > > > > + | group0 | | group1 | | group2 | > > > > + +----+---+ +----+---+ +---+----+ > > > > + | | | > > > > + | | | > > > > + +-----+-----+ +----+-----+---+ +-----+-----+----+--------+ > > > > + | | | | | | | | | > > > > + v v | v v | v v | > > > > + +------------+ +------+ | +------+ +------+ | +------+ > > > > + +------------+ +-----------+ | > > > > + | xmgmt_main | | VSEC | | | GPIO | | QSPI | | | CMC | | > > > > + | AXI-GATE0 | | > > > > + +------------+ +------+ | +------+ +------+ | +------+ > > > > + +------------+ +-----------+ | > > > > + | +---------+ | +------+ +-----------+ | > > > > + +>| MAILBOX | +->| ICAP | | AXI-GATE1 |<+ > > > > + +---------+ | +------+ +-----------+ > > > > + | +-------+ > > > > + +->| CALIB | > > > > + +-------+ > > > > + > > > Nice ascii art! > > > > +After an xclbin is download, group3 will be added and the tree > > > > +looks like the > > > > +following:: > > > > + > > > > + +-----------+ > > > > + | xmgmt | > > > > + +-----+-----+ > > > > + | > > > > + +-------------------------+--------------------+-----------------+ > > > > + | | | | > > > > + v v v | > > > > + +--------+ +--------+ +--------+ | > > > > + | group0 | | group1 | | group2 | | > > > > + +----+---+ +----+---+ +---+----+ | > > > > + | | | | > > > > + | | | | > > > > + +-----+-----+ +-----+-----+---+ +-----+-----+----+--------+ | > > > > + | | | | | | | | | | > > > > + v v | v v | v v | | > > > > + +------------+ +------+ | +------+ +------+ | +------+ +-----------+ | | > > > > + | xmgmt_main | | VSEC | | | GPIO | | QSPI | | | CMC | | > > > > + | AXI-GATE0 | | > > > | > > > > + +------------+ +------+ | +------+ +------+ | +------+ +-----------+ | | > > > > + | +---------+ | +------+ +-----------+ | | > > > > + +>| MAILBOX | +->| ICAP | | AXI-GATE1 |<+ | > > > > + +---------+ | +------+ +-----------+ | > > > > + | +-------+ | > > > > + +->| CALIB | | > > > > + +-------+ | > > > > + +---+----+ | > > > > + | group3 |<--------------------------------------------+ > > > > + +--------+ > > > > + | > > > > + | > > > > + +-------+--------+---+--+--------+------+-------+ > > > > + | | | | | | | > > > > + v | v | v | v > > > > + +--------+ | +--------+ | +--------+ | +-----+ > > > > + | CLOCK0 | | | CLOCK1 | | | CLOCK2 | | | UCS | > > > > + +--------+ v +--------+ v +--------+ v +-----+ > > > > + +-------------+ +-------------+ +-------------+ > > > > + | CLOCK-FREQ0 | | CLOCK-FREQ1 | | CLOCK-FREQ2 | > > > > + +-------------+ +-------------+ +-------------+ > > > > + > > > > + > > > > +xmgmt-root > > > > +^^^^^^^^^^ > > > > + > > > > +The xmgmt-root driver is a PCIe device driver attached to MPF. > > > > +It's part of the infrastructure of the MPF driver and resides in xmgmt.ko. > > > > +This driver > > > > + > > > > +* manages one or more group drivers > > > > +* provides access to functionalities that requires pci_dev, such > > > > +as PCIE config > > > > + space access, to other xleaf drivers through root calls > > > > +* together with group driver, facilities event callbacks for > > > > +other xleaf drivers > > > > +* together with group driver, facilities inter-leaf driver calls > > > > +for other xleaf > > > Maybe drop 'together with group driver' > > > > Will update > > > > > > + drivers > > > > + > > > > +When root driver starts, it will explicitly create an initial > > > > +group instance, which contains xleaf drivers that will trigger > > > > +the creation of other group instances. The root driver will wait > > > > +for all group and leaves to be created before it returns from > > > > +it's probe routine and claim success of the initialization of the entire > xmgmt driver. > > > What happens if there a failure in one leaf ? Does the whole board go down > ? > > > > + > > > > +.. note:: > > > > + See code in ``lib/xroot.c`` and ``mgmt/root.c`` > > > > + > > > > + > > > > +group > > > > +^^^^^ > > > > + > > > > +The group driver is a platform device driver whose life cycle is > > > > +managed by > > > Maybe call this a 'pseudo device' > > > > Will update > > > > > > +root and does not have real IO mem or IRQ resources. It's part of > > > > +the infrastructure of the MPF driver and resides in xrt-lib.ko. > > > > +This driver > > > > + > > > > +* manages one or more xleaf drivers so that multiple leaves can > > > > +be managed as a > > > > + group > > > can drop 'so that multiple leaves can be managed as a group' to me, > > > this is the same as 'one or more' > > > > Will do > > > > > > +* provides access to root from leaves, so that root calls, event > > > > +notifications > > > > + and inter-leaf calls can happen > > > > + > > > > +In xmgmt, an initial group driver instance will be created by > > > > +root, which > > > by the root > > > > +contains leaves that will trigger group instances to be created > > > > +to manage groups of leaves found on different partitions on > > > > +hardware, such as VSEC, Shell, and User. > > > > + > > > > +Every *fpga_region* has a group object associated with it. The > > > > +group is created when xclbin image is loaded on the fpga_region. > > > > +The existing group is destroyed when a new xclbin image is > > > > +loaded. The fpga_region persists across xclbin downloads. > > > The connection of a 'group' node to a fpga region region is fairly > > > important, maybe move this section earlier. 'group' as an fpganess > > > thing would be kept in fpga/ subsystem. > > > > Will update > > > > > > + > > > > +.. note:: > > > > + See code in ``lib/group.c`` > > > > + > > > > + > > > > +xleaf > > > > +^^^^^ > > > > + > > > > +The xleaf driver is a platform device driver whose life cycle is > > > > +managed by a group driver and may or may not have real IO mem or > > > > +IRQ resources. They are the real meat of xmgmt and contains > > > > +platform specific code to Shell and User found on a MPF. > > > > + > > > > > > Maybe a split is pseudo device leaves, those without real IO mem, > > > stay in fpga/ others go ? > > > > > > > This goes back to the earlier question of what minimal set of platform > > drivers should stay in fpga subsystem. There are some like bridge or > > configuration engine (also called icap) which have their own IO mem > > but do not have a life outside of fpga subsystem. > > > > > > +A xleaf driver may not have real hardware resources when it > > > > +merely acts as a driver that manages certain in-memory states for > xmgmt. > > > > +These in-memory states could be shared by multiple other leaves. > > > > + > > > This implies locking and some message passing. > > > > +Leaf drivers assigned to specific hardware resources drive > > > > +specific subsystem in > > > drive a specific > > > > +the device. To manipulate the subsystem or carry out a task, a > > > > +xleaf driver may ask help from root via root calls and/or from > > > > +other leaves via > > > inter-leaf calls. > > > > + > > > > +A xleaf can also broadcast events through infrastructure code for > > > > +other leaves to process. It can also receive event notification > > > > +from infrastructure about certain events, such as post-creation > > > > +or pre-exit of a > > > particular xleaf. > > > I would like to see some examples of how the inter node communications > work. > > > > Would update to show an example. > > > > > > + > > > > +.. note:: > > > > + See code in ``lib/xleaf/*.c`` > > > > + > > > > + > > > > +FPGA Manager Interaction > > > > +======================== > > > > + > > > > +fpga_manager > > > > +------------ > > > > + > > > > +An instance of fpga_manager is created by xmgmt_main and is used > > > > +for xclbin > > > for the xclbin > > > > +image download. fpga_manager requires the full xclbin image > > > > +before it can start programming the FPGA configuration engine via > > > > +ICAP platform > > > driver. > > > > > > via the ICAP > > > > > > what is ICAP ? > > > > Will update. ICAP stands for Internal Configuration Access Port used > > for configuring the fpga. > > > > > > > > > + > > > > +fpga_region > > > > +----------- > > > > + > > > > +For every interface exposed by currently loaded xclbin/xsabin in > > > > +the > > > > +*parent* > > > by the currently > > > > +fpga_region a new instance of fpga_region is created like a *child* > region. > > > fpga_region, > > > > +The device tree of the *parent* fpga_region defines the resources > > > > +for a new instance of fpga_bridge which isolates the parent from > > > and isolates > > > > +child fpga_region. This new instance of fpga_bridge will be used > > > > +when a xclbin image is loaded on the child fpga_region. After the > > > > +xclbin image is downloaded to the fpga_region, an instance of > > > > +group is created for the fpga_region using the device tree > > > > +obtained as part of xclbin. If this device > > > of the xclbin > > > > +tree defines any child interfaces then it can trigger the > > > > +creation of > > > interfaces, then > > > > +fpga_bridge and fpga_region for the next region in the chain. > > > a fpga_bridge and a fpga_region > > > > + > > > > +fpga_bridge > > > > +----------- > > > > + > > > > +Like fpga_region, matching fpga_bridge is also created by walking > > > > +the device > > > Like the fpga_region, a matchin > > > > +tree of the parent group. > > > > + > > > > +Driver Interfaces > > > > +================= > > > > + > > > > +xmgmt Driver Ioctls > > > > +------------------- > > > > + > > > > +Ioctls exposed by xmgmt driver to user space are enumerated in > > > > +the following > > > > +table: > > > > + > > > > +== ===================== ============================ > > > ========================== > > > > +# Functionality ioctl request code data format > > > > +== ===================== ============================ > > > ========================== > > > > +1 FPGA image download XMGMT_IOCICAPDOWNLOAD_AXLF > > > xmgmt_ioc_bitstream_axlf > > > > +== ===================== ============================ > > > > +========================== > > > > > > This data format is described below, maybe swap this section with > > > that so > > > > > > folks will know what xmgmnt_ioc_bitstream_axlf is before this section. > > > > > > > Will update. > > > > > > + > > > > +User xclbin can be downloaded by using xbmgmt tool from XRT open > > > > +source suite. See > > > > > > A user xclbin > > > > > > using the xbmgmt > > > > > > from the XRT > > > > > > > Will update > > > > > > +example usage below:: > > > > + > > > > + xbmgmt partition --program --path > > > > + /lib/firmware/xilinx/862c7020a250293e32036f19956669e5/test/verif > > > > + y.xc > > > > + lbin --force > > > > + > > > > +xmgmt Driver Sysfs > > > > +------------------ > > > > + > > > > +xmgmt driver exposes a rich set of sysfs interfaces. Subsystem > > > > +platform drivers export sysfs node for every platform instance. > > > > + > > > > +Every partition also exports its UUIDs. See below for examples:: > > > > + > > > > + /sys/bus/pci/devices/0000:06:00.0/xmgmt_main.0/interface_uuids > > > > + /sys/bus/pci/devices/0000:06:00.0/xmgmt_main.0/logic_uuids > > > > + > > > > + > > > > +hwmon > > > > +----- > > > > + > > > > +xmgmt driver exposes standard hwmon interface to report voltage, > > > > +current, temperature, power, etc. These can easily be viewed > > > > +using > > > > +*sensors* command line utility. > > > > + > > > > +Alveo Platform Overview > > > > +======================= > > > > + > > > > +Alveo platforms are architected as two physical FPGA partitions: > > > > +*Shell* and *User*. The Shell provides basic infrastructure for > > > > +the Alveo platform like PCIe connectivity, board management, > > > > +Dynamic Function Exchange (DFX), sensors, clocking, reset, and > > > > +security. User partition contains user compiled FPGA > > > the user compiled > > > > +binary which is loaded by a process called DFX also known as > > > > +partial reconfiguration. > > > > + > > > > +Physical partitions require strict HW compatibility with each > > > > +other for DFX to work properly. > > > > > > swap order > > > > > > For DFX to work properly physical partitions .. > > > > > > > > > > Will update > > > > > > Every physical partition has two interface UUIDs: *parent* UUID > > > > +and *child* UUID. For simple single stage platforms, Shell → User > > > > +forms parent child relationship. For complex two stage platforms, > > > > +Base → Shell → User forms the parent child relationship chain. > > > this bit is confusing. is this related to uuid? > > > > + > > > > +.. note:: > > > > + Partition compatibility matching is key design component of > > > > +Alveo > > > platforms > > > > + and XRT. Partitions have child and parent relationship. A > > > > +loaded partition > > > have a child > > > > + exposes child partition UUID to advertise its compatibility > > > > + requirement for > > > > > > the child's > > > > > > can drop 'for child partition' > > > > Will update > > > > > > > > > + child partition. When loading a child partition the xmgmt > > > > + management driver > > > When loading a child partition, > > > > + matches parent UUID of the child partition against child UUID exported > by > > > > + the parent. Parent and child partition UUIDs are stored in the *xclbin* > > > > + (for user) or *xsabin* (for base and shell). > > > > > > this is confusing, is this part of the file image format ? > > > > > > Maybe save/move till the image layout. > > > > Yes these IDs are stored in xclbin image format. Will move the > > sections around as suggested. > > > > > > > > > Except for root UUID, VSEC, > > > > + hardware itself does not know about UUIDs. UUIDs are stored in > > > > + xsabin > > > and > > > > + xclbin. > > > This is confusing too, not sure how to untangle. > > > > Will reword. > > > > > > + > > > > + > > > > +The physical partitions and their loading is illustrated below:: > > > > + > > > > + SHELL USER > > > > + +-----------+ +-------------------+ > > > > + | | | | > > > > + | VSEC UUID | CHILD PARENT | LOGIC UUID | > > > > + | o------->|<--------o | > > > > + | | UUID UUID | | > > > > + +-----+-----+ +--------+----------+ > > > > + | | > > > > + . . > > > > + | | > > > > + +---+---+ +------+--------+ > > > > + | POR | | USER COMPILED | > > > > + | FLASH | | XCLBIN | > > > > + +-------+ +---------------+ > > > > + > > > > + > > > > +Loading Sequence > > > > +---------------- > > > > + > > > > +The Shell partition is loaded from flash at system boot time. It > > > > +establishes the PCIe link and exposes two physical functions to > > > > +the BIOS. After OS boot, xmgmt > > > the OS boots, the xmgmt > > > > +driver attaches to PCIe physical function 0 exposed by the Shell > > > > +and then looks for VSEC in PCIe extended configuration space. > > > > +Using VSEC it determines the logic > > > > > > the PCIe > > > > > > The driver uses VSEC to determine the UUID of Shell. The UUID is > > > also used to load a matching ... > > > > > > > Will update > > > > > > +UUID of Shell and uses the UUID to load matching *xsabin* file > > > > +from Linux firmware directory. The xsabin file contains metadata > > > > +to discover peripherals that are part of Shell and firmware(s) > > > > +for any > > > embedded soft processors in Shell. > > > the firmware needed for any ... > > > > Will update > > > > > > + > > > > +The Shell exports child interface UUID which is used for > > > > +compatibility check when > > > > > > export a child > > > > > > for a compatibility check > > > > > > > Will update > > > > > > +loading user compiled xclbin over the User partition as part of DFX. > > > > +When a user requests loading of a specific xclbin the xmgmt > > > > +management driver reads the parent > > > xclbin, the > > > > +interface UUID specified in the xclbin and matches it with child > > > > +interface UUID exported by Shell to determine if xclbin is > > > > +compatible with the Shell. If match fails loading of xclbin is denied. > > > > + > > > > +xclbin loading is requested using ICAP_DOWNLOAD_AXLF ioctl > command. > > > > +When loading xclbin, xmgmt driver performs the following > > > > +*logical* > > > operations: > > > > + > > > > +1. Copy xclbin from user to kernel memory 2. Sanity check the > > > > +xclbin contents 3. Isolate the User partition 4. Download the > > > > +bitstream using the FPGA config engine (ICAP) 5. De-isolate the > > > > +User partition 6. Program the clocks (ClockWiz) driving the User > > > > +partition > > > maybe drop '(ClockWiz)' > > > > +7. Wait for memory controller (MIG) calibration > > > for the > > > > +8. Return the loading status back to the caller > > > > + > > > > +`Platform Loading Overview > > > > +<https://xilinx.github.io/XRT/master/html/platforms_partitions.ht > > > > +ml>` _ provides more detailed information on platform loading. > > > > + > > > the link works. > > > > + > > > > +xsabin > > > > +------ > > > > + > > > > +Each Alveo platform comes packaged with its own xsabin. The > > > > +xsabin is trusted > > > is a trusted > > > > +component of the platform. For format details refer to > > > > +:ref:`xsabin_xclbin_container_format` > > > > +below. xsabin contains basic information like UUIDs, platform > > > > +name and metadata in the form of device tree. See > > > > +:ref:`device_tree_usage` > > > below for details and example. > > > of a device > > > > + > > > > +xclbin > > > > +------ > > > > + > > > > +xclbin is compiled by end user using `Vitis > > > > +<https://www.xilinx.com/products/design-tools/vitis/vitis-platfor > > > > +m.ht > > > > +ml>`_ > > > this link works, seems reasonable landing > > > > +tool set from Xilinx. The xclbin contains sections describing > > > > +user compiled acceleration engines/kernels, memory subsystems, > > > > +clocking information etc. It also contains bitstream for the user > > > > +partition, UUIDs, platform name, etc. xclbin uses > > > bitstreams > > > > +the same container format as xsabin which is described below. > > > > + > > > > + > > > > +.. _xsabin_xclbin_container_format: > > > > + > > > > +xsabin/xclbin Container Format > > > > +------------------------------ > > > > + > > > > +xclbin/xsabin is ELF-like binary container format. It is > > > > +structured as series of sections. There is a file header followed > > > > +by several section headers which is followed by sections. A > > > > +section header points to an actual section. There is an optional > > > > +signature at the end. The > > > format is defined by header file ``xclbin.h``. > > > > +The following figure illustrates a typical xclbin:: > > > > + > > > > + > > > > + +---------------------+ > > > > + | | > > > > + | HEADER | > > > > + +---------------------+ > > > > + | SECTION HEADER | > > > > + | | > > > > + +---------------------+ > > > > + | ... | > > > > + | | > > > > + +---------------------+ > > > > + | SECTION HEADER | > > > > + | | > > > > + +---------------------+ > > > > + | SECTION | > > > > + | | > > > > + +---------------------+ > > > > + | ... | > > > > + | | > > > > + +---------------------+ > > > > + | SECTION | > > > > + | | > > > > + +---------------------+ > > > > + | SIGNATURE | > > > > + | (OPTIONAL) | > > > > + +---------------------+ > > > > + > > > > + > > > > +xclbin/xsabin files can be packaged, un-packaged and inspected > > > > +using XRT utility called **xclbinutil**. xclbinutil is part of > > > > +XRT open source software stack. The source code for xclbinutil > > > > +can be found at > > > > +https://github.com/Xilinx/XRT/tree/master/src/runtime_src/tools/x > > > > +clbi > > > > +nutil > > > > + > > > Works, but maybe the location of a manpage or doc would be better. > > > > +For example to enumerate the contents of a xclbin/xsabin use the > > > > +*--info* switch as shown below:: > > > > + > > > > + > > > > + xclbinutil --info --input > > > > + /opt/xilinx/firmware/u50/gen3x16-xdma/blp/test/bandwidth.xclbin > > > > + xclbinutil --info --input > > > > + /lib/firmware/xilinx/862c7020a250293e32036f19956669e5/partition. > > > > + xsab > > > > + in > > > > + > > > > + > > > > +.. _device_tree_usage: > > > > + > > > > +Device Tree Usage > > > > +----------------- > > > > + > > > > +As mentioned previously xsabin stores metadata which advertise HW > > > > +subsystems present in a partition. The metadata is stored in > > > > +device tree > > > format with well defined schema. > > > > +XRT management driver uses this information to bind *platform > > > > +drivers* to the subsystem instantiations. The platform drivers > > > > +are found in **xrt-lib.ko** kernel module defined later. > > > > + > > > > +Logic UUID > > > > +^^^^^^^^^^ > > > > +A partition is identified uniquely through ``logic_uuid`` property:: > > > > + > > > > + /dts-v1/; > > > > + / { > > > > + logic_uuid = "0123456789abcdef0123456789abcdef"; > > > > + ... > > > > + } > > > > + > > > > +Schema Version > > > > +^^^^^^^^^^^^^^ > > > > +Schema version is defined through ``schema_version`` node. And it > > > > +contains ``major`` and ``minor`` properties as below:: > > > > + > > > > + /dts-v1/; > > > > + / { > > > > + schema_version { > > > > + major = <0x01>; > > > > + minor = <0x00>; > > > > + }; > > > > + ... > > > > + } > > > > + > > > > +Partition UUIDs > > > > +^^^^^^^^^^^^^^^ > > > > +As said earlier, each partition may have parent and child UUIDs. > > > > +These UUIDs are defined by ``interfaces`` node and > > > > +``interface_uuid`` > > > property:: > > > > + > > > > + /dts-v1/; > > > > + / { > > > > + interfaces { > > > > + @0 { > > > > + interface_uuid = "0123456789abcdef0123456789abcdef"; > > > > + }; > > > > + @1 { > > > > + interface_uuid = "fedcba9876543210fedcba9876543210"; > > > > + }; > > > > + ... > > > > + }; > > > > + ... > > > > + } > > > > + > > > > + > > > > +Subsystem Instantiations > > > > +^^^^^^^^^^^^^^^^^^^^^^^^ > > > > +Subsystem instantiations are captured as children of > > > > +``addressable_endpoints`` > > > > +node:: > > > > + > > > > + /dts-v1/; > > > > + / { > > > > + addressable_endpoints { > > > > + abc { > > > > + ... > > > > + }; > > > > + def { > > > > + ... > > > > + }; > > > > + ... > > > > + } > > > > + } > > > > + > > > > +Subnode 'abc' and 'def' are the name of subsystem nodes > > > > + > > > > +Subsystem Node > > > > +^^^^^^^^^^^^^^ > > > > +Each subsystem node and its properties define a hardware instance:: > > > > + > > > > + > > > > + addressable_endpoints { > > > > + abc { > > > > + reg = <0xa 0xb> > > > > + pcie_physical_function = <0x0>; > > > > + pcie_bar_mapping = <0x2>; > > > > + compatible = "abc def"; > > > > + firmware { > > > > + firmware_product_name = "abc" > > > > + firmware_branch_name = "def" > > > > + firmware_version_major = <1> > > > > + firmware_version_minor = <2> > > > > + }; > > > > + } > > > > + ... > > > > + } > > > > + > > > > +:reg: > > > > + Property defines address range. '<0xa 0xb>' is BAR offset and > > > > +length pair, both are 64-bit integer. > > > > +:pcie_physical_function: > > > > + Property specifies which PCIe physical function the subsystem node > resides. > > > > +:pcie_bar_mapping: > > > > + Property specifies which PCIe BAR the subsystem node resides. > > > > +'<0x2>' is BAR index and it is 0 if this property is not defined. > > > > +:compatible: > > > > + Property is a list of strings. The first string in the list > > > > +specifies the exact subsystem node. The following strings > > > > +represent other devices that the device is compatible with. > > > > +:firmware: > > > > + Subnode defines the firmware required by this subsystem node. > > > > + > > > > +Alveo U50 Platform Example > > > > +^^^^^^^^^^^^^^^^^^^^^^^^^^ > > > > +:: > > > > + > > > > + /dts-v1/; > > > > + > > > > + /{ > > > > + logic_uuid = "f465b0a3ae8c64f619bc150384ace69b"; > > > > + > > > > + schema_version { > > > > + major = <0x01>; > > > > + minor = <0x00>; > > > > + }; > > > > + > > > > + interfaces { > > > > + > > > > + @0 { > > > > + interface_uuid = "862c7020a250293e32036f19956669e5"; > > > > + }; > > > > + }; > > > > + > > > > + addressable_endpoints { > > > > + > > > > + ep_blp_rom_00 { > > > > + reg = <0x00 0x1f04000 0x00 0x1000>; > > > > + pcie_physical_function = <0x00>; > > > > + compatible = > > > > + "xilinx.com,reg_abs-axi_bram_ctrl- > > > 1.0\0axi_bram_ctrl"; > > > > + }; > > > > + > > > > + ep_card_flash_program_00 { > > > > + reg = <0x00 0x1f06000 0x00 0x1000>; > > > > + pcie_physical_function = <0x00>; > > > > + compatible = > > > > + "xilinx.com,reg_abs-axi_quad_spi- > > > 1.0\0axi_quad_spi"; > > > > + interrupts = <0x03 0x03>; > > > > + }; > > > > + > > > > + ep_cmc_firmware_mem_00 { > > > > + reg = <0x00 0x1e20000 0x00 0x20000>; > > > > + pcie_physical_function = <0x00>; > > > > + compatible = > > > > + "xilinx.com,reg_abs-axi_bram_ctrl-1.0\0axi_bram_ctrl"; > > > > + > > > > + firmware { > > > > + firmware_product_name = "cmc"; > > > > + firmware_branch_name = "u50"; > > > > + firmware_version_major = <0x01>; > > > > + firmware_version_minor = <0x00>; > > > > + }; > > > > + }; > > > > + > > > > + ep_cmc_intc_00 { > > > > + reg = <0x00 0x1e03000 0x00 0x1000>; > > > > + pcie_physical_function = <0x00>; > > > > + compatible = "xilinx.com,reg_abs-axi_intc-1.0\0axi_intc"; > > > > + interrupts = <0x04 0x04>; > > > > + }; > > > > + > > > > + ep_cmc_mutex_00 { > > > > + reg = <0x00 0x1e02000 0x00 0x1000>; > > > > + pcie_physical_function = <0x00>; > > > > + compatible = "xilinx.com,reg_abs-axi_gpio- > 1.0\0axi_gpio"; > > > > + }; > > > > + > > > > + ep_cmc_regmap_00 { > > > > + reg = <0x00 0x1e08000 0x00 0x2000>; > > > > + pcie_physical_function = <0x00>; > > > > + compatible = > > > > + "xilinx.com,reg_abs-axi_bram_ctrl-1.0\0axi_bram_ctrl"; > > > > + > > > > + firmware { > > > > + firmware_product_name = "sc-fw"; > > > > + firmware_branch_name = "u50"; > > > > + firmware_version_major = <0x05>; > > > > + }; > > > > + }; > > > > + > > > > + ep_cmc_reset_00 { > > > > + reg = <0x00 0x1e01000 0x00 0x1000>; > > > > + pcie_physical_function = <0x00>; > > > > + compatible = "xilinx.com,reg_abs-axi_gpio- > 1.0\0axi_gpio"; > > > > + }; > > > > + > > > > + ep_ddr_mem_calib_00 { > > > > + reg = <0x00 0x63000 0x00 0x1000>; > > > > + pcie_physical_function = <0x00>; > > > > + compatible = "xilinx.com,reg_abs-axi_gpio- > 1.0\0axi_gpio"; > > > > + }; > > > > + > > > > + ep_debug_bscan_mgmt_00 { > > > > + reg = <0x00 0x1e90000 0x00 0x10000>; > > > > + pcie_physical_function = <0x00>; > > > > + compatible = > > > > + "xilinx.com,reg_abs-debug_bridge- > > > 1.0\0debug_bridge"; > > > > + }; > > > > + > > > > + ep_ert_base_address_00 { > > > > + reg = <0x00 0x21000 0x00 0x1000>; > > > > + pcie_physical_function = <0x00>; > > > > + compatible = "xilinx.com,reg_abs-axi_gpio- > 1.0\0axi_gpio"; > > > > + }; > > > > + > > > > + ep_ert_command_queue_mgmt_00 { > > > > + reg = <0x00 0x40000 0x00 0x10000>; > > > > + pcie_physical_function = <0x00>; > > > > + compatible = > > > > + "xilinx.com,reg_abs-ert_command_queue- > > > 1.0\0ert_command_queue"; > > > > + }; > > > > + > > > > + ep_ert_command_queue_user_00 { > > > > + reg = <0x00 0x40000 0x00 0x10000>; > > > > + pcie_physical_function = <0x01>; > > > > + compatible = > > > > + "xilinx.com,reg_abs-ert_command_queue- > > > 1.0\0ert_command_queue"; > > > > + }; > > > > + > > > > + ep_ert_firmware_mem_00 { > > > > + reg = <0x00 0x30000 0x00 0x8000>; > > > > + pcie_physical_function = <0x00>; > > > > + compatible = > > > > + "xilinx.com,reg_abs-axi_bram_ctrl-1.0\0axi_bram_ctrl"; > > > > + > > > > + firmware { > > > > + firmware_product_name = "ert"; > > > > + firmware_branch_name = "v20"; > > > > + firmware_version_major = <0x01>; > > > > + }; > > > > + }; > > > > + > > > > + ep_ert_intc_00 { > > > > + reg = <0x00 0x23000 0x00 0x1000>; > > > > + pcie_physical_function = <0x00>; > > > > + compatible = "xilinx.com,reg_abs-axi_intc-1.0\0axi_intc"; > > > > + interrupts = <0x05 0x05>; > > > > + }; > > > > + > > > > + ep_ert_reset_00 { > > > > + reg = <0x00 0x22000 0x00 0x1000>; > > > > + pcie_physical_function = <0x00>; > > > > + compatible = "xilinx.com,reg_abs-axi_gpio- > 1.0\0axi_gpio"; > > > > + }; > > > > + > > > > + ep_ert_sched_00 { > > > > + reg = <0x00 0x50000 0x00 0x1000>; > > > > + pcie_physical_function = <0x01>; > > > > + compatible = "xilinx.com,reg_abs-ert_sched- > 1.0\0ert_sched"; > > > > + interrupts = <0x09 0x0c>; > > > > + }; > > > > + > > > > + ep_fpga_configuration_00 { > > > > + reg = <0x00 0x1e88000 0x00 0x8000>; > > > > + pcie_physical_function = <0x00>; > > > > + compatible = > > > > + "xilinx.com,reg_abs-axi_hwicap- > > > 1.0\0axi_hwicap"; > > > > + interrupts = <0x02 0x02>; > > > > + }; > > > > + > > > > + ep_icap_reset_00 { > > > > + reg = <0x00 0x1f07000 0x00 0x1000>; > > > > + pcie_physical_function = <0x00>; > > > > + compatible = "xilinx.com,reg_abs-axi_gpio- > 1.0\0axi_gpio"; > > > > + }; > > > > + > > > > + ep_msix_00 { > > > > + reg = <0x00 0x00 0x00 0x20000>; > > > > + pcie_physical_function = <0x00>; > > > > + compatible = "xilinx.com,reg_abs-msix-1.0\0msix"; > > > > + pcie_bar_mapping = <0x02>; > > > > + }; > > > > + > > > > + ep_pcie_link_mon_00 { > > > > + reg = <0x00 0x1f05000 0x00 0x1000>; > > > > + pcie_physical_function = <0x00>; > > > > + compatible = "xilinx.com,reg_abs-axi_gpio- > 1.0\0axi_gpio"; > > > > + }; > > > > + > > > > + ep_pr_isolate_plp_00 { > > > > + reg = <0x00 0x1f01000 0x00 0x1000>; > > > > + pcie_physical_function = <0x00>; > > > > + compatible = "xilinx.com,reg_abs-axi_gpio- > 1.0\0axi_gpio"; > > > > + }; > > > > + > > > > + ep_pr_isolate_ulp_00 { > > > > + reg = <0x00 0x1000 0x00 0x1000>; > > > > + pcie_physical_function = <0x00>; > > > > + compatible = "xilinx.com,reg_abs-axi_gpio- > 1.0\0axi_gpio"; > > > > + }; > > > > + > > > > + ep_uuid_rom_00 { > > > > + reg = <0x00 0x64000 0x00 0x1000>; > > > > + pcie_physical_function = <0x00>; > > > > + compatible = > > > > + "xilinx.com,reg_abs-axi_bram_ctrl- > > > 1.0\0axi_bram_ctrl"; > > > > + }; > > > > + > > > > + ep_xdma_00 { > > > > + reg = <0x00 0x00 0x00 0x10000>; > > > > + pcie_physical_function = <0x01>; > > > > + compatible = "xilinx.com,reg_abs-xdma-1.0\0xdma"; > > > > + pcie_bar_mapping = <0x02>; > > > > + }; > > > > + }; > > > > + > > > > + } > > > > + > > > > + > > > > + > > > > +Deployment Models > > > > +================= > > > > + > > > > +Baremetal > > > > +--------- > > > > + > > > > +In bare-metal deployments both MPF and UPF are visible and > > > > +accessible. xmgmt > > > In bare-meta deployments, > > > > +driver binds to MPF. xmgmt driver operations are privileged and > > > > +available to system administrator. The full stack is illustrated below:: > > > > + > > > > + HOST > > > > + > > > > + [XMGMT] [XUSER] > > > > + | | > > > > + | | > > > > + +-----+ +-----+ > > > > + | MPF | | UPF | > > > > + | | | | > > > > + | PF0 | | PF1 | > > > > + +--+--+ +--+--+ > > > > + ......... ^................. ^.......... > > > > + | | > > > > + | PCIe DEVICE | > > > > + | | > > > > + +--+------------------+--+ > > > > + | SHELL | > > > > + | | > > > > + +------------------------+ > > > > + | USER | > > > > + | | > > > > + | | > > > > + | | > > > > + | | > > > > + +------------------------+ > > > > + > > > > + > > > > + > > > > +Virtualized > > > > +----------- > > > > + > > > > +In virtualized deployments privileged MPF is assigned to host but > > > > +unprivileged > > > In virtualized deployments, the > > > > +UPF is assigned to guest VM via PCIe pass-through. xmgmt driver > > > > +in host binds > > > in the host > > > > +to MPF. xmgmt driver operations are privileged and only > > > > +accessible by hosting > > > to the MPF > > > > +service provider. The full stack is illustrated below:: > > > > + > > > > + > > > > + ............. > > > > + HOST . VM . > > > > + . . > > > > + [XMGMT] . [XUSER] . > > > > + | . | . > > > > + | . | . > > > > + +-----+ . +-----+ . > > > > + | MPF | . | UPF | . > > > > + | | . | | . > > > > + | PF0 | . | PF1 | . > > > > + +--+--+ . +--+--+ . > > > > + ......... ^................. ^.......... > > > > + | | > > > > + | PCIe DEVICE | > > > > + | | > > > > + +--+------------------+--+ > > > > + | SHELL | > > > > + | | > > > > + +------------------------+ > > > > + | USER | > > > > + | | > > > > + | | > > > > + | | > > > > + | | > > > > + +------------------------+ > > > > + > > > > + > > > > + > > > > + > > > > + > > > > +Platform Security Considerations > > > > +================================ > > > > + > > > > +`Security of Alveo Platform > > > > +<https://xilinx.github.io/XRT/master/html/security.html>`_ > > > > +discusses the deployment options and security implications in great > detail. > > > > > > This link works and looks great. > > > > > > Tom > > > > Thanks for the detailed review of the document. I am working on > > incorporating the feedback. One outstanding question is about usage of > > formal bus in XRT and if we should phase that in as a follow-on. It > > would also determine if IP drivers should move to other subsystems. > > > > -Sonal > > - Moritz -Sonal
Hi Tom, On 2/25/21 1:59 PM, Tom Rix wrote: > CAUTION: This message has originated from an External Source. Please use proper judgment and caution when opening attachments, clicking links, or responding to this email. > > > On 2/17/21 10:40 PM, Lizhi Hou wrote: >> infrastructure code providing APIs for managing leaf driver instance >> groups, facilitating inter-leaf driver calls and root calls, managing leaf >> driver device nodes. >> >> Signed-off-by: Sonal Santan<sonal.santan@xilinx.com> >> Signed-off-by: Max Zhen<max.zhen@xilinx.com> >> Signed-off-by: Lizhi Hou<lizhih@xilinx.com> >> --- >> drivers/fpga/xrt/include/events.h | 48 ++ >> drivers/fpga/xrt/include/subdev_id.h | 43 ++ >> drivers/fpga/xrt/include/xleaf.h | 276 +++++++++ >> drivers/fpga/xrt/lib/cdev.c | 231 +++++++ >> drivers/fpga/xrt/lib/subdev.c | 871 +++++++++++++++++++++++++++ >> drivers/fpga/xrt/lib/subdev_pool.h | 53 ++ >> drivers/fpga/xrt/lib/xroot.c | 598 ++++++++++++++++++ >> 7 files changed, 2120 insertions(+) >> create mode 100644 drivers/fpga/xrt/include/events.h >> create mode 100644 drivers/fpga/xrt/include/subdev_id.h >> create mode 100644 drivers/fpga/xrt/include/xleaf.h >> create mode 100644 drivers/fpga/xrt/lib/cdev.c >> create mode 100644 drivers/fpga/xrt/lib/subdev.c >> create mode 100644 drivers/fpga/xrt/lib/subdev_pool.h >> create mode 100644 drivers/fpga/xrt/lib/xroot.c >> >> diff --git a/drivers/fpga/xrt/include/events.h b/drivers/fpga/xrt/include/events.h >> new file mode 100644 >> index 000000000000..2a9aae8bceb4 >> --- /dev/null >> +++ b/drivers/fpga/xrt/include/events.h >> @@ -0,0 +1,48 @@ >> +/* SPDX-License-Identifier: GPL-2.0 */ >> +/* >> + * Header file for Xilinx Runtime (XRT) driver > general problem with generic, low information comments This is removed. >> + * >> + * Copyright (C) 2020-2021 Xilinx, Inc. >> + * >> + * Authors: >> + * Cheng Zhen<maxz@xilinx.com> >> + */ >> + >> +#ifndef _XRT_EVENTS_H_ >> +#define _XRT_EVENTS_H_ >> + >> +#include <linux/platform_device.h> > why is platform_device.h needed ? It is not needed. Removed. >> +#include "subdev_id.h" >> + >> +/* >> + * Event notification. >> + */ >> +enum xrt_events { >> + XRT_EVENT_TEST = 0, /* for testing */ >> + /* >> + * Events related to specific subdev >> + * Callback arg: struct xrt_event_arg_subdev >> + */ >> + XRT_EVENT_POST_CREATION, >> + XRT_EVENT_PRE_REMOVAL, >> + /* >> + * Events related to change of the whole board >> + * Callback arg: <none> >> + */ >> + XRT_EVENT_PRE_HOT_RESET, >> + XRT_EVENT_POST_HOT_RESET, >> + XRT_EVENT_PRE_GATE_CLOSE, >> + XRT_EVENT_POST_GATE_OPEN, >> +}; >> + >> +struct xrt_event_arg_subdev { >> + enum xrt_subdev_id xevt_subdev_id; >> + int xevt_subdev_instance; >> +}; >> + >> +struct xrt_event { >> + enum xrt_events xe_evt; >> + struct xrt_event_arg_subdev xe_subdev; >> +}; >> + >> +#endif /* _XRT_EVENTS_H_ */ >> diff --git a/drivers/fpga/xrt/include/subdev_id.h b/drivers/fpga/xrt/include/subdev_id.h >> new file mode 100644 >> index 000000000000..6205a9f26196 >> --- /dev/null >> +++ b/drivers/fpga/xrt/include/subdev_id.h >> @@ -0,0 +1,43 @@ >> +/* SPDX-License-Identifier: GPL-2.0 */ >> +/* >> + * Header file for Xilinx Runtime (XRT) driver >> + * >> + * Copyright (C) 2020-2021 Xilinx, Inc. >> + * >> + * Authors: >> + * Cheng Zhen<maxz@xilinx.com> >> + */ >> + >> +#ifndef _XRT_SUBDEV_ID_H_ >> +#define _XRT_SUBDEV_ID_H_ >> + >> +/* >> + * Every subdev driver should have an ID for others to refer to it. > driver has an ID Sure. >> + * There can be unlimited number of instances of a subdev driver. A > unlimited? change to 'multiple' Sure. >> + * <subdev_id, subdev_instance> tuple should be a unique identification of > tuple is a unique Sure. >> + * a specific instance of a subdev driver. >> + * NOTE: PLEASE do not change the order of IDs. Sub devices in the same >> + * group are initialized by this order. > why does the order matter? the enums are all initialized Right. Will remove this statement. >> + */ >> +enum xrt_subdev_id { >> + XRT_SUBDEV_GRP = 0, >> + XRT_SUBDEV_VSEC = 1, >> + XRT_SUBDEV_VSEC_GOLDEN = 2, >> + XRT_SUBDEV_DEVCTL = 3, >> + XRT_SUBDEV_AXIGATE = 4, >> + XRT_SUBDEV_ICAP = 5, >> + XRT_SUBDEV_TEST = 6, >> + XRT_SUBDEV_MGMT_MAIN = 7, >> + XRT_SUBDEV_QSPI = 8, >> + XRT_SUBDEV_MAILBOX = 9, >> + XRT_SUBDEV_CMC = 10, >> + XRT_SUBDEV_CALIB = 11, >> + XRT_SUBDEV_CLKFREQ = 12, >> + XRT_SUBDEV_CLOCK = 13, >> + XRT_SUBDEV_SRSR = 14, >> + XRT_SUBDEV_UCS = 15, >> + XRT_SUBDEV_NUM = 16, /* Total number of subdevs. */ >> + XRT_ROOT = -1, /* Special ID for root driver. */ >> +}; >> + >> +#endif /* _XRT_SUBDEV_ID_H_ */ >> diff --git a/drivers/fpga/xrt/include/xleaf.h b/drivers/fpga/xrt/include/xleaf.h >> new file mode 100644 >> index 000000000000..10215a75d474 >> --- /dev/null >> +++ b/drivers/fpga/xrt/include/xleaf.h >> @@ -0,0 +1,276 @@ >> +/* SPDX-License-Identifier: GPL-2.0 */ >> +/* >> + * Header file for Xilinx Runtime (XRT) driver >> + * >> + * Copyright (C) 2020-2021 Xilinx, Inc. >> + * >> + * Authors: >> + * Cheng Zhen<maxz@xilinx.com> >> + * Sonal Santan<sonal.santan@xilinx.com> >> + */ >> + >> +#ifndef _XRT_XLEAF_H_ >> +#define _XRT_XLEAF_H_ >> + >> +#include <linux/mod_devicetable.h> > not needed Removed. >> +#include <linux/platform_device.h> >> +#include <linux/fs.h> >> +#include <linux/cdev.h> >> +#include <linux/pci.h> > not needed > > check if includes are actually needed. Removed these headers. They are not needed. The rest are needed. >> +#include <linux/libfdt_env.h> >> +#include "libfdt.h" >> +#include "subdev_id.h" >> +#include "xroot.h" >> +#include "events.h" >> + >> +/* All subdev drivers should use below common routines to print out msg. */ >> +#define DEV(pdev) (&(pdev)->dev) >> +#define DEV_PDATA(pdev) \ >> + ((struct xrt_subdev_platdata *)dev_get_platdata(DEV(pdev))) >> +#define DEV_DRVDATA(pdev) \ >> + ((struct xrt_subdev_drvdata *) \ >> + platform_get_device_id(pdev)->driver_data) >> +#define FMT_PRT(prt_fn, pdev, fmt, args...) \ >> + ({typeof(pdev) (_pdev) = (pdev); \ >> + prt_fn(DEV(_pdev), "%s %s: " fmt, \ >> + DEV_PDATA(_pdev)->xsp_root_name, __func__, ##args); }) >> +#define xrt_err(pdev, fmt, args...) FMT_PRT(dev_err, pdev, fmt, ##args) >> +#define xrt_warn(pdev, fmt, args...) FMT_PRT(dev_warn, pdev, fmt, ##args) >> +#define xrt_info(pdev, fmt, args...) FMT_PRT(dev_info, pdev, fmt, ##args) >> +#define xrt_dbg(pdev, fmt, args...) FMT_PRT(dev_dbg, pdev, fmt, ##args) >> + >> +/* Starting IOCTL for common IOCTLs implemented by all leaves. */ >> +#define XRT_XLEAF_COMMON_BASE 0 >> +/* Starting IOCTL for leaves' specific IOCTLs. */ >> +#define XRT_XLEAF_CUSTOM_BASE 64 >> +enum xrt_xleaf_common_ioctl_cmd { >> + XRT_XLEAF_EVENT = XRT_XLEAF_COMMON_BASE, >> +}; >> + >> +/* >> + * If populated by subdev driver, infra will handle the mechanics of >> + * char device (un)registration. >> + */ >> +enum xrt_subdev_file_mode { >> + /* Infra create cdev, default file name */ >> + XRT_SUBDEV_FILE_DEFAULT = 0, >> + /* Infra create cdev, need to encode inst num in file name */ >> + XRT_SUBDEV_FILE_MULTI_INST, >> + /* No auto creation of cdev by infra, leaf handles it by itself */ >> + XRT_SUBDEV_FILE_NO_AUTO, >> +}; >> + >> +struct xrt_subdev_file_ops { >> + const struct file_operations xsf_ops; >> + dev_t xsf_dev_t; >> + const char *xsf_dev_name; >> + enum xrt_subdev_file_mode xsf_mode; >> +}; >> + >> +/* >> + * Subdev driver callbacks populated by subdev driver. >> + */ >> +struct xrt_subdev_drv_ops { >> + /* >> + * Per driver instance callback. The pdev points to the instance. >> + * If defined these are called by other leaf drivers. > If defined, Sure. >> + * Note that root driver may call into xsd_ioctl of a group driver. >> + */ >> + int (*xsd_ioctl)(struct platform_device *pdev, u32 cmd, void *arg); >> +}; >> + >> +/* >> + * Defined and populated by subdev driver, exported as driver_data in >> + * struct platform_device_id. >> + */ >> +struct xrt_subdev_drvdata { >> + struct xrt_subdev_file_ops xsd_file_ops; >> + struct xrt_subdev_drv_ops xsd_dev_ops; >> +}; >> + >> +/* >> + * Partially initialized by the parent driver, then, passed in as subdev driver's >> + * platform data when creating subdev driver instance by calling platform >> + * device register API (platform_device_register_data() or the likes). >> + * >> + * Once device register API returns, platform driver framework makes a copy of >> + * this buffer and maintains its life cycle. The content of the buffer is >> + * completely owned by subdev driver. >> + * >> + * Thus, parent driver should be very careful when it touches this buffer >> + * again once it's handed over to subdev driver. And the data structure >> + * should not contain pointers pointing to buffers that is managed by >> + * other or parent drivers since it could have been freed before platform >> + * data buffer is freed by platform driver framework. > This sounds complicated and risky, why have two copies ? There is only one copy. The buffer used for registering the platform device will be freed by parent. >> + */ >> +struct xrt_subdev_platdata { >> + /* >> + * Per driver instance callback. The pdev points to the instance. >> + * Should always be defined for subdev driver to get service from root. >> + */ >> + xrt_subdev_root_cb_t xsp_root_cb; >> + void *xsp_root_cb_arg; >> + >> + /* Something to associate w/ root for msg printing. */ >> + const char *xsp_root_name; >> + >> + /* >> + * Char dev support for this subdev instance. >> + * Initialized by subdev driver. >> + */ >> + struct cdev xsp_cdev; >> + struct device *xsp_sysdev; >> + struct mutex xsp_devnode_lock; /* devnode lock */ >> + struct completion xsp_devnode_comp; >> + int xsp_devnode_ref; >> + bool xsp_devnode_online; >> + bool xsp_devnode_excl; >> + >> + /* >> + * Subdev driver specific init data. The buffer should be embedded >> + * in this data structure buffer after dtb, so that it can be freed >> + * together with platform data. >> + */ >> + loff_t xsp_priv_off; /* Offset into this platform data buffer. */ >> + size_t xsp_priv_len; >> + >> + /* >> + * Populated by parent driver to describe the device tree for >> + * the subdev driver to handle. Should always be last one since it's >> + * of variable length. >> + */ >> + char xsp_dtb[sizeof(struct fdt_header)]; > could be xsp_dtb[1] and save including the fdt headers just to get a size that doesn't matter. Sure. Will change the code and remove the included headers. >> +}; >> + >> +/* >> + * this struct define the endpoints belong to the same subdevice >> + */ >> +struct xrt_subdev_ep_names { >> + const char *ep_name; >> + const char *regmap_name; >> +}; >> + >> +struct xrt_subdev_endpoints { >> + struct xrt_subdev_ep_names *xse_names; >> + /* minimum number of endpoints to support the subdevice */ >> + u32 xse_min_ep; > see earlier comment about needed a null entry and checking for it. > > a 'size' element would be better here. See my reply to your earlier comment. Can't change here. >> +}; >> + >> +struct subdev_match_arg { >> + enum xrt_subdev_id id; >> + int instance; >> +}; >> + >> +bool xleaf_has_endpoint(struct platform_device *pdev, const char *endpoint_name); >> +struct platform_device *xleaf_get_leaf(struct platform_device *pdev, >> + xrt_subdev_match_t cb, void *arg); >> + >> +static inline bool subdev_match(enum xrt_subdev_id id, struct platform_device *pdev, void *arg) >> +{ >> + const struct subdev_match_arg *a = (struct subdev_match_arg *)arg; >> + bool ret = (id == a->id && (pdev->id == a->instance || PLATFORM_DEVID_NONE == a->instance)); > This statement is too complicated, turn this into an if-else Sure. >> + >> + return ret; >> +} >> + >> +static inline bool xrt_subdev_match_epname(enum xrt_subdev_id id, >> + struct platform_device *pdev, void *arg) >> +{ >> + return xleaf_has_endpoint(pdev, arg); > This function is used only once. > > Just inline the function to the caller and remove this function. This function is used by being passed as a function pointer to another function. I can't inline it. >> +} >> + >> +static inline struct platform_device * >> +xleaf_get_leaf_by_id(struct platform_device *pdev, >> + enum xrt_subdev_id id, int instance) >> +{ >> + struct subdev_match_arg arg = { id, instance }; >> + >> + return xleaf_get_leaf(pdev, subdev_match, &arg); >> +} >> + >> +static inline struct platform_device * >> +xleaf_get_leaf_by_epname(struct platform_device *pdev, const char *name) >> +{ >> + return xleaf_get_leaf(pdev, xrt_subdev_match_epname, (void *)name); >> +} >> + >> +static inline int xleaf_ioctl(struct platform_device *tgt, u32 cmd, void *arg) >> +{ >> + struct xrt_subdev_drvdata *drvdata = DEV_DRVDATA(tgt); >> + >> + return (*drvdata->xsd_dev_ops.xsd_ioctl)(tgt, cmd, arg); >> +} >> + >> +int xleaf_put_leaf(struct platform_device *pdev, >> + struct platform_device *leaf); >> +int xleaf_create_group(struct platform_device *pdev, char *dtb); >> +int xleaf_destroy_group(struct platform_device *pdev, int instance); >> +int xleaf_wait_for_group_bringup(struct platform_device *pdev); >> +void xleaf_hot_reset(struct platform_device *pdev); >> +int xleaf_broadcast_event(struct platform_device *pdev, >> + enum xrt_events evt, bool async); >> +void xleaf_get_barres(struct platform_device *pdev, >> + struct resource **res, uint bar_idx); >> +void xleaf_get_root_id(struct platform_device *pdev, >> + unsigned short *vendor, unsigned short *device, >> + unsigned short *subvendor, unsigned short *subdevice); >> +struct device *xleaf_register_hwmon(struct platform_device *pdev, >> + const char *name, void *drvdata, >> + const struct attribute_group **grps); >> +void xleaf_unregister_hwmon(struct platform_device *pdev, struct device *hwmon); > could better organize these decl's alphabetically. Sure. > Also not intermix inlines and decls. These decls are used in inlines, so can't reorder. >> + >> +/* >> + * Character device helper APIs for use by leaf drivers >> + */ >> +static inline bool xleaf_devnode_enabled(struct xrt_subdev_drvdata *drvdata) >> +{ >> + return drvdata && drvdata->xsd_file_ops.xsf_ops.open; >> +} >> + >> +int xleaf_devnode_create(struct platform_device *pdev, >> + const char *file_name, const char *inst_name); >> +int xleaf_devnode_destroy(struct platform_device *pdev); >> + >> +struct platform_device *xleaf_devnode_open_excl(struct inode *inode); >> +struct platform_device *xleaf_devnode_open(struct inode *inode); >> +void xleaf_devnode_close(struct inode *inode); >> + >> +/* Helpers. */ >> +static inline void xrt_memcpy_fromio(void *buf, void __iomem *iomem, u32 size) >> +{ > Replace with mmio_insl/outsl No, I can't call mmio_insl/outsl here or even ioread32_rep()/iowrite32_rep(). These function will not increase port address inside the loop. But, the implementation we need is like memcpy() - both src and dst will be increased during the loop. >> + int i; >> + >> + WARN_ON(size & 0x3); >> + for (i = 0; i < size / 4; i++) >> + ((u32 *)buf)[i] = ioread32((char *)(iomem) + sizeof(u32) * i); >> +} >> + >> +static inline void xrt_memcpy_toio(void __iomem *iomem, void *buf, u32 size) >> +{ >> + int i; >> + >> + WARN_ON(size & 0x3); >> + for (i = 0; i < size / 4; i++) >> + iowrite32(((u32 *)buf)[i], ((char *)(iomem) + sizeof(u32) * i)); >> +} >> + >> +int xleaf_register_driver(enum xrt_subdev_id id, struct platform_driver *drv, >> + struct xrt_subdev_endpoints *eps); >> +void xleaf_unregister_driver(enum xrt_subdev_id id); >> + >> +/* Module's init/fini routines for leaf driver in xrt-lib module */ >> +void group_leaf_init_fini(bool init); >> +void vsec_leaf_init_fini(bool init); >> +void vsec_golden_leaf_init_fini(bool init); >> +void devctl_leaf_init_fini(bool init); >> +void axigate_leaf_init_fini(bool init); >> +void icap_leaf_init_fini(bool init); >> +void calib_leaf_init_fini(bool init); >> +void qspi_leaf_init_fini(bool init); >> +void mailbox_leaf_init_fini(bool init); >> +void cmc_leaf_init_fini(bool init); >> +void clkfreq_leaf_init_fini(bool init); >> +void clock_leaf_init_fini(bool init); >> +void ucs_leaf_init_fini(bool init); > Shouldn't these be in the specific leaf drv ? If the leaf drivers are standalone .ko, yes. But these are for leaf drivers inside xrt-lib.ko, so we need them here to be called inside xrt-lib.ko's __init/__fini routine. >> + >> +#endif /* _XRT_LEAF_H_ */ >> diff --git a/drivers/fpga/xrt/lib/cdev.c b/drivers/fpga/xrt/lib/cdev.c >> new file mode 100644 >> index 000000000000..7f104ab3d527 >> --- /dev/null >> +++ b/drivers/fpga/xrt/lib/cdev.c >> @@ -0,0 +1,231 @@ >> +// SPDX-License-Identifier: GPL-2.0 >> +/* >> + * Xilinx Alveo FPGA device node helper functions. >> + * >> + * Copyright (C) 2020-2021 Xilinx, Inc. >> + * >> + * Authors: >> + * Cheng Zhen<maxz@xilinx.com> >> + */ >> + >> +#include "xleaf.h" >> + >> +extern struct class *xrt_class; >> + >> +#define XRT_CDEV_DIR "xfpga" > 'xfpga' is not very unique, maybe 'xrt' ? This is to make sure it's compatible with XRT's user space utilities, which also works with other version of drivers (they all use xfpga). >> +#define INODE2PDATA(inode) \ >> + container_of((inode)->i_cdev, struct xrt_subdev_platdata, xsp_cdev) >> +#define INODE2PDEV(inode) \ >> + to_platform_device(kobj_to_dev((inode)->i_cdev->kobj.parent)) >> +#define CDEV_NAME(sysdev) (strchr((sysdev)->kobj.name, '!') + 1) >> + >> +/* Allow it to be accessed from cdev. */ >> +static void xleaf_devnode_allowed(struct platform_device *pdev) >> +{ >> + struct xrt_subdev_platdata *pdata = DEV_PDATA(pdev); >> + >> + /* Allow new opens. */ >> + mutex_lock(&pdata->xsp_devnode_lock); >> + pdata->xsp_devnode_online = true; >> + mutex_unlock(&pdata->xsp_devnode_lock); >> +} >> + >> +/* Turn off access from cdev and wait for all existing user to go away. */ >> +static int xleaf_devnode_disallowed(struct platform_device *pdev) >> +{ >> + int ret = 0; >> + struct xrt_subdev_platdata *pdata = DEV_PDATA(pdev); >> + >> + mutex_lock(&pdata->xsp_devnode_lock); >> + >> + /* Prevent new opens. */ >> + pdata->xsp_devnode_online = false; >> + /* Wait for existing user to close. */ >> + while (!ret && pdata->xsp_devnode_ref) { >> + int rc; >> + >> + mutex_unlock(&pdata->xsp_devnode_lock); >> + rc = wait_for_completion_killable(&pdata->xsp_devnode_comp); >> + mutex_lock(&pdata->xsp_devnode_lock); >> + >> + if (rc == -ERESTARTSYS) { >> + /* Restore online state. */ >> + pdata->xsp_devnode_online = true; >> + xrt_err(pdev, "%s is in use, ref=%d", >> + CDEV_NAME(pdata->xsp_sysdev), >> + pdata->xsp_devnode_ref); >> + ret = -EBUSY; >> + } >> + } >> + >> + mutex_unlock(&pdata->xsp_devnode_lock); >> + >> + return ret; >> +} >> + >> +static struct platform_device * >> +__xleaf_devnode_open(struct inode *inode, bool excl) >> +{ >> + struct xrt_subdev_platdata *pdata = INODE2PDATA(inode); >> + struct platform_device *pdev = INODE2PDEV(inode); >> + bool opened = false; >> + >> + mutex_lock(&pdata->xsp_devnode_lock); >> + >> + if (pdata->xsp_devnode_online) { >> + if (excl && pdata->xsp_devnode_ref) { >> + xrt_err(pdev, "%s has already been opened exclusively", >> + CDEV_NAME(pdata->xsp_sysdev)); >> + } else if (!excl && pdata->xsp_devnode_excl) { >> + xrt_err(pdev, "%s has been opened exclusively", >> + CDEV_NAME(pdata->xsp_sysdev)); >> + } else { >> + pdata->xsp_devnode_ref++; >> + pdata->xsp_devnode_excl = excl; >> + opened = true; >> + xrt_info(pdev, "opened %s, ref=%d", >> + CDEV_NAME(pdata->xsp_sysdev), >> + pdata->xsp_devnode_ref); >> + } >> + } else { >> + xrt_err(pdev, "%s is offline", CDEV_NAME(pdata->xsp_sysdev)); >> + } >> + >> + mutex_unlock(&pdata->xsp_devnode_lock); >> + >> + pdev = opened ? pdev : NULL; >> + return pdev; >> +} >> + >> +struct platform_device * >> +xleaf_devnode_open_excl(struct inode *inode) >> +{ >> + return __xleaf_devnode_open(inode, true); >> +} >> + >> +struct platform_device * >> +xleaf_devnode_open(struct inode *inode) >> +{ >> + return __xleaf_devnode_open(inode, false); >> +} >> +EXPORT_SYMBOL_GPL(xleaf_devnode_open); > generally > > exported systems should have their decl's in include/linux/fpga/ > > These are in drivers/fpga/xrt/include/xleaf.h But, our exported symbols are only meant to be used inside our drivers (between two KOs: xmgmt.ko and xrt-lib.ko). They should not be included and used by other parts of Linux. > as exported, they should have a better than average prefix. > > maybe 'xrt_fpga_' Since they are really private symbols (exported only because we have two KOs), I prefer the existing pre-fix so that it is consistent with other functions in our driver. They should not be used by other codes than our own driver. >> + >> +void xleaf_devnode_close(struct inode *inode) >> +{ >> + struct xrt_subdev_platdata *pdata = INODE2PDATA(inode); >> + struct platform_device *pdev = INODE2PDEV(inode); >> + bool notify = false; >> + >> + mutex_lock(&pdata->xsp_devnode_lock); >> + >> + pdata->xsp_devnode_ref--; > check before dec ? or at least warn if ref is already 0 Will add a warning here. >> + if (pdata->xsp_devnode_ref == 0) { >> + pdata->xsp_devnode_excl = false; >> + notify = true; >> + } >> + if (notify) { >> + xrt_info(pdev, "closed %s, ref=%d", >> + CDEV_NAME(pdata->xsp_sysdev), pdata->xsp_devnode_ref); >> + } else { >> + xrt_info(pdev, "closed %s, notifying waiter", >> + CDEV_NAME(pdata->xsp_sysdev)); >> + } >> + >> + mutex_unlock(&pdata->xsp_devnode_lock); >> + >> + if (notify) >> + complete(&pdata->xsp_devnode_comp); >> +} >> +EXPORT_SYMBOL_GPL(xleaf_devnode_close); >> + >> +static inline enum xrt_subdev_file_mode >> +devnode_mode(struct xrt_subdev_drvdata *drvdata) >> +{ >> + return drvdata->xsd_file_ops.xsf_mode; >> +} >> + >> +int xleaf_devnode_create(struct platform_device *pdev, const char *file_name, >> + const char *inst_name) >> +{ >> + struct xrt_subdev_drvdata *drvdata = DEV_DRVDATA(pdev); >> + struct xrt_subdev_file_ops *fops = &drvdata->xsd_file_ops; >> + struct xrt_subdev_platdata *pdata = DEV_PDATA(pdev); >> + struct cdev *cdevp; >> + struct device *sysdev; >> + int ret = 0; >> + char fname[256]; > will a /dev/xfpga* created for ever leaf device ? > > do they all really need /dev/ support ? No, most of them do not need one. The device node is only created for some of them. >> + >> + mutex_init(&pdata->xsp_devnode_lock); >> + init_completion(&pdata->xsp_devnode_comp); >> + >> + cdevp = &DEV_PDATA(pdev)->xsp_cdev; > no cdev_alloc ? We did a cdev_init() here as below. Does it not work? >> + cdev_init(cdevp, &fops->xsf_ops); >> + cdevp->owner = fops->xsf_ops.owner; >> + cdevp->dev = MKDEV(MAJOR(fops->xsf_dev_t), pdev->id); >> + >> + /* >> + * Set pdev as parent of cdev so that when pdev (and its platform >> + * data) will not be freed when cdev is not freed. >> + */ >> + cdev_set_parent(cdevp, &DEV(pdev)->kobj); >> + >> + ret = cdev_add(cdevp, cdevp->dev, 1); >> + if (ret) { >> + xrt_err(pdev, "failed to add cdev: %d", ret); >> + goto failed; >> + } >> + if (!file_name) >> + file_name = pdev->name; >> + if (!inst_name) { >> + if (devnode_mode(drvdata) == XRT_SUBDEV_FILE_MULTI_INST) { >> + snprintf(fname, sizeof(fname), "%s/%s/%s.%u", >> + XRT_CDEV_DIR, DEV_PDATA(pdev)->xsp_root_name, >> + file_name, pdev->id); >> + } else { >> + snprintf(fname, sizeof(fname), "%s/%s/%s", >> + XRT_CDEV_DIR, DEV_PDATA(pdev)->xsp_root_name, >> + file_name); >> + } >> + } else { >> + snprintf(fname, sizeof(fname), "%s/%s/%s.%s", XRT_CDEV_DIR, >> + DEV_PDATA(pdev)->xsp_root_name, file_name, inst_name); >> + } >> + sysdev = device_create(xrt_class, NULL, cdevp->dev, NULL, "%s", fname); >> + if (IS_ERR(sysdev)) { >> + ret = PTR_ERR(sysdev); >> + xrt_err(pdev, "failed to create device node: %d", ret); >> + goto failed; > this calls device_destroy, but the create call failed, so is this needed ? Will fix. >> + } >> + pdata->xsp_sysdev = sysdev; >> + >> + xleaf_devnode_allowed(pdev); >> + >> + xrt_info(pdev, "created (%d, %d): /dev/%s", >> + MAJOR(cdevp->dev), pdev->id, fname); >> + return 0; >> + >> +failed: >> + device_destroy(xrt_class, cdevp->dev); >> + cdev_del(cdevp); >> + cdevp->owner = NULL; >> + return ret; >> +} >> + >> +int xleaf_devnode_destroy(struct platform_device *pdev) >> +{ >> + struct xrt_subdev_platdata *pdata = DEV_PDATA(pdev); >> + struct cdev *cdevp = &pdata->xsp_cdev; >> + dev_t dev = cdevp->dev; >> + int rc; >> + >> + rc = xleaf_devnode_disallowed(pdev); >> + if (rc) >> + return rc; > This return is not checked by xrt_subdev_destroy I will add a check and warning in xrt_subdev_destroy(). >> + >> + xrt_info(pdev, "removed (%d, %d): /dev/%s/%s", MAJOR(dev), MINOR(dev), >> + XRT_CDEV_DIR, CDEV_NAME(pdata->xsp_sysdev)); >> + device_destroy(xrt_class, cdevp->dev); >> + pdata->xsp_sysdev = NULL; >> + cdev_del(cdevp); >> + return 0; >> +} >> diff --git a/drivers/fpga/xrt/lib/subdev.c b/drivers/fpga/xrt/lib/subdev.c >> new file mode 100644 >> index 000000000000..73552c549bdb >> --- /dev/null >> +++ b/drivers/fpga/xrt/lib/subdev.c >> @@ -0,0 +1,871 @@ >> +// SPDX-License-Identifier: GPL-2.0 >> +/* >> + * Xilinx Alveo FPGA device helper functions >> + * >> + * Copyright (C) 2020-2021 Xilinx, Inc. >> + * >> + * Authors: >> + * Cheng Zhen<maxz@xilinx.com> >> + */ >> + >> +#include <linux/platform_device.h> >> +#include <linux/pci.h> >> +#include <linux/vmalloc.h> >> +#include "xleaf.h" >> +#include "subdev_pool.h" >> +#include "main.h" >> +#include "metadata.h" >> + >> +#define DEV_IS_PCI(dev) ((dev)->bus == &pci_bus_type) >> +static inline struct device *find_root(struct platform_device *pdev) >> +{ >> + struct device *d = DEV(pdev); >> + >> + while (!DEV_IS_PCI(d)) >> + d = d->parent; > Shouldn't the root have no parent ? > > Could then check if d->parent == NULL instead of bus type The root is a PCIE device driver whose struct device is managed by PCIE driver framework. I don't think I can assume d->parent is NULL, right? >> + return d; >> +} >> + >> +/* >> + * It represents a holder of a subdev. One holder can repeatedly hold a subdev >> + * as long as there is a unhold corresponding to a hold. >> + */ >> +struct xrt_subdev_holder { >> + struct list_head xsh_holder_list; >> + struct device *xsh_holder; >> + int xsh_count; >> + struct kref xsh_kref; > general, i see this in struct xrt_subdev > > guessing 'xsh' is xrt subdev holder. > > why is this prefix needed for the elements ? consider removing it. It's good to have unique element name so that it's easier to grep the reference in the code. I'd like to keep them. >> +}; >> + >> +/* >> + * It represents a specific instance of platform driver for a subdev, which >> + * provides services to its clients (another subdev driver or root driver). >> + */ >> +struct xrt_subdev { >> + struct list_head xs_dev_list; >> + struct list_head xs_holder_list; >> + enum xrt_subdev_id xs_id; /* type of subdev */ >> + struct platform_device *xs_pdev; /* a particular subdev inst */ >> + struct completion xs_holder_comp; >> +}; >> + >> +static struct xrt_subdev *xrt_subdev_alloc(void) >> +{ >> + struct xrt_subdev *sdev = vzalloc(sizeof(*sdev)); > similar kzalloc as another patch. Sure. >> + >> + if (!sdev) >> + return NULL; >> + >> + INIT_LIST_HEAD(&sdev->xs_dev_list); >> + INIT_LIST_HEAD(&sdev->xs_holder_list); >> + init_completion(&sdev->xs_holder_comp); >> + return sdev; >> +} >> + >> +static void xrt_subdev_free(struct xrt_subdev *sdev) >> +{ >> + vfree(sdev); >> +} >> + >> +int xrt_subdev_root_request(struct platform_device *self, u32 cmd, void *arg) >> +{ >> + struct device *dev = DEV(self); >> + struct xrt_subdev_platdata *pdata = DEV_PDATA(self); >> + >> + return (*pdata->xsp_root_cb)(dev->parent, pdata->xsp_root_cb_arg, cmd, arg); > xrt_subdev_create does not check if pcb is valid. is a null is passed in, it will crash. > > there should at least be a warn or -INVALID returned there This should not happen. I will add a warning here. >> +} >> + >> +/* >> + * Subdev common sysfs nodes. >> + */ >> +static ssize_t holders_show(struct device *dev, struct device_attribute *attr, char *buf) >> +{ >> + ssize_t len; >> + struct platform_device *pdev = to_platform_device(dev); >> + struct xrt_root_ioctl_get_holders holders = { pdev, buf, 1024 }; > is 1024 a guess ? Yes, something big enough. >> + >> + len = xrt_subdev_root_request(pdev, XRT_ROOT_GET_LEAF_HOLDERS, &holders); > take a closer look at xrt_subdev_get_holders() it stops after it goes past len. Yes, this is for debug only, so it's OK to truncate the holder list here. >> + if (len >= holders.xpigh_holder_buf_len) >> + return len; >> + buf[len] = '\n'; >> + return len + 1; >> +} >> +static DEVICE_ATTR_RO(holders); >> + >> +static struct attribute *xrt_subdev_attrs[] = { >> + &dev_attr_holders.attr, >> + NULL, >> +}; >> + >> +static ssize_t metadata_output(struct file *filp, struct kobject *kobj, >> + struct bin_attribute *attr, char *buf, loff_t off, size_t count) >> +{ >> + struct device *dev = kobj_to_dev(kobj); >> + struct platform_device *pdev = to_platform_device(dev); >> + struct xrt_subdev_platdata *pdata = DEV_PDATA(pdev); >> + unsigned char *blob; >> + unsigned long size; >> + ssize_t ret = 0; >> + >> + blob = pdata->xsp_dtb; >> + size = xrt_md_size(dev, blob); >> + if (size == XRT_MD_INVALID_LENGTH) { >> + ret = -EINVAL; >> + goto failed; >> + } >> + >> + if (off >= size) >> + goto failed; > silently failed because ret = 0 ? It's fine. This is just for debugging. >> + >> + if (off + count > size) >> + count = size - off; > truncating is ok ? Yes, this is just for debugging. >> + memcpy(buf, blob + off, count); >> + >> + ret = count; >> +failed: >> + return ret; >> +} >> + >> +static struct bin_attribute meta_data_attr = { >> + .attr = { >> + .name = "metadata", >> + .mode = 0400 >> + }, >> + .read = metadata_output, >> + .size = 0 >> +}; >> + >> +static struct bin_attribute *xrt_subdev_bin_attrs[] = { >> + &meta_data_attr, > is giving the average user access to the meta data a good idea ? > > this seems like a developer only need. Yes, this is for developer only. We do not want to give normal user access to it. Hence we set .mode to 0400. >> + NULL, >> +}; >> + >> +static const struct attribute_group xrt_subdev_attrgroup = { >> + .attrs = xrt_subdev_attrs, >> + .bin_attrs = xrt_subdev_bin_attrs, >> +}; >> + >> +/* >> + * Given the device metadata, parse it to get IO ranges and construct >> + * resource array. >> + */ >> +static int >> +xrt_subdev_getres(struct device *parent, enum xrt_subdev_id id, >> + char *dtb, struct resource **res, int *res_num) >> +{ >> + struct xrt_subdev_platdata *pdata; >> + struct resource *pci_res = NULL; >> + const u64 *bar_range; >> + const u32 *bar_idx; >> + char *ep_name = NULL, *regmap = NULL; >> + uint bar; >> + int count1 = 0, count2 = 0, ret; >> + >> + if (!dtb) >> + return -EINVAL; >> + >> + pdata = DEV_PDATA(to_platform_device(parent)); >> + >> + /* go through metadata and count endpoints in it */ >> + for (xrt_md_get_next_endpoint(parent, dtb, NULL, NULL, &ep_name, ®map); ep_name; > Ugly. > > Can you preprocess the dtb into a list of end points ? Not sure I follow? But you still need to iterate the list even if you preprocess it, right? Not sure which part is ugly? >> + xrt_md_get_next_endpoint(parent, dtb, ep_name, regmap, &ep_name, ®map)) { >> + ret = xrt_md_get_prop(parent, dtb, ep_name, regmap, >> + XRT_MD_PROP_IO_OFFSET, (const void **)&bar_range, NULL); >> + if (!ret) >> + count1++; >> + } >> + if (!count1) >> + return 0; >> + >> + /* allocate resource array for all endpoints been found in metadata */ >> + *res = vzalloc(sizeof(**res) * count1); >> + >> + /* go through all endpoints again and get IO range for each endpoint */ >> + for (xrt_md_get_next_endpoint(parent, dtb, NULL, NULL, &ep_name, ®map); ep_name; >> + xrt_md_get_next_endpoint(parent, dtb, ep_name, regmap, &ep_name, ®map)) { >> + ret = xrt_md_get_prop(parent, dtb, ep_name, regmap, >> + XRT_MD_PROP_IO_OFFSET, (const void **)&bar_range, NULL); >> + if (ret) >> + continue; >> + xrt_md_get_prop(parent, dtb, ep_name, regmap, >> + XRT_MD_PROP_BAR_IDX, (const void **)&bar_idx, NULL); > bar can fail, but bar idx can not. > > should add an assert here When there is no bar idx, we use default value 0. So, bar idx can also fail. >> + bar = bar_idx ? be32_to_cpu(*bar_idx) : 0; >> + xleaf_get_barres(to_platform_device(parent), &pci_res, bar); >> + (*res)[count2].start = pci_res->start + >> + be64_to_cpu(bar_range[0]); >> + (*res)[count2].end = pci_res->start + >> + be64_to_cpu(bar_range[0]) + >> + be64_to_cpu(bar_range[1]) - 1; >> + (*res)[count2].flags = IORESOURCE_MEM; > any irqs need handling? Currently, we do not have irqs to handle. >> + /* check if there is conflicted resource */ >> + ret = request_resource(pci_res, *res + count2); >> + if (ret) { >> + dev_err(parent, "Conflict resource %pR\n", *res + count2); >> + vfree(*res); >> + *res_num = 0; >> + *res = NULL; >> + return ret; >> + } >> + release_resource(*res + count2); >> + >> + (*res)[count2].parent = pci_res; >> + >> + xrt_md_find_endpoint(parent, pdata->xsp_dtb, ep_name, >> + regmap, &(*res)[count2].name); >> + >> + count2++; >> + } >> + >> + WARN_ON(count1 != count2); >> + *res_num = count2; >> + >> + return 0; >> +} >> + >> +static inline enum xrt_subdev_file_mode >> +xleaf_devnode_mode(struct xrt_subdev_drvdata *drvdata) >> +{ >> + return drvdata->xsd_file_ops.xsf_mode; >> +} >> + >> +static bool xrt_subdev_cdev_auto_creation(struct platform_device *pdev) >> +{ >> + struct xrt_subdev_drvdata *drvdata = DEV_DRVDATA(pdev); >> + >> + if (!drvdata) >> + return false; >> + >> + return xleaf_devnode_enabled(drvdata) && >> + (xleaf_devnode_mode(drvdata) == XRT_SUBDEV_FILE_DEFAULT || >> + (xleaf_devnode_mode(drvdata) == XRT_SUBDEV_FILE_MULTI_INST)); > This is complicated to check, split into checking the call and then checking its side effects. Sure. >> +} >> + >> +static struct xrt_subdev * >> +xrt_subdev_create(struct device *parent, enum xrt_subdev_id id, >> + xrt_subdev_root_cb_t pcb, void *pcb_arg, char *dtb) >> +{ >> + struct xrt_subdev *sdev = NULL; >> + struct platform_device *pdev = NULL; >> + struct xrt_subdev_platdata *pdata = NULL; >> + unsigned long dtb_len = 0; >> + size_t pdata_sz; >> + int inst = PLATFORM_DEVID_NONE; >> + struct resource *res = NULL; >> + int res_num = 0; >> + >> + sdev = xrt_subdev_alloc(); >> + if (!sdev) { >> + dev_err(parent, "failed to alloc subdev for ID %d", id); >> + goto fail; >> + } >> + sdev->xs_id = id; >> + >> + if (dtb) { >> + xrt_md_pack(parent, dtb); >> + dtb_len = xrt_md_size(parent, dtb); >> + if (dtb_len == XRT_MD_INVALID_LENGTH) { >> + dev_err(parent, "invalid metadata len %ld", dtb_len); >> + goto fail; >> + } >> + } >> + pdata_sz = sizeof(struct xrt_subdev_platdata) + dtb_len - 1; > -1 ? > > if dtb_len == 0, pdata_sz be too small. Will fix. >> + >> + /* Prepare platform data passed to subdev. */ >> + pdata = vzalloc(pdata_sz); >> + if (!pdata) >> + goto fail; >> + >> + pdata->xsp_root_cb = pcb; >> + pdata->xsp_root_cb_arg = pcb_arg; >> + memcpy(pdata->xsp_dtb, dtb, dtb_len); >> + if (id == XRT_SUBDEV_GRP) { >> + /* Group can only be created by root driver. */ >> + pdata->xsp_root_name = dev_name(parent); >> + } else { >> + struct platform_device *grp = to_platform_device(parent); >> + /* Leaf can only be created by group driver. */ >> + WARN_ON(strcmp(xrt_drv_name(XRT_SUBDEV_GRP), platform_get_device_id(grp)->name)); >> + pdata->xsp_root_name = DEV_PDATA(grp)->xsp_root_name; >> + } >> + >> + /* Obtain dev instance number. */ >> + inst = xrt_drv_get_instance(id); >> + if (inst < 0) { >> + dev_err(parent, "failed to obtain instance: %d", inst); >> + goto fail; >> + } >> + >> + /* Create subdev. */ >> + if (id == XRT_SUBDEV_GRP) { >> + pdev = platform_device_register_data(parent, xrt_drv_name(XRT_SUBDEV_GRP), >> + inst, pdata, pdata_sz); >> + } else { >> + int rc = xrt_subdev_getres(parent, id, dtb, &res, &res_num); >> + >> + if (rc) { >> + dev_err(parent, "failed to get resource for %s.%d: %d", >> + xrt_drv_name(id), inst, rc); >> + goto fail; >> + } >> + pdev = platform_device_register_resndata(parent, xrt_drv_name(id), >> + inst, res, res_num, pdata, pdata_sz); >> + vfree(res); >> + } > a small optimization > > platform_device_register_data is a wrapper to platform_device_register_resndata. > > with initial values for res, res_num, just one call need to be made. Sure. >> + if (IS_ERR(pdev)) { >> + dev_err(parent, "failed to create subdev for %s inst %d: %ld", >> + xrt_drv_name(id), inst, PTR_ERR(pdev)); >> + goto fail; >> + } >> + sdev->xs_pdev = pdev; >> + >> + if (device_attach(DEV(pdev)) != 1) { >> + xrt_err(pdev, "failed to attach"); >> + goto fail; >> + } >> + >> + if (sysfs_create_group(&DEV(pdev)->kobj, &xrt_subdev_attrgroup)) >> + xrt_err(pdev, "failed to create sysfs group"); > no failure ? Not treated as fatal, so just issue a error message. >> + >> + /* >> + * Create sysfs sym link under root for leaves >> + * under random groups for easy access to them. >> + */ >> + if (id != XRT_SUBDEV_GRP) { >> + if (sysfs_create_link(&find_root(pdev)->kobj, >> + &DEV(pdev)->kobj, dev_name(DEV(pdev)))) { >> + xrt_err(pdev, "failed to create sysfs link"); >> + } >> + } >> + >> + /* All done, ready to handle req thru cdev. */ >> + if (xrt_subdev_cdev_auto_creation(pdev)) >> + xleaf_devnode_create(pdev, DEV_DRVDATA(pdev)->xsd_file_ops.xsf_dev_name, NULL); >> + >> + vfree(pdata); >> + return sdev; >> + >> +fail: > Instead of adding checks in the error handling block, add more specific labels and gotos. > > I think i have noticed this before, so apply this advice generally. It seems that it's easier to do the check than adding a whole bunch of labels, so that you can just jump to the same label for error handling without worrying about jumping to the wrong label? And it is also possible that some of the error handling may have been done in the middle of the function, so you don't need to redo it in the end. But adding labels only works for incremental error handlings. >> + vfree(pdata); >> + if (sdev && !IS_ERR_OR_NULL(sdev->xs_pdev)) >> + platform_device_unregister(sdev->xs_pdev); >> + if (inst >= 0) >> + xrt_drv_put_instance(id, inst); >> + xrt_subdev_free(sdev); >> + return NULL; >> +} >> + >> +static void xrt_subdev_destroy(struct xrt_subdev *sdev) >> +{ >> + struct platform_device *pdev = sdev->xs_pdev; >> + int inst = pdev->id; >> + struct device *dev = DEV(pdev); >> + >> + /* Take down the device node */ >> + if (xrt_subdev_cdev_auto_creation(pdev)) >> + xleaf_devnode_destroy(pdev); >> + if (sdev->xs_id != XRT_SUBDEV_GRP) >> + sysfs_remove_link(&find_root(pdev)->kobj, dev_name(dev)); >> + sysfs_remove_group(&dev->kobj, &xrt_subdev_attrgroup); >> + platform_device_unregister(pdev); >> + xrt_drv_put_instance(sdev->xs_id, inst); >> + xrt_subdev_free(sdev); >> +} >> + >> +struct platform_device * >> +xleaf_get_leaf(struct platform_device *pdev, xrt_subdev_match_t match_cb, void *match_arg) >> +{ >> + int rc; >> + struct xrt_root_ioctl_get_leaf get_leaf = { >> + pdev, match_cb, match_arg, }; >> + >> + rc = xrt_subdev_root_request(pdev, XRT_ROOT_GET_LEAF, &get_leaf); >> + if (rc) >> + return NULL; >> + return get_leaf.xpigl_leaf; >> +} >> +EXPORT_SYMBOL_GPL(xleaf_get_leaf); >> + >> +bool xleaf_has_endpoint(struct platform_device *pdev, const char *endpoint_name) >> +{ >> + struct resource *res; >> + int i; > whitespace Sure. >> + >> + for (i = 0, res = platform_get_resource(pdev, IORESOURCE_MEM, 0); >> + res; >> + res = platform_get_resource(pdev, IORESOURCE_MEM, ++i)) { > Do not inc i inside the call, do it at the bottom of the loop Sure. >> + if (!strncmp(res->name, endpoint_name, strlen(res->name) + 1)) > shouldn't you also check the strlen matches ? We compare strlen + 1, so the null terminate will be compared, too. >> + return true; >> + } >> + >> + return false; >> +} >> +EXPORT_SYMBOL_GPL(xleaf_has_endpoint); >> + >> +int xleaf_put_leaf(struct platform_device *pdev, struct platform_device *leaf) >> +{ >> + struct xrt_root_ioctl_put_leaf put_leaf = { pdev, leaf }; >> + >> + return xrt_subdev_root_request(pdev, XRT_ROOT_PUT_LEAF, &put_leaf); >> +} >> +EXPORT_SYMBOL_GPL(xleaf_put_leaf); >> + >> +int xleaf_create_group(struct platform_device *pdev, char *dtb) >> +{ >> + return xrt_subdev_root_request(pdev, XRT_ROOT_CREATE_GROUP, dtb); >> +} >> +EXPORT_SYMBOL_GPL(xleaf_create_group); >> + >> +int xleaf_destroy_group(struct platform_device *pdev, int instance) >> +{ >> + return xrt_subdev_root_request(pdev, XRT_ROOT_REMOVE_GROUP, (void *)(uintptr_t)instance); > Instead of these clunky casts, why not make the type of the args void * > > and leave it to the handler to cast. > > this would unify the signature of these functions somewhat. The type of arg for xrt_subdev_root_request() is already void *. But I can't just pass instance as a int to the void *, so have to cast here. >> +} >> +EXPORT_SYMBOL_GPL(xleaf_destroy_group); >> + >> +int xleaf_wait_for_group_bringup(struct platform_device *pdev) >> +{ >> + return xrt_subdev_root_request(pdev, XRT_ROOT_WAIT_GROUP_BRINGUP, NULL); >> +} >> +EXPORT_SYMBOL_GPL(xleaf_wait_for_group_bringup); >> + >> +static ssize_t >> +xrt_subdev_get_holders(struct xrt_subdev *sdev, char *buf, size_t len) >> +{ >> + const struct list_head *ptr; >> + struct xrt_subdev_holder *h; >> + ssize_t n = 0; >> + >> + list_for_each(ptr, &sdev->xs_holder_list) { >> + h = list_entry(ptr, struct xrt_subdev_holder, xsh_holder_list); >> + n += snprintf(buf + n, len - n, "%s:%d ", >> + dev_name(h->xsh_holder), kref_read(&h->xsh_kref)); >> + if (n >= (len - 1)) > This is the overrun i mentioned above. Truncation is fine. >> + break; >> + } >> + return n; >> +} >> + >> +void xrt_subdev_pool_init(struct device *dev, struct xrt_subdev_pool *spool) >> +{ >> + INIT_LIST_HEAD(&spool->xsp_dev_list); >> + spool->xsp_owner = dev; >> + mutex_init(&spool->xsp_lock); >> + spool->xsp_closing = false; >> +} >> + >> +static void xrt_subdev_free_holder(struct xrt_subdev_holder *holder) >> +{ >> + list_del(&holder->xsh_holder_list); >> + vfree(holder); >> +} >> + >> +static void xrt_subdev_pool_wait_for_holders(struct xrt_subdev_pool *spool, struct xrt_subdev *sdev) >> +{ >> + const struct list_head *ptr, *next; >> + char holders[128]; >> + struct xrt_subdev_holder *holder; >> + struct mutex *lk = &spool->xsp_lock; >> + >> + WARN_ON(!mutex_is_locked(lk)); >> + >> + while (!list_empty(&sdev->xs_holder_list)) { >> + int rc; >> + >> + /* It's most likely a bug if we ever enters this loop. */ >> + xrt_subdev_get_holders(sdev, holders, sizeof(holders)); > will overrun, error not reported. It's ok, just for debugging. >> + xrt_err(sdev->xs_pdev, "awaits holders: %s", holders); >> + mutex_unlock(lk); >> + rc = wait_for_completion_killable(&sdev->xs_holder_comp); >> + mutex_lock(lk); >> + if (rc == -ERESTARTSYS) { >> + xrt_err(sdev->xs_pdev, "give up on waiting for holders, clean up now"); >> + list_for_each_safe(ptr, next, &sdev->xs_holder_list) { >> + holder = list_entry(ptr, struct xrt_subdev_holder, xsh_holder_list); >> + xrt_subdev_free_holder(holder); >> + } >> + } >> + } >> +} >> + >> +void xrt_subdev_pool_fini(struct xrt_subdev_pool *spool) >> +{ >> + struct list_head *dl = &spool->xsp_dev_list; >> + struct mutex *lk = &spool->xsp_lock; >> + >> + mutex_lock(lk); >> + > i am wondering about the locking here. > > xsp_closing is only set to true in this function. > > the unlocking then relocking in the loop is strange, why do you need to do this ? Right, I don't need to hold the lock while going through the list and destroy each subdev. Setting xsp_closing to true will prevent others from messing up with the list already. I will fix this. >> + if (spool->xsp_closing) { >> + mutex_unlock(lk); >> + return; >> + } >> + >> + spool->xsp_closing = true; >> + /* Remove subdev in the reverse order of added. */ >> + while (!list_empty(dl)) { >> + struct xrt_subdev *sdev = list_first_entry(dl, struct xrt_subdev, xs_dev_list); >> + >> + xrt_subdev_pool_wait_for_holders(spool, sdev); >> + list_del(&sdev->xs_dev_list); >> + mutex_unlock(lk); >> + xrt_subdev_destroy(sdev); >> + mutex_lock(lk); >> + } >> + >> + mutex_unlock(lk); >> +} >> + >> +static struct xrt_subdev_holder *xrt_subdev_find_holder(struct xrt_subdev *sdev, >> + struct device *holder_dev) >> +{ >> + struct list_head *hl = &sdev->xs_holder_list; >> + struct xrt_subdev_holder *holder; >> + const struct list_head *ptr; >> + >> + list_for_each(ptr, hl) { >> + holder = list_entry(ptr, struct xrt_subdev_holder, xsh_holder_list); >> + if (holder->xsh_holder == holder_dev) >> + return holder; >> + } >> + return NULL; >> +} >> + >> +static int xrt_subdev_hold(struct xrt_subdev *sdev, struct device *holder_dev) >> +{ >> + struct xrt_subdev_holder *holder = xrt_subdev_find_holder(sdev, holder_dev); >> + struct list_head *hl = &sdev->xs_holder_list; >> + >> + if (!holder) { >> + holder = vzalloc(sizeof(*holder)); >> + if (!holder) >> + return -ENOMEM; >> + holder->xsh_holder = holder_dev; >> + kref_init(&holder->xsh_kref); >> + list_add_tail(&holder->xsh_holder_list, hl); >> + } else { >> + kref_get(&holder->xsh_kref); >> + } >> + >> + return 0; >> +} >> + >> +static void xrt_subdev_free_holder_kref(struct kref *kref) >> +{ >> + struct xrt_subdev_holder *holder = container_of(kref, struct xrt_subdev_holder, xsh_kref); >> + >> + xrt_subdev_free_holder(holder); >> +} >> + >> +static int >> +xrt_subdev_release(struct xrt_subdev *sdev, struct device *holder_dev) >> +{ >> + struct xrt_subdev_holder *holder = xrt_subdev_find_holder(sdev, holder_dev); >> + struct list_head *hl = &sdev->xs_holder_list; >> + >> + if (!holder) { >> + dev_err(holder_dev, "can't release, %s did not hold %s", >> + dev_name(holder_dev), dev_name(DEV(sdev->xs_pdev))); >> + return -EINVAL; >> + } >> + kref_put(&holder->xsh_kref, xrt_subdev_free_holder_kref); >> + >> + /* kref_put above may remove holder from list. */ >> + if (list_empty(hl)) >> + complete(&sdev->xs_holder_comp); >> + return 0; >> +} >> + >> +int xrt_subdev_pool_add(struct xrt_subdev_pool *spool, enum xrt_subdev_id id, >> + xrt_subdev_root_cb_t pcb, void *pcb_arg, char *dtb) >> +{ >> + struct mutex *lk = &spool->xsp_lock; >> + struct list_head *dl = &spool->xsp_dev_list; >> + struct xrt_subdev *sdev; >> + int ret = 0; >> + >> + sdev = xrt_subdev_create(spool->xsp_owner, id, pcb, pcb_arg, dtb); >> + if (sdev) { >> + mutex_lock(lk); >> + if (spool->xsp_closing) { >> + /* No new subdev when pool is going away. */ >> + xrt_err(sdev->xs_pdev, "pool is closing"); >> + ret = -ENODEV; >> + } else { >> + list_add(&sdev->xs_dev_list, dl); >> + } >> + mutex_unlock(lk); >> + if (ret) >> + xrt_subdev_destroy(sdev); >> + } else { >> + ret = -EINVAL; >> + } >> + >> + ret = ret ? ret : sdev->xs_pdev->id; >> + return ret; >> +} >> + >> +int xrt_subdev_pool_del(struct xrt_subdev_pool *spool, enum xrt_subdev_id id, int instance) >> +{ >> + const struct list_head *ptr; >> + struct mutex *lk = &spool->xsp_lock; >> + struct list_head *dl = &spool->xsp_dev_list; >> + struct xrt_subdev *sdev; >> + int ret = -ENOENT; >> + >> + mutex_lock(lk); >> + list_for_each(ptr, dl) { >> + sdev = list_entry(ptr, struct xrt_subdev, xs_dev_list); >> + if (sdev->xs_id != id || sdev->xs_pdev->id != instance) >> + continue; >> + xrt_subdev_pool_wait_for_holders(spool, sdev); >> + list_del(&sdev->xs_dev_list); >> + ret = 0; >> + break; >> + } >> + mutex_unlock(lk); >> + if (ret) >> + return ret; >> + >> + xrt_subdev_destroy(sdev); >> + return 0; >> +} >> + >> +static int xrt_subdev_pool_get_impl(struct xrt_subdev_pool *spool, xrt_subdev_match_t match, >> + void *arg, struct device *holder_dev, struct xrt_subdev **sdevp) >> +{ >> + const struct list_head *ptr; >> + struct mutex *lk = &spool->xsp_lock; >> + struct list_head *dl = &spool->xsp_dev_list; >> + struct xrt_subdev *sdev = NULL; >> + int ret = -ENOENT; >> + >> + mutex_lock(lk); >> + >> + if (match == XRT_SUBDEV_MATCH_PREV) { >> + struct platform_device *pdev = (struct platform_device *)arg; >> + struct xrt_subdev *d = NULL; >> + >> + if (!pdev) { >> + sdev = list_empty(dl) ? NULL : >> + list_last_entry(dl, struct xrt_subdev, xs_dev_list); >> + } else { >> + list_for_each(ptr, dl) { >> + d = list_entry(ptr, struct xrt_subdev, xs_dev_list); >> + if (d->xs_pdev != pdev) >> + continue; >> + if (!list_is_first(ptr, dl)) >> + sdev = list_prev_entry(d, xs_dev_list); >> + break; >> + } >> + } >> + } else if (match == XRT_SUBDEV_MATCH_NEXT) { >> + struct platform_device *pdev = (struct platform_device *)arg; >> + struct xrt_subdev *d = NULL; >> + >> + if (!pdev) { >> + sdev = list_first_entry_or_null(dl, struct xrt_subdev, xs_dev_list); >> + } else { >> + list_for_each(ptr, dl) { >> + d = list_entry(ptr, struct xrt_subdev, xs_dev_list); >> + if (d->xs_pdev != pdev) >> + continue; >> + if (!list_is_last(ptr, dl)) >> + sdev = list_next_entry(d, xs_dev_list); >> + break; >> + } >> + } >> + } else { >> + list_for_each(ptr, dl) { >> + struct xrt_subdev *d = NULL; >> + >> + d = list_entry(ptr, struct xrt_subdev, xs_dev_list); >> + if (d && !match(d->xs_id, d->xs_pdev, arg)) >> + continue; >> + sdev = d; >> + break; >> + } >> + } > 3 similar blocks of code > > This looks like it could be refactored into this else case and minor changes for match_next/prev Will refactor and keep only one list_for_each() loop. >> + >> + if (sdev) >> + ret = xrt_subdev_hold(sdev, holder_dev); >> + >> + mutex_unlock(lk); >> + >> + if (!ret) >> + *sdevp = sdev; >> + return ret; >> +} >> + >> +int xrt_subdev_pool_get(struct xrt_subdev_pool *spool, xrt_subdev_match_t match, void *arg, >> + struct device *holder_dev, struct platform_device **pdevp) >> +{ >> + int rc; >> + struct xrt_subdev *sdev; >> + >> + rc = xrt_subdev_pool_get_impl(spool, match, arg, holder_dev, &sdev); >> + if (rc) { >> + if (rc != -ENOENT) >> + dev_err(holder_dev, "failed to hold device: %d", rc); >> + return rc; >> + } >> + >> + if (!DEV_IS_PCI(holder_dev)) { > ! root_dev() Will add root_dev(). >> + xrt_dbg(to_platform_device(holder_dev), "%s <<==== %s", >> + dev_name(holder_dev), dev_name(DEV(sdev->xs_pdev))); >> + } >> + >> + *pdevp = sdev->xs_pdev; >> + return 0; >> +} >> + >> +static int xrt_subdev_pool_put_impl(struct xrt_subdev_pool *spool, struct platform_device *pdev, >> + struct device *holder_dev) >> +{ >> + const struct list_head *ptr; >> + struct mutex *lk = &spool->xsp_lock; >> + struct list_head *dl = &spool->xsp_dev_list; >> + struct xrt_subdev *sdev; >> + int ret = -ENOENT; >> + >> + mutex_lock(lk); >> + list_for_each(ptr, dl) { >> + sdev = list_entry(ptr, struct xrt_subdev, xs_dev_list); >> + if (sdev->xs_pdev != pdev) >> + continue; > Could this and similar looping be avoided by storing sdev in pdev ? Not sure which field in struct platform_device can sdev pointer be saved? >> + ret = xrt_subdev_release(sdev, holder_dev); >> + break; >> + } >> + mutex_unlock(lk); >> + >> + return ret; >> +} >> + >> +int xrt_subdev_pool_put(struct xrt_subdev_pool *spool, struct platform_device *pdev, >> + struct device *holder_dev) >> +{ >> + int ret = xrt_subdev_pool_put_impl(spool, pdev, holder_dev); >> + >> + if (ret) >> + return ret; >> + >> + if (!DEV_IS_PCI(holder_dev)) { > ! root_dev() or similar. > > If you really need to use DEV_IS_PCI, do it only once so when you need to change something you don not have to find all the calls to DEV_IS_PCI. Will add root_dev() function. >> + xrt_dbg(to_platform_device(holder_dev), "%s <<==X== %s", >> + dev_name(holder_dev), dev_name(DEV(pdev))); >> + } >> + return 0; >> +} >> + >> +void xrt_subdev_pool_trigger_event(struct xrt_subdev_pool *spool, enum xrt_events e) >> +{ >> + struct platform_device *tgt = NULL; >> + struct xrt_subdev *sdev = NULL; >> + struct xrt_event evt; >> + >> + while (!xrt_subdev_pool_get_impl(spool, XRT_SUBDEV_MATCH_NEXT, >> + tgt, spool->xsp_owner, &sdev)) { >> + tgt = sdev->xs_pdev; >> + evt.xe_evt = e; >> + evt.xe_subdev.xevt_subdev_id = sdev->xs_id; >> + evt.xe_subdev.xevt_subdev_instance = tgt->id; >> + xrt_subdev_root_request(tgt, XRT_ROOT_EVENT, &evt); >> + xrt_subdev_pool_put_impl(spool, tgt, spool->xsp_owner); >> + } >> +} >> + >> +void xrt_subdev_pool_handle_event(struct xrt_subdev_pool *spool, struct xrt_event *evt) >> +{ >> + struct platform_device *tgt = NULL; >> + struct xrt_subdev *sdev = NULL; >> + >> + while (!xrt_subdev_pool_get_impl(spool, XRT_SUBDEV_MATCH_NEXT, >> + tgt, spool->xsp_owner, &sdev)) { >> + tgt = sdev->xs_pdev; >> + xleaf_ioctl(tgt, XRT_XLEAF_EVENT, evt); >> + xrt_subdev_pool_put_impl(spool, tgt, spool->xsp_owner); >> + } >> +} >> + >> +ssize_t xrt_subdev_pool_get_holders(struct xrt_subdev_pool *spool, >> + struct platform_device *pdev, char *buf, size_t len) >> +{ >> + const struct list_head *ptr; >> + struct mutex *lk = &spool->xsp_lock; >> + struct list_head *dl = &spool->xsp_dev_list; >> + struct xrt_subdev *sdev; >> + ssize_t ret = 0; >> + >> + mutex_lock(lk); >> + list_for_each(ptr, dl) { >> + sdev = list_entry(ptr, struct xrt_subdev, xs_dev_list); >> + if (sdev->xs_pdev != pdev) >> + continue; >> + ret = xrt_subdev_get_holders(sdev, buf, len); >> + break; >> + } >> + mutex_unlock(lk); >> + >> + return ret; >> +} >> +EXPORT_SYMBOL_GPL(xrt_subdev_pool_get_holders); >> + >> +int xleaf_broadcast_event(struct platform_device *pdev, enum xrt_events evt, bool async) >> +{ >> + struct xrt_event e = { evt, }; >> + u32 cmd = async ? XRT_ROOT_EVENT_ASYNC : XRT_ROOT_EVENT; >> + >> + WARN_ON(evt == XRT_EVENT_POST_CREATION || evt == XRT_EVENT_PRE_REMOVAL); >> + return xrt_subdev_root_request(pdev, cmd, &e); >> +} >> +EXPORT_SYMBOL_GPL(xleaf_broadcast_event); >> + >> +void xleaf_hot_reset(struct platform_device *pdev) >> +{ >> + xrt_subdev_root_request(pdev, XRT_ROOT_HOT_RESET, NULL); >> +} >> +EXPORT_SYMBOL_GPL(xleaf_hot_reset); >> + >> +void xleaf_get_barres(struct platform_device *pdev, struct resource **res, uint bar_idx) >> +{ >> + struct xrt_root_ioctl_get_res arg = { 0 }; >> + >> + if (bar_idx > PCI_STD_RESOURCE_END) { >> + xrt_err(pdev, "Invalid bar idx %d", bar_idx); >> + *res = NULL; >> + return; >> + } >> + >> + xrt_subdev_root_request(pdev, XRT_ROOT_GET_RESOURCE, &arg); >> + >> + *res = &arg.xpigr_res[bar_idx]; > is this correct ? > > do all res need to be found to return a single one ? It does not seem to hurt to do so, if the code is simpler. Do you see a bug here? >> +} >> + >> +void xleaf_get_root_id(struct platform_device *pdev, unsigned short *vendor, unsigned short *device, >> + unsigned short *subvendor, unsigned short *subdevice) >> +{ >> + struct xrt_root_ioctl_get_id id = { 0 }; >> + >> + xrt_subdev_root_request(pdev, XRT_ROOT_GET_ID, (void *)&id); >> + if (vendor) >> + *vendor = id.xpigi_vendor_id; >> + if (device) >> + *device = id.xpigi_device_id; >> + if (subvendor) >> + *subvendor = id.xpigi_sub_vendor_id; >> + if (subdevice) >> + *subdevice = id.xpigi_sub_device_id; > not setting anything because user passed in all nulls would make this function a noop. Will add a warning, if all pointers passed in are NULL. >> +} >> + >> +struct device *xleaf_register_hwmon(struct platform_device *pdev, const char *name, void *drvdata, >> + const struct attribute_group **grps) >> +{ >> + struct xrt_root_ioctl_hwmon hm = { true, name, drvdata, grps, }; >> + >> + xrt_subdev_root_request(pdev, XRT_ROOT_HWMON, (void *)&hm); >> + return hm.xpih_hwmon_dev; >> +} >> + >> +void xleaf_unregister_hwmon(struct platform_device *pdev, struct device *hwmon) >> +{ >> + struct xrt_root_ioctl_hwmon hm = { false, }; >> + >> + hm.xpih_hwmon_dev = hwmon; >> + xrt_subdev_root_request(pdev, XRT_ROOT_HWMON, (void *)&hm); >> +} >> diff --git a/drivers/fpga/xrt/lib/subdev_pool.h b/drivers/fpga/xrt/lib/subdev_pool.h >> new file mode 100644 >> index 000000000000..50a8490e0e41 > apologies for delay, was busy. > > If it seems like i forgot a train of thought, i did. > >> --- /dev/null >> +++ b/drivers/fpga/xrt/lib/subdev_pool.h >> @@ -0,0 +1,53 @@ >> +/* SPDX-License-Identifier: GPL-2.0 */ >> +/* >> + * Header file for Xilinx Runtime (XRT) driver >> + * >> + * Copyright (C) 2020-2021 Xilinx, Inc. >> + * >> + * Authors: >> + * Cheng Zhen<maxz@xilinx.com> >> + */ >> + >> +#ifndef _XRT_SUBDEV_POOL_H_ >> +#define _XRT_SUBDEV_POOL_H_ >> + >> +#include "xroot.h" >> + >> +/* >> + * It manages a list of xrt_subdevs for root and group drivers. > 'It' does not have a lot of context, better would be > > The xrt_subdev_pool struct .. Sure. >> + */ >> +struct xrt_subdev_pool { >> + struct list_head xsp_dev_list; >> + struct device *xsp_owner; >> + struct mutex xsp_lock; /* pool lock */ > Header files should be self contained, a quick look at xroot.h makes me suspicious that device and mutex decls assume the includer has added their headers before this one Will add these two headers here. >> + bool xsp_closing; > If you thing additional state will be needed, you could change this to a bitfield. sizewise with compiler padding i don't think the size would change. Will consider using a bit flag in the future when more state is needed. >> +}; >> + >> +/* >> + * Subdev pool API for root and group drivers only. > 'API' makes me think these should go in include/linux/fpga > > Do/will these functions get called outside of the drivers/fpga ? No, these are internal functions. Will change "API" to "helper functions". >> + */ >> +void xrt_subdev_pool_init(struct device *dev, >> + struct xrt_subdev_pool *spool); >> +void xrt_subdev_pool_fini(struct xrt_subdev_pool *spool); >> +int xrt_subdev_pool_get(struct xrt_subdev_pool *spool, >> + xrt_subdev_match_t match, >> + void *arg, struct device *holder_dev, >> + struct platform_device **pdevp); >> +int xrt_subdev_pool_put(struct xrt_subdev_pool *spool, >> + struct platform_device *pdev, >> + struct device *holder_dev); >> +int xrt_subdev_pool_add(struct xrt_subdev_pool *spool, >> + enum xrt_subdev_id id, xrt_subdev_root_cb_t pcb, >> + void *pcb_arg, char *dtb); >> +int xrt_subdev_pool_del(struct xrt_subdev_pool *spool, >> + enum xrt_subdev_id id, int instance); >> +ssize_t xrt_subdev_pool_get_holders(struct xrt_subdev_pool *spool, >> + struct platform_device *pdev, >> + char *buf, size_t len); >> + >> +void xrt_subdev_pool_trigger_event(struct xrt_subdev_pool *spool, >> + enum xrt_events evt); >> +void xrt_subdev_pool_handle_event(struct xrt_subdev_pool *spool, >> + struct xrt_event *evt); >> + >> +#endif /* _XRT_SUBDEV_POOL_H_ */ >> diff --git a/drivers/fpga/xrt/lib/xroot.c b/drivers/fpga/xrt/lib/xroot.c >> new file mode 100644 >> index 000000000000..3dc7b0243277 >> --- /dev/null >> +++ b/drivers/fpga/xrt/lib/xroot.c >> @@ -0,0 +1,598 @@ >> +// SPDX-License-Identifier: GPL-2.0 >> +/* >> + * Xilinx Alveo FPGA Root Functions >> + * >> + * Copyright (C) 2020-2021 Xilinx, Inc. >> + * >> + * Authors: >> + * Cheng Zhen<maxz@xilinx.com> >> + */ >> + >> +#include <linux/module.h> >> +#include <linux/pci.h> >> +#include <linux/hwmon.h> >> +#include "xroot.h" >> +#include "subdev_pool.h" >> +#include "group.h" >> +#include "metadata.h" >> + >> +#define XROOT_PDEV(xr) ((xr)->pdev) >> +#define XROOT_DEV(xr) (&(XROOT_PDEV(xr)->dev)) >> +#define xroot_err(xr, fmt, args...) \ >> + dev_err(XROOT_DEV(xr), "%s: " fmt, __func__, ##args) >> +#define xroot_warn(xr, fmt, args...) \ >> + dev_warn(XROOT_DEV(xr), "%s: " fmt, __func__, ##args) >> +#define xroot_info(xr, fmt, args...) \ >> + dev_info(XROOT_DEV(xr), "%s: " fmt, __func__, ##args) >> +#define xroot_dbg(xr, fmt, args...) \ >> + dev_dbg(XROOT_DEV(xr), "%s: " fmt, __func__, ##args) >> + >> +#define XRT_VSEC_ID 0x20 > Is this the best place to define some pci magic ? > > It looks like the xroot is combination of the root of the device tree and the pci setup for the board. > > Can the pci-ness be split and the root mostly handling how the subtrees are organized ? Root driver is a PCIE device driver by design, so it makes sense to define pci specific stuff here. It manages the set of group drivers by calling into above pool API. So, the code has already been split. >> + >> +#define XROOT_GRP_FIRST (-1) >> +#define XROOT_GRP_LAST (-2) >> + >> +static int xroot_root_cb(struct device *, void *, u32, void *); >> + >> +struct xroot_evt { >> + struct list_head list; >> + struct xrt_event evt; >> + struct completion comp; >> + bool async; >> +}; >> + >> +struct xroot_events { >> + struct mutex evt_lock; /* event lock */ >> + struct list_head evt_list; >> + struct work_struct evt_work; >> +}; >> + >> +struct xroot_grps { >> + struct xrt_subdev_pool pool; >> + struct work_struct bringup_work; >> + atomic_t bringup_pending; >> + atomic_t bringup_failed; > combine with bitfield These two are counters, not bit flags. >> + struct completion bringup_comp; >> +}; >> + >> +struct xroot { >> + struct pci_dev *pdev; >> + struct xroot_events events; >> + struct xroot_grps grps; >> + struct xroot_pf_cb pf_cb; > expand pf_cb, maybe 'physical_function_callback' ? Sure. >> +}; >> + >> +struct xroot_grp_match_arg { >> + enum xrt_subdev_id id; >> + int instance; >> +}; >> + >> +static bool xroot_grp_match(enum xrt_subdev_id id, >> + struct platform_device *pdev, void *arg) >> +{ >> + struct xroot_grp_match_arg *a = (struct xroot_grp_match_arg *)arg; >> + return id == a->id && pdev->id == a->instance; > scanning the code i expected to see ... && pdev->instance == a->instance > > pdev->id == a->instance looks like a bug, a change to pdev->id element name to pdev->instance or in needed of a comment. pdev is of struct platform_device type, so we can't change. I will add a comment. >> +} >> + >> +static int xroot_get_group(struct xroot *xr, int instance, >> + struct platform_device **grpp) >> +{ >> + int rc = 0; >> + struct xrt_subdev_pool *grps = &xr->grps.pool; >> + struct device *dev = DEV(xr->pdev); >> + struct xroot_grp_match_arg arg = { XRT_SUBDEV_GRP, instance }; >> + >> + if (instance == XROOT_GRP_LAST) { >> + rc = xrt_subdev_pool_get(grps, XRT_SUBDEV_MATCH_NEXT, >> + *grpp, dev, grpp); >> + } else if (instance == XROOT_GRP_FIRST) { >> + rc = xrt_subdev_pool_get(grps, XRT_SUBDEV_MATCH_PREV, >> + *grpp, dev, grpp); > For consistency, maybe the suffix of ...MATCH_NEXT/PREV should be changed to LAST/FIRST It is only for finding last and first when the referring device passed in is NULL. Otherwise, it is next and prev. So, can't really change here. >> + } else { >> + rc = xrt_subdev_pool_get(grps, xroot_grp_match, >> + &arg, dev, grpp); >> + } >> + >> + if (rc && rc != -ENOENT) >> + xroot_err(xr, "failed to hold group %d: %d", instance, rc); >> + return rc; >> +} >> + >> +static void xroot_put_group(struct xroot *xr, struct platform_device *grp) >> +{ >> + int inst = grp->id; >> + int rc = xrt_subdev_pool_put(&xr->grps.pool, grp, DEV(xr->pdev)); >> + >> + if (rc) >> + xroot_err(xr, "failed to release group %d: %d", inst, rc); >> +} >> + >> +static int xroot_trigger_event(struct xroot *xr, >> + struct xrt_event *e, bool async) >> +{ >> + struct xroot_evt *enew = vzalloc(sizeof(*enew)); >> + >> + if (!enew) >> + return -ENOMEM; >> + >> + enew->evt = *e; >> + enew->async = async; >> + init_completion(&enew->comp); >> + >> + mutex_lock(&xr->events.evt_lock); >> + list_add(&enew->list, &xr->events.evt_list); >> + mutex_unlock(&xr->events.evt_lock); >> + >> + schedule_work(&xr->events.evt_work); >> + >> + if (async) >> + return 0; >> + >> + wait_for_completion(&enew->comp); >> + vfree(enew); >> + return 0; >> +} >> + >> +static void >> +xroot_group_trigger_event(struct xroot *xr, int inst, enum xrt_events e) >> +{ >> + int ret; >> + struct platform_device *pdev = NULL; >> + struct xrt_event evt = { 0 }; >> + >> + WARN_ON(inst < 0); >> + /* Only triggers subdev specific events. */ >> + if (e != XRT_EVENT_POST_CREATION && e != XRT_EVENT_PRE_REMOVAL) { >> + xroot_err(xr, "invalid event %d", e); >> + return; >> + } >> + >> + ret = xroot_get_group(xr, inst, &pdev); >> + if (ret) >> + return; >> + >> + /* Triggers event for children, first. */ >> + (void)xleaf_ioctl(pdev, XRT_GROUP_TRIGGER_EVENT, (void *)(uintptr_t)e); > These voids are not needed, but maybe error checking is. It is OK for this to fail. The driver handler will issue error or warning message. I'll remove the voids. >> + >> + /* Triggers event for itself. */ >> + evt.xe_evt = e; >> + evt.xe_subdev.xevt_subdev_id = XRT_SUBDEV_GRP; >> + evt.xe_subdev.xevt_subdev_instance = inst; >> + (void)xroot_trigger_event(xr, &evt, false); >> + >> + (void)xroot_put_group(xr, pdev); >> +} >> + >> +int xroot_create_group(void *root, char *dtb) >> +{ >> + struct xroot *xr = (struct xroot *)root; >> + int ret; >> + >> + atomic_inc(&xr->grps.bringup_pending); > could this state and the error be moved to xrt_sbudev_pool_add where locking happens so atomics are not needed ? This is marked so that xrt_subdev_pool_add can be called later on it. So, can't be moved. >> + ret = xrt_subdev_pool_add(&xr->grps.pool, XRT_SUBDEV_GRP, >> + xroot_root_cb, xr, dtb); >> + if (ret >= 0) { >> + schedule_work(&xr->grps.bringup_work); >> + } else { >> + atomic_dec(&xr->grps.bringup_pending); >> + atomic_inc(&xr->grps.bringup_failed); >> + xroot_err(xr, "failed to create group: %d", ret); >> + } >> + return ret; >> +} >> +EXPORT_SYMBOL_GPL(xroot_create_group); >> + >> +static int xroot_destroy_single_group(struct xroot *xr, int instance) >> +{ > A better name would be 'xroot_destroy_group' "group" and "groups" look too close. I'd like to have a 'single' here to make the code less confusing. >> + struct platform_device *pdev = NULL; >> + int ret; >> + >> + WARN_ON(instance < 0); >> + ret = xroot_get_group(xr, instance, &pdev); >> + if (ret) >> + return ret; >> + >> + xroot_group_trigger_event(xr, instance, XRT_EVENT_PRE_REMOVAL); >> + >> + /* Now tear down all children in this group. */ >> + ret = xleaf_ioctl(pdev, XRT_GROUP_FINI_CHILDREN, NULL); >> + (void)xroot_put_group(xr, pdev); >> + if (!ret) { >> + ret = xrt_subdev_pool_del(&xr->grps.pool, XRT_SUBDEV_GRP, >> + instance); >> + } >> + >> + return ret; >> +} >> + >> +static int xroot_destroy_group(struct xroot *xr, int instance) > A better name would be 'xroot_destroy_groups' Please see my above comment. >> +{ >> + struct platform_device *target = NULL; >> + struct platform_device *deps = NULL; >> + int ret; >> + >> + WARN_ON(instance < 0); >> + /* >> + * Make sure target group exists and can't go away before >> + * we remove it's dependents >> + */ >> + ret = xroot_get_group(xr, instance, &target); >> + if (ret) >> + return ret; >> + >> + /* >> + * Remove all groups depend on target one. >> + * Assuming subdevs in higher group ID can depend on ones in >> + * lower ID groups, we remove them in the reservse order. >> + */ >> + while (xroot_get_group(xr, XROOT_GRP_LAST, &deps) != -ENOENT) { >> + int inst = deps->id; >> + >> + xroot_put_group(xr, deps); >> + if (instance == inst) >> + break; > breaking in the middle does not seem correct. > > please add a comment Will add a comment. >> + (void)xroot_destroy_single_group(xr, inst); >> + deps = NULL; >> + } >> + >> + /* Now we can remove the target group. */ >> + xroot_put_group(xr, target); >> + return xroot_destroy_single_group(xr, instance); >> +} >> + >> +static int xroot_lookup_group(struct xroot *xr, >> + struct xrt_root_ioctl_lookup_group *arg) >> +{ >> + int rc = -ENOENT; >> + struct platform_device *grp = NULL; >> + >> + while (rc < 0 && xroot_get_group(xr, XROOT_GRP_LAST, &grp) != -ENOENT) { >> + if (arg->xpilp_match_cb(XRT_SUBDEV_GRP, grp, >> + arg->xpilp_match_arg)) { >> + rc = grp->id; >> + } >> + xroot_put_group(xr, grp); >> + } >> + return rc; >> +} >> + >> +static void xroot_event_work(struct work_struct *work) >> +{ >> + struct xroot_evt *tmp; >> + struct xroot *xr = container_of(work, struct xroot, events.evt_work); >> + >> + mutex_lock(&xr->events.evt_lock); >> + while (!list_empty(&xr->events.evt_list)) { >> + tmp = list_first_entry(&xr->events.evt_list, >> + struct xroot_evt, list); >> + list_del(&tmp->list); >> + mutex_unlock(&xr->events.evt_lock); > why is unlocking necessary ? It'd be better to release the lock when you call into other code module to avoid any potential deadlock. >> + >> + (void)xrt_subdev_pool_handle_event(&xr->grps.pool, &tmp->evt); >> + >> + if (tmp->async) >> + vfree(tmp); >> + else >> + complete(&tmp->comp); >> + >> + mutex_lock(&xr->events.evt_lock); >> + } >> + mutex_unlock(&xr->events.evt_lock); >> +} >> + >> +static void xroot_event_init(struct xroot *xr) >> +{ >> + INIT_LIST_HEAD(&xr->events.evt_list); >> + mutex_init(&xr->events.evt_lock); >> + INIT_WORK(&xr->events.evt_work, xroot_event_work); >> +} >> + >> +static void xroot_event_fini(struct xroot *xr) >> +{ >> + flush_scheduled_work(); >> + WARN_ON(!list_empty(&xr->events.evt_list)); >> +} >> + >> +static int xroot_get_leaf(struct xroot *xr, struct xrt_root_ioctl_get_leaf *arg) >> +{ >> + int rc = -ENOENT; >> + struct platform_device *grp = NULL; >> + >> + while (rc && xroot_get_group(xr, XROOT_GRP_LAST, &grp) != -ENOENT) { > while (rc) ? > > while we see an error on xleaf_ioctl, keep going ? > > Seems like would rather have !rc The root is trying to call into each group to find a leaf instance. If xleaf_call returns error, it means that it can't find it. So, we continue with next group. > similar below in put_leaf See my comment above. >> + rc = xleaf_ioctl(grp, XRT_GROUP_GET_LEAF, arg); >> + xroot_put_group(xr, grp); >> + } >> + return rc; >> +} >> + >> +static int xroot_put_leaf(struct xroot *xr, struct xrt_root_ioctl_put_leaf *arg) >> +{ >> + int rc = -ENOENT; >> + struct platform_device *grp = NULL; >> + >> + while (rc && xroot_get_group(xr, XROOT_GRP_LAST, &grp) != -ENOENT) { >> + rc = xleaf_ioctl(grp, XRT_GROUP_PUT_LEAF, arg); >> + xroot_put_group(xr, grp); >> + } >> + return rc; >> +} >> + >> +static int xroot_root_cb(struct device *dev, void *parg, u32 cmd, void *arg) >> +{ >> + struct xroot *xr = (struct xroot *)parg; >> + int rc = 0; >> + >> + switch (cmd) { >> + /* Leaf actions. */ >> + case XRT_ROOT_GET_LEAF: { >> + struct xrt_root_ioctl_get_leaf *getleaf = >> + (struct xrt_root_ioctl_get_leaf *)arg; >> + rc = xroot_get_leaf(xr, getleaf); >> + break; >> + } >> + case XRT_ROOT_PUT_LEAF: { >> + struct xrt_root_ioctl_put_leaf *putleaf = >> + (struct xrt_root_ioctl_put_leaf *)arg; >> + rc = xroot_put_leaf(xr, putleaf); >> + break; >> + } > looking at these two cases without any changes to arg but a cast, i think these and the next pass the void * onto the function and have the function manage the cast. The functions are not only called inside xroot_root_cb(), so it does not make sense to force other callers to pass a void *. >> + case XRT_ROOT_GET_LEAF_HOLDERS: { >> + struct xrt_root_ioctl_get_holders *holders = >> + (struct xrt_root_ioctl_get_holders *)arg; >> + rc = xrt_subdev_pool_get_holders(&xr->grps.pool, >> + holders->xpigh_pdev, >> + holders->xpigh_holder_buf, >> + holders->xpigh_holder_buf_len); >> + break; >> + } >> + >> + /* Group actions. */ >> + case XRT_ROOT_CREATE_GROUP: >> + rc = xroot_create_group(xr, (char *)arg); >> + break; >> + case XRT_ROOT_REMOVE_GROUP: >> + rc = xroot_destroy_group(xr, (int)(uintptr_t)arg); >> + break; >> + case XRT_ROOT_LOOKUP_GROUP: { >> + struct xrt_root_ioctl_lookup_group *getgrp = >> + (struct xrt_root_ioctl_lookup_group *)arg; >> + rc = xroot_lookup_group(xr, getgrp); >> + break; >> + } >> + case XRT_ROOT_WAIT_GROUP_BRINGUP: >> + rc = xroot_wait_for_bringup(xr) ? 0 : -EINVAL; >> + break; >> + >> + /* Event actions. */ >> + case XRT_ROOT_EVENT: >> + case XRT_ROOT_EVENT_ASYNC: { >> + bool async = (cmd == XRT_ROOT_EVENT_ASYNC); >> + struct xrt_event *evt = (struct xrt_event *)arg; >> + >> + rc = xroot_trigger_event(xr, evt, async); >> + break; >> + } >> + >> + /* Device info. */ >> + case XRT_ROOT_GET_RESOURCE: { >> + struct xrt_root_ioctl_get_res *res = >> + (struct xrt_root_ioctl_get_res *)arg; >> + res->xpigr_res = xr->pdev->resource; >> + break; >> + } >> + case XRT_ROOT_GET_ID: { >> + struct xrt_root_ioctl_get_id *id = >> + (struct xrt_root_ioctl_get_id *)arg; >> + >> + id->xpigi_vendor_id = xr->pdev->vendor; >> + id->xpigi_device_id = xr->pdev->device; >> + id->xpigi_sub_vendor_id = xr->pdev->subsystem_vendor; >> + id->xpigi_sub_device_id = xr->pdev->subsystem_device; >> + break; >> + } >> + >> + /* MISC generic PCIE driver functions. */ > misc functions may need a need some place else. > > Is there a way to extend the cmd with some additional layer of abstraction ? Not sure why there is a need to do so? It is misc, but also PCIE related services. They just can't be grouped with others, but does not really mean there is need for another layer? >> + case XRT_ROOT_HOT_RESET: { >> + xr->pf_cb.xpc_hot_reset(xr->pdev); >> + break; >> + } >> + case XRT_ROOT_HWMON: { >> + struct xrt_root_ioctl_hwmon *hwmon = >> + (struct xrt_root_ioctl_hwmon *)arg; >> + >> + if (hwmon->xpih_register) { >> + hwmon->xpih_hwmon_dev = >> + hwmon_device_register_with_info(DEV(xr->pdev), >> + hwmon->xpih_name, >> + hwmon->xpih_drvdata, >> + NULL, >> + hwmon->xpih_groups); >> + } else { >> + (void)hwmon_device_unregister(hwmon->xpih_hwmon_dev); >> + } >> + break; >> + } >> + >> + default: >> + xroot_err(xr, "unknown IOCTL cmd %d", cmd); >> + rc = -EINVAL; >> + break; >> + } >> + >> + return rc; >> +} >> + >> +static void xroot_bringup_group_work(struct work_struct *work) >> +{ >> + struct platform_device *pdev = NULL; >> + struct xroot *xr = container_of(work, struct xroot, grps.bringup_work); >> + >> + while (xroot_get_group(xr, XROOT_GRP_FIRST, &pdev) != -ENOENT) { >> + int r, i; >> + >> + i = pdev->id; >> + r = xleaf_ioctl(pdev, XRT_GROUP_INIT_CHILDREN, NULL); >> + (void)xroot_put_group(xr, pdev); >> + if (r == -EEXIST) >> + continue; /* Already brough up, nothing to do. */ >> + if (r) >> + atomic_inc(&xr->grps.bringup_failed); >> + >> + xroot_group_trigger_event(xr, i, XRT_EVENT_POST_CREATION); >> + >> + if (atomic_dec_and_test(&xr->grps.bringup_pending)) >> + complete(&xr->grps.bringup_comp); >> + } >> +} >> + >> +static void xroot_grps_init(struct xroot *xr) > Consistency in terms is needed. In the last few lines i see > > group, grp, grps, my vote is for group(s) Will use group(s) in struct and function names. Will use grp(s) in variable names. >> +{ >> + xrt_subdev_pool_init(DEV(xr->pdev), &xr->grps.pool); >> + INIT_WORK(&xr->grps.bringup_work, xroot_bringup_group_work); >> + atomic_set(&xr->grps.bringup_pending, 0); >> + atomic_set(&xr->grps.bringup_failed, 0); >> + init_completion(&xr->grps.bringup_comp); >> +} >> + >> +static void xroot_grps_fini(struct xroot *xr) >> +{ >> + flush_scheduled_work(); >> + xrt_subdev_pool_fini(&xr->grps.pool); >> +} >> + >> +int xroot_add_vsec_node(void *root, char *dtb) >> +{ > This is the pci part i think needs to move to its own file. Please see my comment above. >> + struct xroot *xr = (struct xroot *)root; >> + struct device *dev = DEV(xr->pdev); >> + struct xrt_md_endpoint ep = { 0 }; >> + int cap = 0, ret = 0; >> + u32 off_low, off_high, vsec_bar, header; >> + u64 vsec_off; >> + >> + while ((cap = pci_find_next_ext_capability(xr->pdev, cap, >> + PCI_EXT_CAP_ID_VNDR))) { >> + pci_read_config_dword(xr->pdev, cap + PCI_VNDR_HEADER, &header); >> + if (PCI_VNDR_HEADER_ID(header) == XRT_VSEC_ID) >> + break; >> + } >> + if (!cap) { >> + xroot_info(xr, "No Vendor Specific Capability."); >> + return -ENOENT; >> + } >> + >> + if (pci_read_config_dword(xr->pdev, cap + 8, &off_low) || >> + pci_read_config_dword(xr->pdev, cap + 12, &off_high)) { >> + xroot_err(xr, "pci_read vendor specific failed."); >> + return -EINVAL; >> + } >> + >> + ep.ep_name = XRT_MD_NODE_VSEC; >> + ret = xrt_md_add_endpoint(dev, dtb, &ep); >> + if (ret) { >> + xroot_err(xr, "add vsec metadata failed, ret %d", ret); >> + goto failed; >> + } >> + >> + vsec_bar = cpu_to_be32(off_low & 0xf); >> + ret = xrt_md_set_prop(dev, dtb, XRT_MD_NODE_VSEC, NULL, >> + XRT_MD_PROP_BAR_IDX, &vsec_bar, sizeof(vsec_bar)); >> + if (ret) { >> + xroot_err(xr, "add vsec bar idx failed, ret %d", ret); >> + goto failed; >> + } >> + >> + vsec_off = cpu_to_be64(((u64)off_high << 32) | (off_low & ~0xfU)); >> + ret = xrt_md_set_prop(dev, dtb, XRT_MD_NODE_VSEC, NULL, >> + XRT_MD_PROP_OFFSET, &vsec_off, sizeof(vsec_off)); >> + if (ret) { >> + xroot_err(xr, "add vsec offset failed, ret %d", ret); >> + goto failed; >> + } >> + >> +failed: >> + return ret; >> +} >> +EXPORT_SYMBOL_GPL(xroot_add_vsec_node); >> + >> +int xroot_add_simple_node(void *root, char *dtb, const char *endpoint) >> +{ >> + struct xroot *xr = (struct xroot *)root; >> + struct device *dev = DEV(xr->pdev); >> + struct xrt_md_endpoint ep = { 0 }; >> + int ret = 0; >> + >> + ep.ep_name = endpoint; >> + ret = xrt_md_add_endpoint(dev, dtb, &ep); >> + if (ret) >> + xroot_err(xr, "add %s failed, ret %d", endpoint, ret); >> + >> + return ret; >> +} >> +EXPORT_SYMBOL_GPL(xroot_add_simple_node); >> + >> +bool xroot_wait_for_bringup(void *root) >> +{ >> + struct xroot *xr = (struct xroot *)root; >> + >> + wait_for_completion(&xr->grps.bringup_comp); >> + return atomic_xchg(&xr->grps.bringup_failed, 0) == 0; > Is there going to a race in intialization ? There should not be. I'll change it to atomic_read() >> +} >> +EXPORT_SYMBOL_GPL(xroot_wait_for_bringup); >> + >> +int xroot_probe(struct pci_dev *pdev, struct xroot_pf_cb *cb, void **root) >> +{ >> + struct device *dev = DEV(pdev); >> + struct xroot *xr = NULL; >> + >> + dev_info(dev, "%s: probing...", __func__); >> + >> + xr = devm_kzalloc(dev, sizeof(*xr), GFP_KERNEL); >> + if (!xr) >> + return -ENOMEM; >> + >> + xr->pdev = pdev; >> + xr->pf_cb = *cb; >> + xroot_grps_init(xr); >> + xroot_event_init(xr); >> + >> + *root = xr; >> + return 0; >> +} >> +EXPORT_SYMBOL_GPL(xroot_probe); >> + >> +void xroot_remove(void *root) >> +{ >> + struct xroot *xr = (struct xroot *)root; >> + struct platform_device *grp = NULL; >> + >> + xroot_info(xr, "leaving..."); >> + >> + if (xroot_get_group(xr, XROOT_GRP_FIRST, &grp) == 0) { >> + int instance = grp->id; > another instance = id, the variable and element names should be consistent. > > earlier (id, instance) is used to uniquely determine a node. if that is so then using the names should be kept seperate. grp is also of struct platform_device, so we can't change. But, really grp->id is the instance. >> + >> + xroot_put_group(xr, grp); >> + (void)xroot_destroy_group(xr, instance); >> + } >> + >> + xroot_event_fini(xr); >> + xroot_grps_fini(xr); >> +} >> +EXPORT_SYMBOL_GPL(xroot_remove); >> + >> +void xroot_broadcast(void *root, enum xrt_events evt) >> +{ >> + struct xroot *xr = (struct xroot *)root; >> + struct xrt_event e = { 0 }; >> + >> + /* Root pf driver only broadcasts below two events. */ >> + if (evt != XRT_EVENT_POST_CREATION && evt != XRT_EVENT_PRE_REMOVAL) { >> + xroot_info(xr, "invalid event %d", evt); >> + return; >> + } >> + >> + e.xe_evt = evt; >> + e.xe_subdev.xevt_subdev_id = XRT_ROOT; >> + e.xe_subdev.xevt_subdev_instance = 0; > see.. > > id = > > instance = ->id is part of the platform_device framework, we can't change. Thanks, Max > Tom > >> + (void)xroot_trigger_event(xr, &e, false); >> +} >> +EXPORT_SYMBOL_GPL(xroot_broadcast);
Hi Tom, On 03/02/2021 08:09 AM, Tom Rix wrote: > On 2/17/21 10:40 PM, Lizhi Hou wrote: >> Add UCS driver. UCS is a hardware function discovered by walking xclbin > What does UCS stand for ? add to commit log UCS stands for User Clock Subsystem. I will add it to log. >> metadata. A platform device node will be created for it. >> UCS enables/disables the dynamic region clocks. >> >> Signed-off-by: Sonal Santan <sonal.santan@xilinx.com> >> Signed-off-by: Max Zhen <max.zhen@xilinx.com> >> Signed-off-by: Lizhi Hou <lizhih@xilinx.com> >> --- >> drivers/fpga/xrt/include/xleaf/ucs.h | 24 +++ >> drivers/fpga/xrt/lib/xleaf/ucs.c | 235 +++++++++++++++++++++++++++ >> 2 files changed, 259 insertions(+) >> create mode 100644 drivers/fpga/xrt/include/xleaf/ucs.h >> create mode 100644 drivers/fpga/xrt/lib/xleaf/ucs.c >> >> diff --git a/drivers/fpga/xrt/include/xleaf/ucs.h b/drivers/fpga/xrt/include/xleaf/ucs.h >> new file mode 100644 >> index 000000000000..a5ef0e100e12 >> --- /dev/null >> +++ b/drivers/fpga/xrt/include/xleaf/ucs.h > This header is only used by ucs.c, so is it needed ? > > could the enum be defined in ucs.c ? It will be used in the future. I will remove it. > >> @@ -0,0 +1,24 @@ >> +/* SPDX-License-Identifier: GPL-2.0 */ >> +/* >> + * Header file for XRT UCS Leaf Driver >> + * >> + * Copyright (C) 2020-2021 Xilinx, Inc. >> + * >> + * Authors: >> + * Lizhi Hou <Lizhi.Hou@xilinx.com> >> + */ >> + >> +#ifndef _XRT_UCS_H_ >> +#define _XRT_UCS_H_ >> + >> +#include "xleaf.h" >> + >> +/* >> + * UCS driver IOCTL calls. >> + */ >> +enum xrt_ucs_ioctl_cmd { >> + XRT_UCS_CHECK = XRT_XLEAF_CUSTOM_BASE, /* See comments in xleaf.h */ >> + XRT_UCS_ENABLE, > no disable ? It does not need to disable because reset the fpga bridge will disable it. I will remove ucs.h because it is not used in this patchset. >> +}; >> + >> +#endif /* _XRT_UCS_H_ */ >> diff --git a/drivers/fpga/xrt/lib/xleaf/ucs.c b/drivers/fpga/xrt/lib/xleaf/ucs.c >> new file mode 100644 >> index 000000000000..ae762c8fddbb >> --- /dev/null >> +++ b/drivers/fpga/xrt/lib/xleaf/ucs.c >> @@ -0,0 +1,235 @@ >> +// SPDX-License-Identifier: GPL-2.0 >> +/* >> + * Xilinx Alveo FPGA UCS Driver >> + * >> + * Copyright (C) 2020-2021 Xilinx, Inc. >> + * >> + * Authors: >> + * Lizhi Hou<Lizhi.Hou@xilinx.com> >> + */ >> + >> +#include <linux/mod_devicetable.h> >> +#include <linux/platform_device.h> >> +#include <linux/delay.h> >> +#include <linux/device.h> >> +#include <linux/io.h> >> +#include "metadata.h" >> +#include "xleaf.h" >> +#include "xleaf/ucs.h" >> +#include "xleaf/clock.h" >> + >> +#define UCS_ERR(ucs, fmt, arg...) \ >> + xrt_err((ucs)->pdev, fmt "\n", ##arg) >> +#define UCS_WARN(ucs, fmt, arg...) \ >> + xrt_warn((ucs)->pdev, fmt "\n", ##arg) >> +#define UCS_INFO(ucs, fmt, arg...) \ >> + xrt_info((ucs)->pdev, fmt "\n", ##arg) >> +#define UCS_DBG(ucs, fmt, arg...) \ >> + xrt_dbg((ucs)->pdev, fmt "\n", ##arg) >> + >> +#define XRT_UCS "xrt_ucs" >> + >> +#define CHANNEL1_OFFSET 0 >> +#define CHANNEL2_OFFSET 8 >> + >> +#define CLK_MAX_VALUE 6400 >> + >> +struct ucs_control_status_ch1 { >> + unsigned int shutdown_clocks_latched:1; >> + unsigned int reserved1:15; >> + unsigned int clock_throttling_average:14; >> + unsigned int reserved2:2; >> +}; > Likely needs to be packed and/or the unsigned int changed to u32 Will remove this structure because it is not used in this patch set. >> + >> +struct xrt_ucs { >> + struct platform_device *pdev; >> + void __iomem *ucs_base; >> + struct mutex ucs_lock; /* ucs dev lock */ >> +}; >> + >> +static inline u32 reg_rd(struct xrt_ucs *ucs, u32 offset) >> +{ >> + return ioread32(ucs->ucs_base + offset); >> +} >> + >> +static inline void reg_wr(struct xrt_ucs *ucs, u32 val, u32 offset) >> +{ >> + iowrite32(val, ucs->ucs_base + offset); >> +} >> + >> +static void xrt_ucs_event_cb(struct platform_device *pdev, void *arg) >> +{ >> + struct platform_device *leaf; >> + struct xrt_event *evt = (struct xrt_event *)arg; >> + enum xrt_events e = evt->xe_evt; >> + enum xrt_subdev_id id = evt->xe_subdev.xevt_subdev_id; >> + int instance = evt->xe_subdev.xevt_subdev_instance; >> + >> + switch (e) { >> + case XRT_EVENT_POST_CREATION: >> + break; >> + default: >> + xrt_dbg(pdev, "ignored event %d", e); >> + return; >> + } > this switch is a noop, remove Will change to if (e != XRT_EVENT_POST_CREATION) return -EINVAL >> + >> + if (id != XRT_SUBDEV_CLOCK) >> + return; >> + >> + leaf = xleaf_get_leaf_by_id(pdev, XRT_SUBDEV_CLOCK, instance); >> + if (!leaf) { >> + xrt_err(pdev, "does not get clock subdev"); >> + return; >> + } >> + >> + xleaf_ioctl(leaf, XRT_CLOCK_VERIFY, NULL); >> + xleaf_put_leaf(pdev, leaf); >> +} >> + >> +static void ucs_check(struct xrt_ucs *ucs, bool *latched) >> +{ > checking but not returning status, change to returning int. > > this function is called but xrt_ucs_leaf_ioctl which does return status. Will remove ucs_check() because it is not used in this patch set. > >> + struct ucs_control_status_ch1 *ucs_status_ch1; >> + u32 status; >> + >> + mutex_lock(&ucs->ucs_lock); >> + status = reg_rd(ucs, CHANNEL1_OFFSET); >> + ucs_status_ch1 = (struct ucs_control_status_ch1 *)&status; >> + if (ucs_status_ch1->shutdown_clocks_latched) { >> + UCS_ERR(ucs, >> + "Critical temperature or power event, kernel clocks have been stopped."); >> + UCS_ERR(ucs, >> + "run 'xbutil valiate -q' to continue. See AR 73398 for more details."); > This error message does not seem like it would be useful, please review. >> + /* explicitly indicate reset should be latched */ >> + *latched = true; >> + } else if (ucs_status_ch1->clock_throttling_average > >> + CLK_MAX_VALUE) { >> + UCS_ERR(ucs, "kernel clocks %d exceeds expected maximum value %d.", >> + ucs_status_ch1->clock_throttling_average, >> + CLK_MAX_VALUE); >> + } else if (ucs_status_ch1->clock_throttling_average) { >> + UCS_ERR(ucs, "kernel clocks throttled at %d%%.", >> + (ucs_status_ch1->clock_throttling_average / >> + (CLK_MAX_VALUE / 100))); >> + } >> + mutex_unlock(&ucs->ucs_lock); >> +} >> + >> +static void ucs_enable(struct xrt_ucs *ucs) >> +{ >> + reg_wr(ucs, 1, CHANNEL2_OFFSET); > lock ? Yes. will add it. >> +} >> + >> +static int >> +xrt_ucs_leaf_ioctl(struct platform_device *pdev, u32 cmd, void *arg) >> +{ >> + struct xrt_ucs *ucs; >> + int ret = 0; >> + >> + ucs = platform_get_drvdata(pdev); >> + >> + switch (cmd) { >> + case XRT_XLEAF_EVENT: >> + xrt_ucs_event_cb(pdev, arg); >> + break; >> + case XRT_UCS_CHECK: { > brace not needed here will remove. >> + ucs_check(ucs, (bool *)arg); >> + break; >> + } >> + case XRT_UCS_ENABLE: >> + ucs_enable(ucs); >> + break; >> + default: >> + xrt_err(pdev, "unsupported cmd %d", cmd); >> + return -EINVAL; >> + } >> + >> + return ret; >> +} >> + >> +static int ucs_remove(struct platform_device *pdev) >> +{ >> + struct xrt_ucs *ucs; >> + >> + ucs = platform_get_drvdata(pdev); >> + if (!ucs) { > is this possible ? Will remove. Thanks, Lizhi > > Tom > >> + xrt_err(pdev, "driver data is NULL"); >> + return -EINVAL; >> + } >> + >> + if (ucs->ucs_base) >> + iounmap(ucs->ucs_base); >> + >> + platform_set_drvdata(pdev, NULL); >> + devm_kfree(&pdev->dev, ucs); >> + >> + return 0; >> +} >> + >> +static int ucs_probe(struct platform_device *pdev) >> +{ >> + struct xrt_ucs *ucs = NULL; >> + struct resource *res; >> + int ret; >> + >> + ucs = devm_kzalloc(&pdev->dev, sizeof(*ucs), GFP_KERNEL); >> + if (!ucs) >> + return -ENOMEM; >> + >> + platform_set_drvdata(pdev, ucs); >> + ucs->pdev = pdev; >> + mutex_init(&ucs->ucs_lock); >> + >> + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); >> + ucs->ucs_base = ioremap(res->start, res->end - res->start + 1); >> + if (!ucs->ucs_base) { >> + UCS_ERR(ucs, "map base %pR failed", res); >> + ret = -EFAULT; >> + goto failed; >> + } >> + ucs_enable(ucs); >> + >> + return 0; >> + >> +failed: >> + ucs_remove(pdev); >> + return ret; >> +} >> + >> +static struct xrt_subdev_endpoints xrt_ucs_endpoints[] = { >> + { >> + .xse_names = (struct xrt_subdev_ep_names[]) { >> + { .ep_name = XRT_MD_NODE_UCS_CONTROL_STATUS }, >> + { NULL }, >> + }, >> + .xse_min_ep = 1, >> + }, >> + { 0 }, >> +}; >> + >> +static struct xrt_subdev_drvdata xrt_ucs_data = { >> + .xsd_dev_ops = { >> + .xsd_ioctl = xrt_ucs_leaf_ioctl, >> + }, >> +}; >> + >> +static const struct platform_device_id xrt_ucs_table[] = { >> + { XRT_UCS, (kernel_ulong_t)&xrt_ucs_data }, >> + { }, >> +}; >> + >> +static struct platform_driver xrt_ucs_driver = { >> + .driver = { >> + .name = XRT_UCS, >> + }, >> + .probe = ucs_probe, >> + .remove = ucs_remove, >> + .id_table = xrt_ucs_table, >> +}; >> + >> +void ucs_leaf_init_fini(bool init) >> +{ >> + if (init) >> + xleaf_register_driver(XRT_SUBDEV_UCS, &xrt_ucs_driver, xrt_ucs_endpoints); >> + else >> + xleaf_unregister_driver(XRT_SUBDEV_UCS); >> +}
Hi Tom, On 03/06/2021 07:54 AM, Tom Rix wrote: > On 2/17/21 10:40 PM, Lizhi Hou wrote: >> Add partition isolation platform driver. partition isolation is >> a hardware function discovered by walking firmware metadata. >> A platform device node will be created for it. Partition isolation >> function isolate the different fpga regions >> >> Signed-off-by: Sonal Santan <sonal.santan@xilinx.com> >> Signed-off-by: Max Zhen <max.zhen@xilinx.com> >> Signed-off-by: Lizhi Hou <lizhih@xilinx.com> >> --- >> drivers/fpga/xrt/include/xleaf/axigate.h | 25 ++ >> drivers/fpga/xrt/lib/xleaf/axigate.c | 298 +++++++++++++++++++++++ >> 2 files changed, 323 insertions(+) >> create mode 100644 drivers/fpga/xrt/include/xleaf/axigate.h >> create mode 100644 drivers/fpga/xrt/lib/xleaf/axigate.c >> >> diff --git a/drivers/fpga/xrt/include/xleaf/axigate.h b/drivers/fpga/xrt/include/xleaf/axigate.h >> new file mode 100644 >> index 000000000000..2cef71e13b30 >> --- /dev/null >> +++ b/drivers/fpga/xrt/include/xleaf/axigate.h >> @@ -0,0 +1,25 @@ >> +/* SPDX-License-Identifier: GPL-2.0 */ >> +/* >> + * Header file for XRT Axigate Leaf Driver >> + * >> + * Copyright (C) 2020-2021 Xilinx, Inc. >> + * >> + * Authors: >> + * Lizhi Hou <Lizhi.Hou@xilinx.com> >> + */ >> + >> +#ifndef _XRT_AXIGATE_H_ >> +#define _XRT_AXIGATE_H_ >> + >> +#include "xleaf.h" >> +#include "metadata.h" >> + >> +/* >> + * AXIGATE driver IOCTL calls. >> + */ >> +enum xrt_axigate_ioctl_cmd { >> + XRT_AXIGATE_FREEZE = XRT_XLEAF_CUSTOM_BASE, /* See comments in xleaf.h */ >> + XRT_AXIGATE_FREE, > These are substrings, could change suffix to make it harder for developer to mix up. Will change 'freeze' to 'close', 'free' to 'open'. >> +}; >> + >> +#endif /* _XRT_AXIGATE_H_ */ >> diff --git a/drivers/fpga/xrt/lib/xleaf/axigate.c b/drivers/fpga/xrt/lib/xleaf/axigate.c >> new file mode 100644 >> index 000000000000..382969f9925f >> --- /dev/null >> +++ b/drivers/fpga/xrt/lib/xleaf/axigate.c >> @@ -0,0 +1,298 @@ >> +// SPDX-License-Identifier: GPL-2.0 >> +/* >> + * Xilinx Alveo FPGA AXI Gate Driver >> + * >> + * Copyright (C) 2020-2021 Xilinx, Inc. >> + * >> + * Authors: >> + * Lizhi Hou<Lizhi.Hou@xilinx.com> >> + */ >> + >> +#include <linux/mod_devicetable.h> >> +#include <linux/platform_device.h> >> +#include <linux/delay.h> >> +#include <linux/device.h> >> +#include <linux/io.h> >> +#include "metadata.h" >> +#include "xleaf.h" >> +#include "xleaf/axigate.h" >> + >> +#define XRT_AXIGATE "xrt_axigate" >> + >> +struct axigate_regs { >> + u32 iag_wr; >> + u32 iag_rvsd; >> + u32 iag_rd; >> +} __packed; > similar to other patches, prefix of element is not needed. Will remove this and use #define and regmap. >> + >> +struct xrt_axigate { >> + struct platform_device *pdev; >> + void *base; >> + struct mutex gate_lock; /* gate dev lock */ >> + >> + void *evt_hdl; >> + const char *ep_name; >> + >> + bool gate_freezed; >> +}; >> + >> +/* the ep names are in the order of hardware layers */ >> +static const char * const xrt_axigate_epnames[] = { >> + XRT_MD_NODE_GATE_PLP, >> + XRT_MD_NODE_GATE_ULP, > what are plp, ulp ? it is helpful to comment or expand acronyms plp stands for provider logic partition and ulp stands for user logic partition. Will add comment. >> + NULL >> +}; >> + >> +#define reg_rd(g, r) \ >> + ioread32((void *)(g)->base + offsetof(struct axigate_regs, r)) >> +#define reg_wr(g, v, r) \ >> + iowrite32(v, (void *)(g)->base + offsetof(struct axigate_regs, r)) >> + >> +static inline void freeze_gate(struct xrt_axigate *gate) >> +{ >> + reg_wr(gate, 0, iag_wr); > The values written here and below are magic, the need to have #defines Will add #defines >> + ndelay(500); >> + reg_rd(gate, iag_rd); >> +} >> + >> +static inline void free_gate(struct xrt_axigate *gate) >> +{ >> + reg_wr(gate, 0x2, iag_wr); >> + ndelay(500); >> + (void)reg_rd(gate, iag_rd); >> + reg_wr(gate, 0x3, iag_wr); >> + ndelay(500); >> + reg_rd(gate, iag_rd); >> +} >> + >> +static int xrt_axigate_epname_idx(struct platform_device *pdev) >> +{ >> + int i; >> + int ret; > int i, ret; sure. >> + struct resource *res; >> + >> + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); >> + if (!res) { >> + xrt_err(pdev, "Empty Resource!"); >> + return -EINVAL; >> + } >> + >> + for (i = 0; xrt_axigate_epnames[i]; i++) { > null guarded array is useful with the size isn't know, > > in this case it is, so covert loop to using ARRAY_SIZE Will use ARRAY_SIZE. > >> + ret = strncmp(xrt_axigate_epnames[i], res->name, >> + strlen(xrt_axigate_epnames[i]) + 1); > needs a strlen check in case res->name is just a substring 'strlen() + 1' is used, thus the comparing covers substring as well. >> + if (!ret) >> + break; >> + } >> + >> + ret = (xrt_axigate_epnames[i]) ? i : -EINVAL; >> + return ret; >> +} >> + >> +static void xrt_axigate_freeze(struct platform_device *pdev) >> +{ >> + struct xrt_axigate *gate; >> + u32 freeze = 0; >> + >> + gate = platform_get_drvdata(pdev); >> + >> + mutex_lock(&gate->gate_lock); >> + freeze = reg_rd(gate, iag_rd); >> + if (freeze) { /* gate is opened */ >> + xleaf_broadcast_event(pdev, XRT_EVENT_PRE_GATE_CLOSE, false); >> + freeze_gate(gate); >> + } >> + >> + gate->gate_freezed = true; > Looks like freeze could be 0, so is setting gate_freeze = true correct all the time ? added checking for freeze_gate(). if it succeed, gate will be frozen (closed). >> + mutex_unlock(&gate->gate_lock); >> + >> + xrt_info(pdev, "freeze gate %s", gate->ep_name); >> +} >> + >> +static void xrt_axigate_free(struct platform_device *pdev) >> +{ >> + struct xrt_axigate *gate; >> + u32 freeze; >> + >> + gate = platform_get_drvdata(pdev); >> + >> + mutex_lock(&gate->gate_lock); >> + freeze = reg_rd(gate, iag_rd); >> + if (!freeze) { /* gate is closed */ >> + free_gate(gate); >> + xleaf_broadcast_event(pdev, XRT_EVENT_POST_GATE_OPEN, true); >> + /* xrt_axigate_free() could be called in event cb, thus >> + * we can not wait for the completes >> + */ >> + } >> + >> + gate->gate_freezed = false; > freezed is not a word, the element name should be 'gate_frozen' Will change to gate_closed. >> + mutex_unlock(&gate->gate_lock); >> + >> + xrt_info(pdev, "free gate %s", gate->ep_name); >> +} >> + >> +static void xrt_axigate_event_cb(struct platform_device *pdev, void *arg) >> +{ >> + struct platform_device *leaf; >> + struct xrt_event *evt = (struct xrt_event *)arg; >> + enum xrt_events e = evt->xe_evt; >> + enum xrt_subdev_id id = evt->xe_subdev.xevt_subdev_id; >> + int instance = evt->xe_subdev.xevt_subdev_instance; >> + struct xrt_axigate *gate = platform_get_drvdata(pdev); >> + struct resource *res; >> + >> + switch (e) { >> + case XRT_EVENT_POST_CREATION: >> + break; >> + default: >> + return; >> + } > convert switch() to if () Sure. >> + >> + if (id != XRT_SUBDEV_AXIGATE) >> + return; >> + >> + leaf = xleaf_get_leaf_by_id(pdev, id, instance); >> + if (!leaf) >> + return; >> + >> + res = platform_get_resource(leaf, IORESOURCE_MEM, 0); >> + if (!res || !strncmp(res->name, gate->ep_name, strlen(res->name) + 1)) { >> + (void)xleaf_put_leaf(pdev, leaf); >> + return; >> + } >> + >> + /* >> + * higher level axigate instance created, >> + * make sure the gate is openned. This covers 1RP flow which > is openned -> is opened sure. > > what is 1RP ? 1RP flow is one of hardware shell build flow. It is xilinx internal term I will remove this sentence. Thanks, Lizhi > > Tom > >> + * has plp gate as well. >> + */ >> + if (xrt_axigate_epname_idx(leaf) > xrt_axigate_epname_idx(pdev)) >> + xrt_axigate_free(pdev); >> + else >> + xleaf_ioctl(leaf, XRT_AXIGATE_FREE, NULL); >> + >> + (void)xleaf_put_leaf(pdev, leaf); >> +} >> + >> +static int >> +xrt_axigate_leaf_ioctl(struct platform_device *pdev, u32 cmd, void *arg) >> +{ >> + switch (cmd) { >> + case XRT_XLEAF_EVENT: >> + xrt_axigate_event_cb(pdev, arg); >> + break; >> + case XRT_AXIGATE_FREEZE: >> + xrt_axigate_freeze(pdev); >> + break; >> + case XRT_AXIGATE_FREE: >> + xrt_axigate_free(pdev); >> + break; >> + default: >> + xrt_err(pdev, "unsupported cmd %d", cmd); >> + return -EINVAL; >> + } >> + >> + return 0; >> +} >> + >> +static int xrt_axigate_remove(struct platform_device *pdev) >> +{ >> + struct xrt_axigate *gate; >> + >> + gate = platform_get_drvdata(pdev); >> + >> + if (gate->base) >> + iounmap(gate->base); >> + >> + platform_set_drvdata(pdev, NULL); >> + devm_kfree(&pdev->dev, gate); >> + >> + return 0; >> +} >> + >> +static int xrt_axigate_probe(struct platform_device *pdev) >> +{ >> + struct xrt_axigate *gate; >> + struct resource *res; >> + int ret; >> + >> + gate = devm_kzalloc(&pdev->dev, sizeof(*gate), GFP_KERNEL); >> + if (!gate) >> + return -ENOMEM; >> + >> + gate->pdev = pdev; >> + platform_set_drvdata(pdev, gate); >> + >> + xrt_info(pdev, "probing..."); >> + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); >> + if (!res) { >> + xrt_err(pdev, "Empty resource 0"); >> + ret = -EINVAL; >> + goto failed; >> + } >> + >> + gate->base = ioremap(res->start, res->end - res->start + 1); >> + if (!gate->base) { >> + xrt_err(pdev, "map base iomem failed"); >> + ret = -EFAULT; >> + goto failed; >> + } >> + >> + gate->ep_name = res->name; >> + >> + mutex_init(&gate->gate_lock); >> + >> + return 0; >> + >> +failed: >> + xrt_axigate_remove(pdev); >> + return ret; >> +} >> + >> +static struct xrt_subdev_endpoints xrt_axigate_endpoints[] = { >> + { >> + .xse_names = (struct xrt_subdev_ep_names[]) { >> + { .ep_name = "ep_pr_isolate_ulp_00" }, >> + { NULL }, >> + }, >> + .xse_min_ep = 1, >> + }, >> + { >> + .xse_names = (struct xrt_subdev_ep_names[]) { >> + { .ep_name = "ep_pr_isolate_plp_00" }, >> + { NULL }, >> + }, >> + .xse_min_ep = 1, >> + }, >> + { 0 }, >> +}; >> + >> +static struct xrt_subdev_drvdata xrt_axigate_data = { >> + .xsd_dev_ops = { >> + .xsd_ioctl = xrt_axigate_leaf_ioctl, >> + }, >> +}; >> + >> +static const struct platform_device_id xrt_axigate_table[] = { >> + { XRT_AXIGATE, (kernel_ulong_t)&xrt_axigate_data }, >> + { }, >> +}; >> + >> +static struct platform_driver xrt_axigate_driver = { >> + .driver = { >> + .name = XRT_AXIGATE, >> + }, >> + .probe = xrt_axigate_probe, >> + .remove = xrt_axigate_remove, >> + .id_table = xrt_axigate_table, >> +}; >> + >> +void axigate_leaf_init_fini(bool init) >> +{ >> + if (init) { >> + xleaf_register_driver(XRT_SUBDEV_AXIGATE, >> + &xrt_axigate_driver, xrt_axigate_endpoints); >> + } else { >> + xleaf_unregister_driver(XRT_SUBDEV_AXIGATE); >> + } >> +}
Hi Moritz, On 02/21/2021 12:36 PM, Moritz Fischer wrote: > > On Wed, Feb 17, 2021 at 10:40:18PM -0800, Lizhi Hou wrote: >> Add partition isolation platform driver. partition isolation is >> a hardware function discovered by walking firmware metadata. >> A platform device node will be created for it. Partition isolation >> function isolate the different fpga regions >> >> Signed-off-by: Sonal Santan <sonal.santan@xilinx.com> >> Signed-off-by: Max Zhen <max.zhen@xilinx.com> >> Signed-off-by: Lizhi Hou <lizhih@xilinx.com> >> --- >> drivers/fpga/xrt/include/xleaf/axigate.h | 25 ++ >> drivers/fpga/xrt/lib/xleaf/axigate.c | 298 +++++++++++++++++++++++ >> 2 files changed, 323 insertions(+) >> create mode 100644 drivers/fpga/xrt/include/xleaf/axigate.h >> create mode 100644 drivers/fpga/xrt/lib/xleaf/axigate.c >> >> diff --git a/drivers/fpga/xrt/include/xleaf/axigate.h b/drivers/fpga/xrt/include/xleaf/axigate.h >> new file mode 100644 >> index 000000000000..2cef71e13b30 >> --- /dev/null >> +++ b/drivers/fpga/xrt/include/xleaf/axigate.h >> @@ -0,0 +1,25 @@ >> +/* SPDX-License-Identifier: GPL-2.0 */ >> +/* >> + * Header file for XRT Axigate Leaf Driver >> + * >> + * Copyright (C) 2020-2021 Xilinx, Inc. >> + * >> + * Authors: >> + * Lizhi Hou <Lizhi.Hou@xilinx.com> >> + */ >> + >> +#ifndef _XRT_AXIGATE_H_ >> +#define _XRT_AXIGATE_H_ >> + >> +#include "xleaf.h" >> +#include "metadata.h" >> + >> +/* >> + * AXIGATE driver IOCTL calls. >> + */ >> +enum xrt_axigate_ioctl_cmd { >> + XRT_AXIGATE_FREEZE = XRT_XLEAF_CUSTOM_BASE, /* See comments in xleaf.h */ >> + XRT_AXIGATE_FREE, >> +}; >> + >> +#endif /* _XRT_AXIGATE_H_ */ >> diff --git a/drivers/fpga/xrt/lib/xleaf/axigate.c b/drivers/fpga/xrt/lib/xleaf/axigate.c >> new file mode 100644 >> index 000000000000..382969f9925f >> --- /dev/null >> +++ b/drivers/fpga/xrt/lib/xleaf/axigate.c >> @@ -0,0 +1,298 @@ >> +// SPDX-License-Identifier: GPL-2.0 >> +/* >> + * Xilinx Alveo FPGA AXI Gate Driver >> + * >> + * Copyright (C) 2020-2021 Xilinx, Inc. >> + * >> + * Authors: >> + * Lizhi Hou<Lizhi.Hou@xilinx.com> >> + */ >> + >> +#include <linux/mod_devicetable.h> >> +#include <linux/platform_device.h> >> +#include <linux/delay.h> >> +#include <linux/device.h> >> +#include <linux/io.h> >> +#include "metadata.h" >> +#include "xleaf.h" >> +#include "xleaf/axigate.h" >> + >> +#define XRT_AXIGATE "xrt_axigate" >> + >> +struct axigate_regs { >> + u32 iag_wr; >> + u32 iag_rvsd; >> + u32 iag_rd; >> +} __packed; > Just make them #defines, even more so if there are only 3 of them. We will use #define and regmap. >> + >> +struct xrt_axigate { >> + struct platform_device *pdev; >> + void *base; >> + struct mutex gate_lock; /* gate dev lock */ >> + >> + void *evt_hdl; >> + const char *ep_name; >> + >> + bool gate_freezed; >> +}; >> + >> +/* the ep names are in the order of hardware layers */ >> +static const char * const xrt_axigate_epnames[] = { >> + XRT_MD_NODE_GATE_PLP, >> + XRT_MD_NODE_GATE_ULP, >> + NULL >> +}; >> + >> +#define reg_rd(g, r) \ >> + ioread32((void *)(g)->base + offsetof(struct axigate_regs, r)) >> +#define reg_wr(g, v, r) \ >> + iowrite32(v, (void *)(g)->base + offsetof(struct axigate_regs, r)) >> + >> +static inline void freeze_gate(struct xrt_axigate *gate) >> +{ >> + reg_wr(gate, 0, iag_wr); >> + ndelay(500); >> + reg_rd(gate, iag_rd); >> +} >> + >> +static inline void free_gate(struct xrt_axigate *gate) >> +{ >> + reg_wr(gate, 0x2, iag_wr); >> + ndelay(500); > Magic constants? Will use #define for 500 >> + (void)reg_rd(gate, iag_rd); > At the very least add a comment on why? Is this for PCI synchronization > reasons? Will add comment. Some old board requires this extra read and it will not hurt performance. > >> + reg_wr(gate, 0x3, iag_wr); >> + ndelay(500); > Magic constants? >> + reg_rd(gate, iag_rd); > Does it nead a (void) or not? Be consistent, again, why do we read here > at all? >> +} >> + >> +static int xrt_axigate_epname_idx(struct platform_device *pdev) >> +{ >> + int i; >> + int ret; >> + struct resource *res; > Nope. Indents: > > struct resource *res; > int, i, ret; Will change this. > >> + >> + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); >> + if (!res) { >> + xrt_err(pdev, "Empty Resource!"); >> + return -EINVAL; >> + } >> + >> + for (i = 0; xrt_axigate_epnames[i]; i++) { >> + ret = strncmp(xrt_axigate_epnames[i], res->name, >> + strlen(xrt_axigate_epnames[i]) + 1); >> + if (!ret) >> + break; >> + } >> + >> + ret = (xrt_axigate_epnames[i]) ? i : -EINVAL; > Why not just: > > if (xrt_axigate_epnames[i]) > return i; > > return -EINVAL; Will change this. >> + return ret; >> +} >> + >> +static void xrt_axigate_freeze(struct platform_device *pdev) >> +{ >> + struct xrt_axigate *gate; >> + u32 freeze = 0; > Indents. Fix everywhere. Will fix this. >> + >> + gate = platform_get_drvdata(pdev); >> + >> + mutex_lock(&gate->gate_lock); >> + freeze = reg_rd(gate, iag_rd); >> + if (freeze) { /* gate is opened */ >> + xleaf_broadcast_event(pdev, XRT_EVENT_PRE_GATE_CLOSE, false); >> + freeze_gate(gate); >> + } >> + >> + gate->gate_freezed = true; > s/freezed/frozen Will change terms to open / close. >> + mutex_unlock(&gate->gate_lock); >> + >> + xrt_info(pdev, "freeze gate %s", gate->ep_name); > debug? axigate is a very critical part for programming FPGA. We hope to have an explicit printk to indicate the axigate open/close. >> +} >> + >> +static void xrt_axigate_free(struct platform_device *pdev) >> +{ >> + struct xrt_axigate *gate; >> + u32 freeze; >> + >> + gate = platform_get_drvdata(pdev); >> + >> + mutex_lock(&gate->gate_lock); >> + freeze = reg_rd(gate, iag_rd); >> + if (!freeze) { /* gate is closed */ >> + free_gate(gate); >> + xleaf_broadcast_event(pdev, XRT_EVENT_POST_GATE_OPEN, true); >> + /* xrt_axigate_free() could be called in event cb, thus >> + * we can not wait for the completes >> + */ >> + } >> + >> + gate->gate_freezed = false; >> + mutex_unlock(&gate->gate_lock); >> + >> + xrt_info(pdev, "free gate %s", gate->ep_name); >> +} >> + >> +static void xrt_axigate_event_cb(struct platform_device *pdev, void *arg) >> +{ >> + struct platform_device *leaf; >> + struct xrt_event *evt = (struct xrt_event *)arg; >> + enum xrt_events e = evt->xe_evt; >> + enum xrt_subdev_id id = evt->xe_subdev.xevt_subdev_id; >> + int instance = evt->xe_subdev.xevt_subdev_instance; >> + struct xrt_axigate *gate = platform_get_drvdata(pdev); >> + struct resource *res; > Reverse x-mas tree; > xxxxxxxxxx > xxxxxxxxx > xxxxxxxx > xxxxxx Will fix this. >> + >> + switch (e) { >> + case XRT_EVENT_POST_CREATION: >> + break; >> + default: >> + return; >> + } >> + >> + if (id != XRT_SUBDEV_AXIGATE) >> + return; >> + >> + leaf = xleaf_get_leaf_by_id(pdev, id, instance); >> + if (!leaf) >> + return; >> + >> + res = platform_get_resource(leaf, IORESOURCE_MEM, 0); >> + if (!res || !strncmp(res->name, gate->ep_name, strlen(res->name) + 1)) { >> + (void)xleaf_put_leaf(pdev, leaf); >> + return; >> + } >> + >> + /* >> + * higher level axigate instance created, >> + * make sure the gate is openned. This covers 1RP flow which >> + * has plp gate as well. >> + */ >> + if (xrt_axigate_epname_idx(leaf) > xrt_axigate_epname_idx(pdev)) >> + xrt_axigate_free(pdev); >> + else >> + xleaf_ioctl(leaf, XRT_AXIGATE_FREE, NULL); >> + >> + (void)xleaf_put_leaf(pdev, leaf); >> +} >> + >> +static int >> +xrt_axigate_leaf_ioctl(struct platform_device *pdev, u32 cmd, void *arg) >> +{ >> + switch (cmd) { >> + case XRT_XLEAF_EVENT: >> + xrt_axigate_event_cb(pdev, arg); >> + break; >> + case XRT_AXIGATE_FREEZE: >> + xrt_axigate_freeze(pdev); >> + break; >> + case XRT_AXIGATE_FREE: >> + xrt_axigate_free(pdev); >> + break; >> + default: >> + xrt_err(pdev, "unsupported cmd %d", cmd); >> + return -EINVAL; >> + } >> + >> + return 0; >> +} >> + >> +static int xrt_axigate_remove(struct platform_device *pdev) >> +{ >> + struct xrt_axigate *gate; >> + >> + gate = platform_get_drvdata(pdev); >> + >> + if (gate->base) >> + iounmap(gate->base); >> + >> + platform_set_drvdata(pdev, NULL); >> + devm_kfree(&pdev->dev, gate); > No! The point of using devres is so cleanup happens on removal. > While you're at it, if you move the ioremap to a devres version, this > function can basically go away entirely. Will fix this. >> + >> + return 0; >> +} >> + >> +static int xrt_axigate_probe(struct platform_device *pdev) >> +{ >> + struct xrt_axigate *gate; >> + struct resource *res; >> + int ret; >> + >> + gate = devm_kzalloc(&pdev->dev, sizeof(*gate), GFP_KERNEL); >> + if (!gate) >> + return -ENOMEM; >> + >> + gate->pdev = pdev; >> + platform_set_drvdata(pdev, gate); >> + >> + xrt_info(pdev, "probing..."); >> + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); >> + if (!res) { >> + xrt_err(pdev, "Empty resource 0"); >> + ret = -EINVAL; >> + goto failed; >> + } >> + >> + gate->base = ioremap(res->start, res->end - res->start + 1); >> + if (!gate->base) { >> + xrt_err(pdev, "map base iomem failed"); >> + ret = -EFAULT; >> + goto failed; >> + } >> + >> + gate->ep_name = res->name; >> + >> + mutex_init(&gate->gate_lock); >> + >> + return 0; >> + >> +failed: >> + xrt_axigate_remove(pdev); >> + return ret; >> +} >> + >> +static struct xrt_subdev_endpoints xrt_axigate_endpoints[] = { >> + { >> + .xse_names = (struct xrt_subdev_ep_names[]) { >> + { .ep_name = "ep_pr_isolate_ulp_00" }, >> + { NULL }, >> + }, >> + .xse_min_ep = 1, >> + }, >> + { >> + .xse_names = (struct xrt_subdev_ep_names[]) { >> + { .ep_name = "ep_pr_isolate_plp_00" }, >> + { NULL }, >> + }, >> + .xse_min_ep = 1, >> + }, >> + { 0 }, >> +}; >> + >> +static struct xrt_subdev_drvdata xrt_axigate_data = { >> + .xsd_dev_ops = { >> + .xsd_ioctl = xrt_axigate_leaf_ioctl, >> + }, >> +}; >> + >> +static const struct platform_device_id xrt_axigate_table[] = { >> + { XRT_AXIGATE, (kernel_ulong_t)&xrt_axigate_data }, >> + { }, >> +}; >> + >> +static struct platform_driver xrt_axigate_driver = { >> + .driver = { >> + .name = XRT_AXIGATE, >> + }, >> + .probe = xrt_axigate_probe, >> + .remove = xrt_axigate_remove, >> + .id_table = xrt_axigate_table, >> +}; >> + >> +void axigate_leaf_init_fini(bool init) >> +{ >> + if (init) { >> + xleaf_register_driver(XRT_SUBDEV_AXIGATE, >> + &xrt_axigate_driver, xrt_axigate_endpoints); >> + } else { >> + xleaf_unregister_driver(XRT_SUBDEV_AXIGATE); >> + } >> +} > This thing is duplicated in every file, maybe a macro would be an idea. Will define a macro. Thanks, Lizhi >> -- >> 2.18.4 >> > - Moritz
Hi Tom, On 03/03/2021 07:12 AM, Tom Rix wrote: > On 2/17/21 10:40 PM, Lizhi Hou wrote: >> Add ICAP driver. ICAP is a hardware function discovered by walking > What does ICAP stand for ? ICAP stands for Hardware Internal Configuration Access Port. I will add this. >> firmware metadata. A platform device node will be created for it. >> FPGA bitstream is written to hardware through ICAP. >> >> Signed-off-by: Sonal Santan <sonal.santan@xilinx.com> >> Signed-off-by: Max Zhen <max.zhen@xilinx.com> >> Signed-off-by: Lizhi Hou <lizhih@xilinx.com> >> --- >> drivers/fpga/xrt/include/xleaf/icap.h | 29 +++ >> drivers/fpga/xrt/lib/xleaf/icap.c | 317 ++++++++++++++++++++++++++ >> 2 files changed, 346 insertions(+) >> create mode 100644 drivers/fpga/xrt/include/xleaf/icap.h >> create mode 100644 drivers/fpga/xrt/lib/xleaf/icap.c >> >> diff --git a/drivers/fpga/xrt/include/xleaf/icap.h b/drivers/fpga/xrt/include/xleaf/icap.h >> new file mode 100644 >> index 000000000000..a14fc0ffa78f >> --- /dev/null >> +++ b/drivers/fpga/xrt/include/xleaf/icap.h >> @@ -0,0 +1,29 @@ >> +/* SPDX-License-Identifier: GPL-2.0 */ >> +/* >> + * Header file for XRT ICAP Leaf Driver >> + * >> + * Copyright (C) 2020-2021 Xilinx, Inc. >> + * >> + * Authors: >> + * Lizhi Hou <Lizhi.Hou@xilinx.com> >> + */ >> + >> +#ifndef _XRT_ICAP_H_ >> +#define _XRT_ICAP_H_ >> + >> +#include "xleaf.h" >> + >> +/* >> + * ICAP driver IOCTL calls. >> + */ >> +enum xrt_icap_ioctl_cmd { >> + XRT_ICAP_WRITE = XRT_XLEAF_CUSTOM_BASE, /* See comments in xleaf.h */ > maybe XRT_ICAP_GET_IDCODE Sure. >> + XRT_ICAP_IDCODE, >> +}; >> + >> +struct xrt_icap_ioctl_wr { >> + void *xiiw_bit_data; >> + u32 xiiw_data_len; >> +}; >> + >> +#endif /* _XRT_ICAP_H_ */ >> diff --git a/drivers/fpga/xrt/lib/xleaf/icap.c b/drivers/fpga/xrt/lib/xleaf/icap.c >> new file mode 100644 >> index 000000000000..0500a97bdef9 >> --- /dev/null >> +++ b/drivers/fpga/xrt/lib/xleaf/icap.c >> @@ -0,0 +1,317 @@ >> +// SPDX-License-Identifier: GPL-2.0 >> +/* >> + * Xilinx Alveo FPGA ICAP Driver >> + * >> + * Copyright (C) 2020-2021 Xilinx, Inc. >> + * >> + * Authors: >> + * Lizhi Hou<Lizhi.Hou@xilinx.com> >> + * Sonal Santan <sonals@xilinx.com> >> + * Max Zhen <maxz@xilinx.com> >> + */ >> + >> +#include <linux/mod_devicetable.h> >> +#include <linux/platform_device.h> >> +#include <linux/delay.h> >> +#include <linux/device.h> >> +#include <linux/io.h> >> +#include "metadata.h" >> +#include "xleaf.h" >> +#include "xleaf/icap.h" >> +#include "xclbin-helper.h" >> + >> +#define XRT_ICAP "xrt_icap" >> + >> +#define ICAP_ERR(icap, fmt, arg...) \ >> + xrt_err((icap)->pdev, fmt "\n", ##arg) >> +#define ICAP_WARN(icap, fmt, arg...) \ >> + xrt_warn((icap)->pdev, fmt "\n", ##arg) >> +#define ICAP_INFO(icap, fmt, arg...) \ >> + xrt_info((icap)->pdev, fmt "\n", ##arg) >> +#define ICAP_DBG(icap, fmt, arg...) \ >> + xrt_dbg((icap)->pdev, fmt "\n", ##arg) >> + >> +/* >> + * AXI-HWICAP IP register layout >> + */ >> +struct icap_reg { >> + u32 ir_rsvd1[7]; >> + u32 ir_gier; >> + u32 ir_isr; >> + u32 ir_rsvd2; >> + u32 ir_ier; >> + u32 ir_rsvd3[53]; >> + u32 ir_wf; >> + u32 ir_rf; >> + u32 ir_sz; >> + u32 ir_cr; >> + u32 ir_sr; >> + u32 ir_wfv; >> + u32 ir_rfo; >> + u32 ir_asr; >> +} __packed; >> + >> +struct icap { >> + struct platform_device *pdev; >> + struct icap_reg *icap_regs; >> + struct mutex icap_lock; /* icap dev lock */ >> + >> + unsigned int idcode; > returned as a 64 bit value, but could be stored as 32 bit Will change return to u32. >> +}; >> + >> +static inline u32 reg_rd(void __iomem *reg) >> +{ >> + if (!reg) >> + return -1; >> + >> + return ioread32(reg); > Look at converting the io access to using regmap* api Will change it. >> +} >> + >> +static inline void reg_wr(void __iomem *reg, u32 val) >> +{ >> + if (!reg) >> + return; >> + >> + iowrite32(val, reg); >> +} >> + >> +static int wait_for_done(struct icap *icap) >> +{ >> + u32 w; >> + int i = 0; >> + >> + WARN_ON(!mutex_is_locked(&icap->icap_lock)); > is this needed ? wait_for_done is only called in one place. Will remove it. >> + for (i = 0; i < 10; i++) { >> + udelay(5); > comment on delay. >> + w = reg_rd(&icap->icap_regs->ir_sr); >> + ICAP_INFO(icap, "XHWICAP_SR: %x", w); >> + if (w & 0x5) > 0x5 is a magic number, should be #defined Sure. >> + return 0; >> + } >> + >> + ICAP_ERR(icap, "bitstream download timeout"); >> + return -ETIMEDOUT; >> +} >> + >> +static int icap_write(struct icap *icap, const u32 *word_buf, int size) >> +{ >> + int i; >> + u32 value = 0; >> + >> + for (i = 0; i < size; i++) { >> + value = be32_to_cpu(word_buf[i]); >> + reg_wr(&icap->icap_regs->ir_wf, value); >> + } >> + >> + reg_wr(&icap->icap_regs->ir_cr, 0x1); >> + >> + for (i = 0; i < 20; i++) { >> + value = reg_rd(&icap->icap_regs->ir_cr); >> + if ((value & 0x1) == 0) >> + return 0; >> + ndelay(50); >> + } >> + >> + ICAP_ERR(icap, "writing %d dwords timeout", size); >> + return -EIO; >> +} >> + >> +static int bitstream_helper(struct icap *icap, const u32 *word_buffer, >> + u32 word_count) >> +{ >> + u32 remain_word; >> + u32 word_written = 0; >> + int wr_fifo_vacancy = 0; >> + int err = 0; >> + >> + WARN_ON(!mutex_is_locked(&icap->icap_lock)); >> + for (remain_word = word_count; remain_word > 0; >> + remain_word -= word_written, word_buffer += word_written) { >> + wr_fifo_vacancy = reg_rd(&icap->icap_regs->ir_wfv); >> + if (wr_fifo_vacancy <= 0) { >> + ICAP_ERR(icap, "no vacancy: %d", wr_fifo_vacancy); >> + err = -EIO; >> + break; >> + } >> + word_written = (wr_fifo_vacancy < remain_word) ? >> + wr_fifo_vacancy : remain_word; >> + if (icap_write(icap, word_buffer, word_written) != 0) { >> + ICAP_ERR(icap, "write failed remain %d, written %d", >> + remain_word, word_written); >> + err = -EIO; >> + break; >> + } >> + } >> + >> + return err; >> +} >> + >> +static int icap_download(struct icap *icap, const char *buffer, >> + unsigned long length) >> +{ >> + u32 num_chars_read = DMA_HWICAP_BITFILE_BUFFER_SIZE; >> + u32 byte_read; >> + int err = 0; >> + >> + mutex_lock(&icap->icap_lock); >> + for (byte_read = 0; byte_read < length; byte_read += num_chars_read) { >> + num_chars_read = length - byte_read; >> + if (num_chars_read > DMA_HWICAP_BITFILE_BUFFER_SIZE) >> + num_chars_read = DMA_HWICAP_BITFILE_BUFFER_SIZE; >> + >> + err = bitstream_helper(icap, (u32 *)buffer, num_chars_read / sizeof(u32)); > assumption that num_chars_read % 4 == 0 > > Add a check, or handle. Sure. > >> + if (err) >> + goto failed; >> + buffer += num_chars_read; >> + } >> + >> + err = wait_for_done(icap); > timeout is not handled >> + >> +failed: >> + mutex_unlock(&icap->icap_lock); >> + >> + return err; >> +} >> + >> +/* >> + * Run the following sequence of canned commands to obtain IDCODE of the FPGA >> + */ >> +static void icap_probe_chip(struct icap *icap) >> +{ >> + u32 w; > De magic this. > > If this is a documented startup sequence, please add a link to the document. > > Else add a comment about what you are doing here. > > Where possible, convert the hex values to #defines. Will add comment for this. Thanks, Lizhi > > Tom > >> + >> + w = reg_rd(&icap->icap_regs->ir_sr); >> + w = reg_rd(&icap->icap_regs->ir_sr); >> + reg_wr(&icap->icap_regs->ir_gier, 0x0); >> + w = reg_rd(&icap->icap_regs->ir_wfv); >> + reg_wr(&icap->icap_regs->ir_wf, 0xffffffff); >> + reg_wr(&icap->icap_regs->ir_wf, 0xaa995566); >> + reg_wr(&icap->icap_regs->ir_wf, 0x20000000); >> + reg_wr(&icap->icap_regs->ir_wf, 0x20000000); >> + reg_wr(&icap->icap_regs->ir_wf, 0x28018001); >> + reg_wr(&icap->icap_regs->ir_wf, 0x20000000); >> + reg_wr(&icap->icap_regs->ir_wf, 0x20000000); >> + w = reg_rd(&icap->icap_regs->ir_cr); >> + reg_wr(&icap->icap_regs->ir_cr, 0x1); >> + w = reg_rd(&icap->icap_regs->ir_cr); >> + w = reg_rd(&icap->icap_regs->ir_cr); >> + w = reg_rd(&icap->icap_regs->ir_sr); >> + w = reg_rd(&icap->icap_regs->ir_cr); >> + w = reg_rd(&icap->icap_regs->ir_sr); >> + reg_wr(&icap->icap_regs->ir_sz, 0x1); >> + w = reg_rd(&icap->icap_regs->ir_cr); >> + reg_wr(&icap->icap_regs->ir_cr, 0x2); >> + w = reg_rd(&icap->icap_regs->ir_rfo); >> + icap->idcode = reg_rd(&icap->icap_regs->ir_rf); >> + w = reg_rd(&icap->icap_regs->ir_cr); >> + (void)w; >> +} >> + >> +static int >> +xrt_icap_leaf_ioctl(struct platform_device *pdev, u32 cmd, void *arg) >> +{ >> + struct xrt_icap_ioctl_wr *wr_arg = arg; >> + struct icap *icap; >> + int ret = 0; >> + >> + icap = platform_get_drvdata(pdev); >> + >> + switch (cmd) { >> + case XRT_XLEAF_EVENT: >> + /* Does not handle any event. */ >> + break; >> + case XRT_ICAP_WRITE: >> + ret = icap_download(icap, wr_arg->xiiw_bit_data, >> + wr_arg->xiiw_data_len); >> + break; >> + case XRT_ICAP_IDCODE: >> + *(u64 *)arg = icap->idcode; >> + break; >> + default: >> + ICAP_ERR(icap, "unknown command %d", cmd); >> + return -EINVAL; >> + } >> + >> + return ret; >> +} >> + >> +static int xrt_icap_remove(struct platform_device *pdev) >> +{ >> + struct icap *icap; >> + >> + icap = platform_get_drvdata(pdev); >> + >> + platform_set_drvdata(pdev, NULL); >> + devm_kfree(&pdev->dev, icap); >> + >> + return 0; >> +} >> + >> +static int xrt_icap_probe(struct platform_device *pdev) >> +{ >> + struct icap *icap; >> + int ret = 0; >> + struct resource *res; >> + >> + icap = devm_kzalloc(&pdev->dev, sizeof(*icap), GFP_KERNEL); >> + if (!icap) >> + return -ENOMEM; >> + >> + icap->pdev = pdev; >> + platform_set_drvdata(pdev, icap); >> + mutex_init(&icap->icap_lock); >> + >> + xrt_info(pdev, "probing"); >> + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); >> + if (res) { >> + icap->icap_regs = ioremap(res->start, res->end - res->start + 1); >> + if (!icap->icap_regs) { >> + xrt_err(pdev, "map base failed %pR", res); >> + ret = -EIO; >> + goto failed; >> + } >> + } >> + >> + icap_probe_chip(icap); >> +failed: >> + return ret; >> +} >> + >> +static struct xrt_subdev_endpoints xrt_icap_endpoints[] = { >> + { >> + .xse_names = (struct xrt_subdev_ep_names[]) { >> + { .ep_name = XRT_MD_NODE_FPGA_CONFIG }, >> + { NULL }, >> + }, >> + .xse_min_ep = 1, >> + }, >> + { 0 }, >> +}; >> + >> +static struct xrt_subdev_drvdata xrt_icap_data = { >> + .xsd_dev_ops = { >> + .xsd_ioctl = xrt_icap_leaf_ioctl, >> + }, >> +}; >> + >> +static const struct platform_device_id xrt_icap_table[] = { >> + { XRT_ICAP, (kernel_ulong_t)&xrt_icap_data }, >> + { }, >> +}; >> + >> +static struct platform_driver xrt_icap_driver = { >> + .driver = { >> + .name = XRT_ICAP, >> + }, >> + .probe = xrt_icap_probe, >> + .remove = xrt_icap_remove, >> + .id_table = xrt_icap_table, >> +}; >> + >> +void icap_leaf_init_fini(bool init) >> +{ >> + if (init) >> + xleaf_register_driver(XRT_SUBDEV_ICAP, &xrt_icap_driver, xrt_icap_endpoints); >> + else >> + xleaf_unregister_driver(XRT_SUBDEV_ICAP); >> +}