| Message ID | 20210519143700.27392-1-bhupesh.sharma@linaro.org |
|---|---|
| Headers | show |
| Series | Enable Qualcomm Crypto Engine on sm8250 | expand |
On Wed, May 19, 2021 at 08:06:47PM +0530, Bhupesh Sharma wrote: > Convert Qualcomm QCE crypto devicetree binding to YAML. > > Cc: Thara Gopinath <thara.gopinath@linaro.org> > Cc: Bjorn Andersson <bjorn.andersson@linaro.org> > Cc: Rob Herring <robh+dt@kernel.org> > Cc: Andy Gross <agross@kernel.org> > Cc: Herbert Xu <herbert@gondor.apana.org.au> > Cc: David S. Miller <davem@davemloft.net> > Cc: Stephen Boyd <sboyd@kernel.org> > Cc: Michael Turquette <mturquette@baylibre.com> > Cc: Vinod Koul <vkoul@kernel.org> > Cc: dmaengine@vger.kernel.org > Cc: linux-clk@vger.kernel.org > Cc: linux-crypto@vger.kernel.org > Cc: devicetree@vger.kernel.org > Cc: linux-kernel@vger.kernel.org > Cc: bhupesh.linux@gmail.com > Signed-off-by: Bhupesh Sharma <bhupesh.sharma@linaro.org> > --- > .../devicetree/bindings/crypto/qcom-qce.txt | 25 ------- > .../devicetree/bindings/crypto/qcom-qce.yaml | 69 +++++++++++++++++++ > 2 files changed, 69 insertions(+), 25 deletions(-) > delete mode 100644 Documentation/devicetree/bindings/crypto/qcom-qce.txt > create mode 100644 Documentation/devicetree/bindings/crypto/qcom-qce.yaml > > diff --git a/Documentation/devicetree/bindings/crypto/qcom-qce.txt b/Documentation/devicetree/bindings/crypto/qcom-qce.txt > deleted file mode 100644 > index fdd53b184ba8..000000000000 > --- a/Documentation/devicetree/bindings/crypto/qcom-qce.txt > +++ /dev/null > @@ -1,25 +0,0 @@ > -Qualcomm crypto engine driver > - > -Required properties: > - > -- compatible : should be "qcom,crypto-v5.1" > -- reg : specifies base physical address and size of the registers map > -- clocks : phandle to clock-controller plus clock-specifier pair > -- clock-names : "iface" clocks register interface > - "bus" clocks data transfer interface > - "core" clocks rest of the crypto block > -- dmas : DMA specifiers for tx and rx dma channels. For more see > - Documentation/devicetree/bindings/dma/dma.txt > -- dma-names : DMA request names should be "rx" and "tx" > - > -Example: > - crypto@fd45a000 { > - compatible = "qcom,crypto-v5.1"; > - reg = <0xfd45a000 0x6000>; > - clocks = <&gcc GCC_CE2_AHB_CLK>, > - <&gcc GCC_CE2_AXI_CLK>, > - <&gcc GCC_CE2_CLK>; > - clock-names = "iface", "bus", "core"; > - dmas = <&cryptobam 2>, <&cryptobam 3>; > - dma-names = "rx", "tx"; > - }; > diff --git a/Documentation/devicetree/bindings/crypto/qcom-qce.yaml b/Documentation/devicetree/bindings/crypto/qcom-qce.yaml > new file mode 100644 > index 000000000000..a691cd08f372 > --- /dev/null > +++ b/Documentation/devicetree/bindings/crypto/qcom-qce.yaml > @@ -0,0 +1,69 @@ > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) > +%YAML 1.2 > +--- > +$id: http://devicetree.org/schemas/crypto/qcom-qce.yaml# > +$schema: http://devicetree.org/meta-schemas/core.yaml# > + > +title: Qualcomm crypto engine driver > + > +maintainers: > + - Bhupesh Sharma <bhupesh.sharma@linaro.org> > + > +description: | > + This document defines the binding for the QCE crypto > + controller found on Qualcomm parts. > + > +properties: > + compatible: > + const: qcom,crypto-v5.1 > + > + reg: > + maxItems: 1 > + description: | > + Specifies base physical address and size of the registers map. Yep, that's every 'reg'. Drop. With that dropped, Reviewed-by: Rob Herring <robh@kernel.org> > + > + clocks: > + items: > + - description: iface clocks register interface. > + - description: bus clocks data transfer interface. > + - description: core clocks rest of the crypto block. > + > + clock-names: > + items: > + - const: iface > + - const: bus > + - const: core > + > + dmas: > + items: > + - description: DMA specifiers for tx dma channel. > + - description: DMA specifiers for rx dma channel. > + > + dma-names: > + items: > + - const: rx > + - const: tx > + > +required: > + - compatible > + - reg > + - clocks > + - clock-names > + - dmas > + - dma-names > + > +additionalProperties: false > + > +examples: > + - | > + #include <dt-bindings/clock/qcom,gcc-apq8084.h> > + crypto-engine@fd45a000 { > + compatible = "qcom,crypto-v5.1"; > + reg = <0xfd45a000 0x6000>; > + clocks = <&gcc GCC_CE2_AHB_CLK>, > + <&gcc GCC_CE2_AXI_CLK>, > + <&gcc GCC_CE2_CLK>; > + clock-names = "iface", "bus", "core"; > + dmas = <&cryptobam 2>, <&cryptobam 3>; > + dma-names = "rx", "tx"; > + }; > -- > 2.31.1 >
On 5/19/21 10:36 AM, Bhupesh Sharma wrote: > Print a failure message (dev_err) in case the qcom qce crypto > driver probe() fails. > > Cc: Thara Gopinath <thara.gopinath@linaro.org> > Cc: Bjorn Andersson <bjorn.andersson@linaro.org> > Cc: Rob Herring <robh+dt@kernel.org> > Cc: Andy Gross <agross@kernel.org> > Cc: Herbert Xu <herbert@gondor.apana.org.au> > Cc: David S. Miller <davem@davemloft.net> > Cc: Stephen Boyd <sboyd@kernel.org> > Cc: Michael Turquette <mturquette@baylibre.com> > Cc: Vinod Koul <vkoul@kernel.org> > Cc: dmaengine@vger.kernel.org > Cc: linux-clk@vger.kernel.org > Cc: linux-crypto@vger.kernel.org > Cc: devicetree@vger.kernel.org > Cc: linux-kernel@vger.kernel.org > Cc: bhupesh.linux@gmail.com > Signed-off-by: Bhupesh Sharma <bhupesh.sharma@linaro.org> I kind of felt you can club patch 14 and 15. But it is upto you.. FWIW, Reviewed-by: Thara Gopinath <thara.gopinath@linaro.org> Warm Regards Thara > --- > drivers/crypto/qce/core.c | 1 + > 1 file changed, 1 insertion(+) > > diff --git a/drivers/crypto/qce/core.c b/drivers/crypto/qce/core.c > index 8c3c68ba579e..aecb2cdd79e5 100644 > --- a/drivers/crypto/qce/core.c > +++ b/drivers/crypto/qce/core.c > @@ -300,6 +300,7 @@ static int qce_crypto_probe(struct platform_device *pdev) > err_clks_core: > clk_disable_unprepare(qce->core); > err_out: > + dev_err(dev, "%s failed : %d\n", __func__, ret); > return ret; > } > >
On 5/19/21 10:36 AM, Bhupesh Sharma wrote: > Since the Qualcomm qce crypto driver needs the BAM dma driver to be > setup first (to allow crypto operations), it makes sense to defer > the qce crypto driver probing in case the BAM dma driver is not yet > probed. > > Move the code leg requesting dma channels earlier in the > probe() flow. This fixes the qce probe failure issues when both qce > and BMA dma are compiled as static part of the kernel. So, I do not understand what issue you faced with the current code ordering. When bam dma is not initialized, qce_dma_request will fail and rest the error path kicks in. To me the correct ordering for enabling a driver is to turn on clocks and interconnect before requesting for dma. Unless, there is a specific issue, I will ask for that order to be maintained. Warm Regards Thara > > Cc: Thara Gopinath <thara.gopinath@linaro.org> > Cc: Bjorn Andersson <bjorn.andersson@linaro.org> > Cc: Rob Herring <robh+dt@kernel.org> > Cc: Andy Gross <agross@kernel.org> > Cc: Herbert Xu <herbert@gondor.apana.org.au> > Cc: David S. Miller <davem@davemloft.net> > Cc: Stephen Boyd <sboyd@kernel.org> > Cc: Michael Turquette <mturquette@baylibre.com> > Cc: Vinod Koul <vkoul@kernel.org> > Cc: dmaengine@vger.kernel.org > Cc: linux-clk@vger.kernel.org > Cc: linux-crypto@vger.kernel.org > Cc: devicetree@vger.kernel.org > Cc: linux-kernel@vger.kernel.org > Cc: bhupesh.linux@gmail.com > Signed-off-by: Bhupesh Sharma <bhupesh.sharma@linaro.org> > --- > drivers/crypto/qce/core.c | 16 +++++++++------- > 1 file changed, 9 insertions(+), 7 deletions(-) > > diff --git a/drivers/crypto/qce/core.c b/drivers/crypto/qce/core.c > index 8b3e2b4580c2..207221d5b996 100644 > --- a/drivers/crypto/qce/core.c > +++ b/drivers/crypto/qce/core.c > @@ -218,6 +218,14 @@ static int qce_crypto_probe(struct platform_device *pdev) > if (ret < 0) > goto err_out; > > + /* qce driver requires BAM dma driver to be setup first. > + * In case the dma channel are not set yet, this check > + * helps use to return -EPROBE_DEFER earlier. > + */ > + ret = qce_dma_request(qce->dev, &qce->dma); > + if (ret) > + return ret; > + > qce->mem_path = devm_of_icc_get(qce->dev, "memory"); > if (IS_ERR(qce->mem_path)) > return dev_err_probe(dev, PTR_ERR(qce->mem_path), > @@ -269,10 +277,6 @@ static int qce_crypto_probe(struct platform_device *pdev) > goto err_clks_iface; > } > > - ret = qce_dma_request(qce->dev, &qce->dma); > - if (ret) > - goto err_clks; > - > ret = qce_check_version(qce); > if (ret) > goto err_clks; > @@ -287,12 +291,10 @@ static int qce_crypto_probe(struct platform_device *pdev) > > ret = qce_register_algs(qce); > if (ret) > - goto err_dma; > + goto err_clks; > > return 0; > > -err_dma: > - qce_dma_release(&qce->dma); > err_clks: > clk_disable_unprepare(qce->bus); > err_clks_iface: >
Hi Stephen, On Wed, 2 Jun 2021 at 12:54, Stephen Boyd <sboyd@kernel.org> wrote: > > Quoting Bhupesh Sharma (2021-05-19 07:36:43) > > > > Cc: Thara Gopinath <thara.gopinath@linaro.org> > > Cc: Bjorn Andersson <bjorn.andersson@linaro.org> > > Cc: Rob Herring <robh+dt@kernel.org> > > Cc: Andy Gross <agross@kernel.org> > > Cc: Herbert Xu <herbert@gondor.apana.org.au> > > Cc: David S. Miller <davem@davemloft.net> > > Cc: Stephen Boyd <sboyd@kernel.org> > > Cc: Michael Turquette <mturquette@baylibre.com> > > Cc: Vinod Koul <vkoul@kernel.org> > > Cc: dmaengine@vger.kernel.org > > Cc: linux-clk@vger.kernel.org > > Can you stop Cc-ing the clk list? It puts it into my review queue when > as far as I can tell there isn't anything really clk related to review > here. Or do you need an ack on something? Sure, I will drop the clk-list from Cc-list of future patchset versions. Since I had a couple of clk driver changes in v1 which were dropped starting from v2, I thought it would be good to Cc clk-list for v2 (and so on..) Thanks, Bhupesh
Hi Rob, On Fri, 21 May 2021 at 07:15, Rob Herring <robh@kernel.org> wrote: > > On Wed, May 19, 2021 at 08:06:47PM +0530, Bhupesh Sharma wrote: > > Convert Qualcomm QCE crypto devicetree binding to YAML. > > > > Cc: Thara Gopinath <thara.gopinath@linaro.org> > > Cc: Bjorn Andersson <bjorn.andersson@linaro.org> > > Cc: Rob Herring <robh+dt@kernel.org> > > Cc: Andy Gross <agross@kernel.org> > > Cc: Herbert Xu <herbert@gondor.apana.org.au> > > Cc: David S. Miller <davem@davemloft.net> > > Cc: Stephen Boyd <sboyd@kernel.org> > > Cc: Michael Turquette <mturquette@baylibre.com> > > Cc: Vinod Koul <vkoul@kernel.org> > > Cc: dmaengine@vger.kernel.org > > Cc: linux-clk@vger.kernel.org > > Cc: linux-crypto@vger.kernel.org > > Cc: devicetree@vger.kernel.org > > Cc: linux-kernel@vger.kernel.org > > Cc: bhupesh.linux@gmail.com > > Signed-off-by: Bhupesh Sharma <bhupesh.sharma@linaro.org> > > --- > > .../devicetree/bindings/crypto/qcom-qce.txt | 25 ------- > > .../devicetree/bindings/crypto/qcom-qce.yaml | 69 +++++++++++++++++++ > > 2 files changed, 69 insertions(+), 25 deletions(-) > > delete mode 100644 Documentation/devicetree/bindings/crypto/qcom-qce.txt > > create mode 100644 Documentation/devicetree/bindings/crypto/qcom-qce.yaml > > > > diff --git a/Documentation/devicetree/bindings/crypto/qcom-qce.txt b/Documentation/devicetree/bindings/crypto/qcom-qce.txt > > deleted file mode 100644 > > index fdd53b184ba8..000000000000 > > --- a/Documentation/devicetree/bindings/crypto/qcom-qce.txt > > +++ /dev/null > > @@ -1,25 +0,0 @@ > > -Qualcomm crypto engine driver > > - > > -Required properties: > > - > > -- compatible : should be "qcom,crypto-v5.1" > > -- reg : specifies base physical address and size of the registers map > > -- clocks : phandle to clock-controller plus clock-specifier pair > > -- clock-names : "iface" clocks register interface > > - "bus" clocks data transfer interface > > - "core" clocks rest of the crypto block > > -- dmas : DMA specifiers for tx and rx dma channels. For more see > > - Documentation/devicetree/bindings/dma/dma.txt > > -- dma-names : DMA request names should be "rx" and "tx" > > - > > -Example: > > - crypto@fd45a000 { > > - compatible = "qcom,crypto-v5.1"; > > - reg = <0xfd45a000 0x6000>; > > - clocks = <&gcc GCC_CE2_AHB_CLK>, > > - <&gcc GCC_CE2_AXI_CLK>, > > - <&gcc GCC_CE2_CLK>; > > - clock-names = "iface", "bus", "core"; > > - dmas = <&cryptobam 2>, <&cryptobam 3>; > > - dma-names = "rx", "tx"; > > - }; > > diff --git a/Documentation/devicetree/bindings/crypto/qcom-qce.yaml b/Documentation/devicetree/bindings/crypto/qcom-qce.yaml > > new file mode 100644 > > index 000000000000..a691cd08f372 > > --- /dev/null > > +++ b/Documentation/devicetree/bindings/crypto/qcom-qce.yaml > > @@ -0,0 +1,69 @@ > > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) > > +%YAML 1.2 > > +--- > > +$id: http://devicetree.org/schemas/crypto/qcom-qce.yaml# > > +$schema: http://devicetree.org/meta-schemas/core.yaml# > > + > > +title: Qualcomm crypto engine driver > > + > > +maintainers: > > + - Bhupesh Sharma <bhupesh.sharma@linaro.org> > > + > > +description: | > > + This document defines the binding for the QCE crypto > > + controller found on Qualcomm parts. > > + > > +properties: > > + compatible: > > + const: qcom,crypto-v5.1 > > + > > + reg: > > + maxItems: 1 > > + description: | > > + Specifies base physical address and size of the registers map. > > Yep, that's every 'reg'. Drop. > > With that dropped, > > Reviewed-by: Rob Herring <robh@kernel.org> Ok, I will drop this in v4. Thanks, Bhupesh > > + > > + clocks: > > + items: > > + - description: iface clocks register interface. > > + - description: bus clocks data transfer interface. > > + - description: core clocks rest of the crypto block. > > + > > + clock-names: > > + items: > > + - const: iface > > + - const: bus > > + - const: core > > + > > + dmas: > > + items: > > + - description: DMA specifiers for tx dma channel. > > + - description: DMA specifiers for rx dma channel. > > + > > + dma-names: > > + items: > > + - const: rx > > + - const: tx > > + > > +required: > > + - compatible > > + - reg > > + - clocks > > + - clock-names > > + - dmas > > + - dma-names > > + > > +additionalProperties: false > > + > > +examples: > > + - | > > + #include <dt-bindings/clock/qcom,gcc-apq8084.h> > > + crypto-engine@fd45a000 { > > + compatible = "qcom,crypto-v5.1"; > > + reg = <0xfd45a000 0x6000>; > > + clocks = <&gcc GCC_CE2_AHB_CLK>, > > + <&gcc GCC_CE2_AXI_CLK>, > > + <&gcc GCC_CE2_CLK>; > > + clock-names = "iface", "bus", "core"; > > + dmas = <&cryptobam 2>, <&cryptobam 3>; > > + dma-names = "rx", "tx"; > > + }; > > -- > > 2.31.1 > >
Hi Thara, Thanks for the review and sorry for the late reply. On Fri, 21 May 2021 at 07:27, Thara Gopinath <thara.gopinath@linaro.org> wrote: > > > > On 5/19/21 10:36 AM, Bhupesh Sharma wrote: > > Since the Qualcomm qce crypto driver needs the BAM dma driver to be > > setup first (to allow crypto operations), it makes sense to defer > > the qce crypto driver probing in case the BAM dma driver is not yet > > probed. > > > > Move the code leg requesting dma channels earlier in the > > probe() flow. This fixes the qce probe failure issues when both qce > > and BMA dma are compiled as static part of the kernel. > > So, I do not understand what issue you faced with the current code > ordering. When bam dma is not initialized, qce_dma_request will fail and > rest the error path kicks in. > To me the correct ordering for enabling a driver is to turn on clocks > and interconnect before requesting for dma. Unless, there is a specific > issue, I will ask for that order to be maintained. Sure. The problem I faced was the following. Let's consider the scenario where while the qce crypto driver and the interconnect are compiled as static parts of the kernel, the bam DMA driver is compiled as a module, then the -EPROBE_DEFER return leg from the qce crypto driver is very late in the probe() flow, as we first turn on the clocks and then the interconnect. Now the suggested linux deferred probe implementation is to return as early from the caling driver in case the called driver (subdev) is not yet ready. SInce the qce crypto driver requires the bam DMA to be set up first, it makes sense to move 'qce_dma_request' early in the boot flow. If it's not yet probed(), it probably doesn't make sense to set up the clks and interconnects yet in the qce driver. We can do it later when the bam DMA is setup. I have tested the following combinations with the change I made in this patchset: 1. qce - static, bam - module, interconnect - module -> qce_dma_request returned -EPROBE_DEFER 2. qce - static, bam - module, interconnect - static -> qce_dma_request returned -EPROBE_DEFER 3. qce - static, bam - static, interconnect - module -> qce_dma_request returned -EPROBE_DEFER 4. qce - static, bam - static, interconnect - static -> no -EPROBE_DEFER Thanks, Bhupesh > > Cc: Thara Gopinath <thara.gopinath@linaro.org> > > Cc: Bjorn Andersson <bjorn.andersson@linaro.org> > > Cc: Rob Herring <robh+dt@kernel.org> > > Cc: Andy Gross <agross@kernel.org> > > Cc: Herbert Xu <herbert@gondor.apana.org.au> > > Cc: David S. Miller <davem@davemloft.net> > > Cc: Stephen Boyd <sboyd@kernel.org> > > Cc: Michael Turquette <mturquette@baylibre.com> > > Cc: Vinod Koul <vkoul@kernel.org> > > Cc: dmaengine@vger.kernel.org > > Cc: linux-clk@vger.kernel.org > > Cc: linux-crypto@vger.kernel.org > > Cc: devicetree@vger.kernel.org > > Cc: linux-kernel@vger.kernel.org > > Cc: bhupesh.linux@gmail.com > > Signed-off-by: Bhupesh Sharma <bhupesh.sharma@linaro.org> > > --- > > drivers/crypto/qce/core.c | 16 +++++++++------- > > 1 file changed, 9 insertions(+), 7 deletions(-) > > > > diff --git a/drivers/crypto/qce/core.c b/drivers/crypto/qce/core.c > > index 8b3e2b4580c2..207221d5b996 100644 > > --- a/drivers/crypto/qce/core.c > > +++ b/drivers/crypto/qce/core.c > > @@ -218,6 +218,14 @@ static int qce_crypto_probe(struct platform_device *pdev) > > if (ret < 0) > > goto err_out; > > > > + /* qce driver requires BAM dma driver to be setup first. > > + * In case the dma channel are not set yet, this check > > + * helps use to return -EPROBE_DEFER earlier. > > + */ > > + ret = qce_dma_request(qce->dev, &qce->dma); > > + if (ret) > > + return ret; > > + > > qce->mem_path = devm_of_icc_get(qce->dev, "memory"); > > if (IS_ERR(qce->mem_path)) > > return dev_err_probe(dev, PTR_ERR(qce->mem_path), > > @@ -269,10 +277,6 @@ static int qce_crypto_probe(struct platform_device *pdev) > > goto err_clks_iface; > > } > > > > - ret = qce_dma_request(qce->dev, &qce->dma); > > - if (ret) > > - goto err_clks; > > - > > ret = qce_check_version(qce); > > if (ret) > > goto err_clks; > > @@ -287,12 +291,10 @@ static int qce_crypto_probe(struct platform_device *pdev) > > > > ret = qce_register_algs(qce); > > if (ret) > > - goto err_dma; > > + goto err_clks; > > > > return 0; > > > > -err_dma: > > - qce_dma_release(&qce->dma); > > err_clks: > > clk_disable_unprepare(qce->bus); > > err_clks_iface: > > > >
Changes since v2: ================= - v2 can be seen here: https://lore.kernel.org/dmaengine/20210505213731.538612-1-bhupesh.sharma@linaro.org/ - Drop a couple of patches from v1, which tried to address the defered probing of qce driver in case bam dma driver is not yet probed. Replace it instead with a single (simpler) patch [PATCH 16/17]. - Convert bam dma and qce crypto dt-bindings to YAML. - Addressed review comments from Thara, Bjorn, Vinod and Rob. Changes since v1: ================= - v1 can be seen here: https://lore.kernel.org/linux-arm-msm/20210310052503.3618486-1-bhupesh.sharma@linaro.org/ - v1 did not work well as reported earlier by Dmitry, so v2 contains the following changes/fixes: ~ Enable the interconnect path b/w BAM DMA and main memory first before trying to access the BAM DMA registers. ~ Enable the interconnect path b/w qce crytpo and main memory first before trying to access the qce crypto registers. ~ Make sure to document the required and optional properties for both BAM DMA and qce crypto drivers. ~ Add a few debug related print messages in case the qce crypto driver passes or fails to probe. ~ Convert the qce crypto driver probe to a defered one in case the BAM DMA or the interconnect driver(s) (needed on specific Qualcomm parts) are not yet probed. Qualcomm crypto engine is also available on sm8250 SoC. It supports hardware accelerated algorithms for encryption and authentication. It also provides support for aes, des, 3des encryption algorithms and sha1, sha256, hmac(sha1), hmac(sha256) authentication algorithms. Tested the enabled crypto algorithms with cryptsetup test utilities on sm8250-mtp and RB5 board (see [1]) and also with crypto self-tests, including the fuzz tests (CONFIG_CRYPTO_MANAGER_EXTRA_TESTS=y). While at it, also make a minor fix in 'sdm845.dtsi', to make sure it confirms with the other .dtsi files which expose crypto nodes on qcom SoCs. Note that this series is rebased on AEAD fixes from Thara (see [2]). This is required for all of the fuzz tests to work. [1]. https://linux.die.net/man/8/cryptsetup [2]. https://lore.kernel.org/linux-crypto/20210429150707.3168383-5-thara.gopinath@linaro.org/T/ Cc: Thara Gopinath <thara.gopinath@linaro.org> Cc: Bjorn Andersson <bjorn.andersson@linaro.org> Cc: Rob Herring <robh+dt@kernel.org> Cc: Andy Gross <agross@kernel.org> Cc: Herbert Xu <herbert@gondor.apana.org.au> Cc: David S. Miller <davem@davemloft.net> Cc: Stephen Boyd <sboyd@kernel.org> Cc: Michael Turquette <mturquette@baylibre.com> Cc: Vinod Koul <vkoul@kernel.org> Cc: dmaengine@vger.kernel.org Cc: linux-clk@vger.kernel.org Cc: linux-crypto@vger.kernel.org Cc: devicetree@vger.kernel.org Cc: linux-kernel@vger.kernel.org Cc: bhupesh.linux@gmail.com Bhupesh Sharma (14): dt-bindings: qcom-bam: Convert binding to YAML dt-bindings: qcom-bam: Add 'interconnects' & 'interconnect-names' to optional properties dt-bindings: qcom-bam: Add 'iommus' to required properties dt-bindings: qcom-qce: Convert bindings to yaml dt-bindings: qcom-qce: Add 'interconnects' and move 'clocks' to optional properties dt-bindings: qcom-qce: Add 'iommus' to required properties arm64/dts: qcom: sdm845: Use RPMH_CE_CLK macro directly dt-bindings: crypto : Add new compatible strings for qcom-qce arm64/dts: qcom: Use new compatibles for crypto nodes crypto: qce: Add new compatibles for qce crypto driver crypto: qce: Print a failure msg in case probe() fails crypto: qce: Convert the device found dev_dbg() to dev_info() crypto: qce: Defer probing if BAM dma channel is not yet initialized arm64/dts: qcom: sm8250: Add dt entries to support crypto engine. Thara Gopinath (3): dma: qcom: bam_dma: Add support to initialize interconnect path crypto: qce: core: Add support to initialize interconnect path crypto: qce: core: Make clocks optional .../devicetree/bindings/crypto/qcom-qce.txt | 25 ---- .../devicetree/bindings/crypto/qcom-qce.yaml | 92 +++++++++++++++ .../devicetree/bindings/dma/qcom_bam_dma.txt | 50 -------- .../devicetree/bindings/dma/qcom_bam_dma.yaml | 110 ++++++++++++++++++ arch/arm64/boot/dts/qcom/ipq6018.dtsi | 2 +- arch/arm64/boot/dts/qcom/sdm845.dtsi | 6 +- arch/arm64/boot/dts/qcom/sm8250.dtsi | 28 +++++ drivers/crypto/qce/core.c | 110 ++++++++++++------ drivers/crypto/qce/core.h | 3 + drivers/dma/qcom/bam_dma.c | 10 ++ 10 files changed, 322 insertions(+), 114 deletions(-) delete mode 100644 Documentation/devicetree/bindings/crypto/qcom-qce.txt create mode 100644 Documentation/devicetree/bindings/crypto/qcom-qce.yaml delete mode 100644 Documentation/devicetree/bindings/dma/qcom_bam_dma.txt create mode 100644 Documentation/devicetree/bindings/dma/qcom_bam_dma.yaml -- 2.31.1