From patchwork Wed Jun 30 03:46:50 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Manivannan Sadhasivam X-Patchwork-Id: 468678 Delivered-To: patch@linaro.org Received: by 2002:a02:c94a:0:0:0:0:0 with SMTP id u10csp5550353jao; Tue, 29 Jun 2021 20:47:15 -0700 (PDT) X-Google-Smtp-Source: ABdhPJzTNTxSPfpmQgQimcvwDO78KD/w9lYDMXs4Wwb2UYPdUa1shLKVZXYjrVQhNkPzMsuR4RSZ X-Received: by 2002:a17:906:852:: with SMTP id f18mr8796478ejd.346.1625024834891; Tue, 29 Jun 2021 20:47:14 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1625024834; cv=none; d=google.com; s=arc-20160816; b=M7EvbJgl7va6Xv6aNf2jzDiPTL7cbKNaQdf4oEsNssPg1Sj/I57T80r3/y+6TLnd9M dvApujJZgfLDY+dP5ctB7F3lzu9EjmgGPDzhqcB6F38jbpjiRsYbWl2qysIDj9y1Rhx0 49QQYSPqZneV+6bxjqIiO4C9CukG2YxJo6/mLhS1UqF3xz+r3NwyMW31/GuUG9XfFR8z 3I8cmkPxjtcImWADFIqJr4FH22+cM1+fBem+IBYiJvBmvQUNJg+SQhO0YBy5TUb3we3m vJ9Snfzc37gDRDgKYlz510osU4QIrXTrk3Egirg6BRtXrOx+CoDrpfkhGFcvCeNrF4ET gHWA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :message-id:date:subject:cc:to:from:dkim-signature; bh=Nfp5Ud7Atbg6Yf9Rudx7u8PLh35aqeWCQdA0/EvN+9U=; b=u22rL58+xnPdZuzv3qbknRtDip68nJr1DtQazuFk41sBKgpU5BjU6WsXZutxeDcvKG qqfG9FmxRDRKOr4ToMKWudUYV7CYTdbuHKaF1a8pJIjNNTSW6S76PrqtAfeP3lgXAU+t McXPs23C0dHBrtonPOL+OPnxQyYRb3vmcVLd+YM3Ksiv8gCTmXjwApbf39ELPRDEcrcu ubTcpHALGXmQAG4nnp4zNpJeexvj77H6yhItRDj5qu5CwaweNwXmwlip+UW1seoFDKmd AEiejAQo/+u+aflRptKeZkEMTi+xAu3Bicyoz3zlwLzBxoT8h8UHkbhXr/XOPctieMj9 asIw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=KyHZGH0h; spf=pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [23.128.96.18]) by mx.google.com with ESMTP id s7si8510197edd.314.2021.06.29.20.47.14; Tue, 29 Jun 2021 20:47:14 -0700 (PDT) Received-SPF: pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=KyHZGH0h; spf=pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233083AbhF3Dtl (ORCPT + 7 others); Tue, 29 Jun 2021 23:49:41 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:52784 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232902AbhF3Dti (ORCPT ); Tue, 29 Jun 2021 23:49:38 -0400 Received: from mail-pl1-x62e.google.com (mail-pl1-x62e.google.com [IPv6:2607:f8b0:4864:20::62e]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 557FEC061768 for ; Tue, 29 Jun 2021 20:47:10 -0700 (PDT) Received: by mail-pl1-x62e.google.com with SMTP id v13so689932ple.9 for ; Tue, 29 Jun 2021 20:47:10 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:mime-version :content-transfer-encoding; bh=Nfp5Ud7Atbg6Yf9Rudx7u8PLh35aqeWCQdA0/EvN+9U=; b=KyHZGH0hhhRJhA5+2alc8wkmgYE+A2aP0Q3TkoCB+BvEuNnTaK8VgwCOpZIOoYNCQj eYY7hp8FsfKGnPjpkPALQePXe6hz3livFjYKZb8VSOathXRNgQV58H4AyrU5X0y61e5P rrea4D0JhwTtAYCYHnZ3Y9y3j4aVH77JL7y9uqmyFE77fW8+e59OGxCd1cYBlSNvbQEK +r4eDq+blNJvXOKYPrZm0DovqK8iNCFnOMN3ZESsLU6F1VEABVn9x1jYT600HXoncXRH kLLV0zExKOMXNr8C2t0Nnk/sG7TyRO5CG7ueReXXZ4Q5PiGNCMnaTvXPEJ0dGrfH7SZt pv6A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:mime-version :content-transfer-encoding; bh=Nfp5Ud7Atbg6Yf9Rudx7u8PLh35aqeWCQdA0/EvN+9U=; b=hgySHvTuMSoPtmSUWYyRoBTfA2tdzUbeLorvs18Qzf0pAiRZXMcoPfvbjJxG52Rfjv mZ0kugZtQNRZxx3GFFeGGJeNLOy2utVkynROvq8aN4d6IWCrUkJnC99IxF9FSdSWokDL cmIE1XxrdIoDEIVZknQx5WSCIbeBMFyoGpf18+ThapvX3K+ESMxR3QCNU2pCg08+sY+B 3lbxDPa49a19VAHKWN2HCDoII3Ki0KpD/eRHu6KF/1Nhu10lN6sF1/UXl5NUhxJ5eXt0 qbT18dfuWsvrY6EPMs99yTYfRQ9yK9vlAD2QHEHw3yHBjOFLU4xK/TYwtv4b9MYLbATI fV4w== X-Gm-Message-State: AOAM531GEl413Vq2k5mKmBccp1J64rFbbyfPMdx8nambhJGwUrMbE9vf HFsxGbAg92wXT4/K6OTkGot6 X-Received: by 2002:a17:90b:8cc:: with SMTP id ds12mr37596230pjb.36.1625024829523; Tue, 29 Jun 2021 20:47:09 -0700 (PDT) Received: from localhost.localdomain ([120.138.13.102]) by smtp.gmail.com with ESMTPSA id j15sm19565081pfh.194.2021.06.29.20.47.03 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 29 Jun 2021 20:47:08 -0700 (PDT) From: Manivannan Sadhasivam To: kishon@ti.com, lorenzo.pieralisi@arm.com, bhelgaas@google.com, robh@kernel.org Cc: devicetree@vger.kernel.org, linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, hemantk@codeaurora.org, smohanad@codeaurora.org, bjorn.andersson@linaro.org, sallenki@codeaurora.org, skananth@codeaurora.org, vpernami@codeaurora.org, vbadigan@codeaurora.org, Manivannan Sadhasivam Subject: [PATCH v5 0/3] Add Qualcomm PCIe Endpoint driver support Date: Wed, 30 Jun 2021 09:16:50 +0530 Message-Id: <20210630034653.10260-1-manivannan.sadhasivam@linaro.org> X-Mailer: git-send-email 2.25.1 MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Hello, This series adds support for Qualcomm PCIe Endpoint controller found in platforms like SDX55. The Endpoint controller is based on the designware core with additional Qualcomm wrappers around the core. The driver is added separately unlike other Designware based drivers that combine RC and EP in a single driver. This is done to avoid complexity and to maintain this driver autonomously. The driver has been validated with an out of tree MHI function driver on SDX55 based Telit FN980 EVB connected to x86 host machine over PCIe. Thanks, Mani Changes in v5: * Removed the DBI register settings that are not needed * Used the standard definitions available in pci_regs.h * Added defines for all the register fields * Removed the left over code from previous iteration Changes in v4: * Removed the active_config settings needed for IPA integration * Switched to writel for couple of relaxed versions that sneaked in Changes in v3: * Lot of minor cleanups to the driver patch based on review from Bjorn and Stan. * Noticeable changes are: - Got rid of _relaxed calls and used readl/writel - Got rid of separate TCSR memory region and used syscon for getting the register offsets for Perst registers - Changed the wake gpio handling logic - Added remove() callback and removed "suppress_bind_attrs" - stop_link() callback now just disables PERST IRQ * Added MMIO region and doorbell interrupt to the binding * Added logic to write MMIO physicall address to MHI base address as it is for the function driver to work Changes in v2: * Addressed the comments from Rob on bindings patch * Modified the driver as per binding change * Fixed the warnings reported by Kbuild bot * Removed the PERST# "enable_irq" call from probe() Manivannan Sadhasivam (3): dt-bindings: pci: Add devicetree binding for Qualcomm PCIe EP controller PCI: dwc: Add Qualcomm PCIe Endpoint controller driver MAINTAINERS: Add entry for Qualcomm PCIe Endpoint driver and binding .../devicetree/bindings/pci/qcom,pcie-ep.yaml | 160 ++++ MAINTAINERS | 10 +- drivers/pci/controller/dwc/Kconfig | 10 + drivers/pci/controller/dwc/Makefile | 1 + drivers/pci/controller/dwc/pcie-qcom-ep.c | 742 ++++++++++++++++++ 5 files changed, 922 insertions(+), 1 deletion(-) create mode 100644 Documentation/devicetree/bindings/pci/qcom,pcie-ep.yaml create mode 100644 drivers/pci/controller/dwc/pcie-qcom-ep.c -- 2.25.1