[v5,0/9] Nuvoton WPCM450 pinctrl and GPIO driver

This is version 5 of the WPCM450 pinctrl/GPIO driver patchset.

I was originally just going to rebase the patchset on top of v5.17-rc1,
but while testing, I found that the IRQ handling code violated locking
rules, specifically that it used spin locks (which can sleep on RT kernels)
in IRQ contexts. So I made a few changes to fix that, mainly switching
to raw spin locks.

Best regards,
Jonathan Neuschäfer

v4: https://lore.kernel.org/lkml/20220109173000.1242703-1-j.neuschaefer@gmx.net/
v3: https://lore.kernel.org/lkml/20211224200935.93817-1-j.neuschaefer@gmx.net/
v2: https://lore.kernel.org/lkml/20211207210823.1975632-1-j.neuschaefer@gmx.net/

v1:
- https://lore.kernel.org/lkml/20210602120329.2444672-1-j.neuschaefer@gmx.net/

> This series adds support for pinctrl and GPIO in the Nuvoton WPCM450 SoC.
> Both my DT bindings and my driver are based on the work done by others for
> the newer Nuvoton NPCM7xx SoC, and I've tried to keep both similar.
>
> Instead of extending the pinctrl-npcm7xx driver to add WPCM450 support,
> I copied/forked it. The pinmux mechanism is very similar (using MFSEL1 and
> MFSEL2 registers), but the GPIO register interface has been redesigned for
> NPCM7xx; adding support for the older GPIO controller would make the driver
> harder to understand, while only enabling a small amount of code sharing.
>
> The DT binding in YAML format might make a good template for also converting
> the nuvoton,npcm7xx-pinctrl binding to YAML.
>
> Both in the DT binding and in the driver I kept the name "pinctrl". For the
> driver, I find it accurate enough because it handles pinctrl and GPIO. For
> the DT node, it's a bit less accurate because the register block at 0xb8003000
> is about GPIOs, and pin control happens in the global control registers (GCR)
> block, except for input debouncing. So, "GPIO" might be the more appropriate
> name component there.

Jonathan Neuschäfer (9):
  dt-bindings: arm/npcm: Add binding for global control registers (GCR)
  MAINTAINERS: Match all of bindings/arm/npcm/ as part of NPCM
    architecture
  ARM: dts: wpcm450: Add global control registers (GCR) node
  dt-bindings: pinctrl: Add Nuvoton WPCM450
  pinctrl: nuvoton: Add driver for WPCM450
  ARM: dts: wpcm450: Add pinctrl and GPIO nodes
  ARM: dts: wpcm450: Add pin functions
  ARM: dts: wpcm450-supermicro-x9sci-ln4f: Add GPIO LEDs and buttons
  ARM: dts: wpcm450: Add pinmux information to UART0

 .../bindings/arm/npcm/nuvoton,gcr.yaml        |   48 +
 .../pinctrl/nuvoton,wpcm450-pinctrl.yaml      |  160 +++
 MAINTAINERS                                   |    2 +
 .../nuvoton-wpcm450-supermicro-x9sci-ln4f.dts |   43 +
 arch/arm/boot/dts/nuvoton-wpcm450.dtsi        |  384 ++++++
 drivers/pinctrl/Makefile                      |    2 +-
 drivers/pinctrl/nuvoton/Kconfig               |   18 +
 drivers/pinctrl/nuvoton/Makefile              |    1 +
 drivers/pinctrl/nuvoton/pinctrl-wpcm450.c     | 1150 +++++++++++++++++
 9 files changed, 1807 insertions(+), 1 deletion(-)
 create mode 100644 Documentation/devicetree/bindings/arm/npcm/nuvoton,gcr.yaml
 create mode 100644 Documentation/devicetree/bindings/pinctrl/nuvoton,wpcm450-pinctrl.yaml
 create mode 100644 drivers/pinctrl/nuvoton/pinctrl-wpcm450.c

--
2.34.1

On Sun, Jan 30, 2022 at 02:50:25AM +0100, Linus Walleij wrote:
> On Sat, Jan 29, 2022 at 12:57 PM Jonathan Neuschäfer
> <j.neuschaefer@gmx.net> wrote:
> 
> > This is version 5 of the WPCM450 pinctrl/GPIO driver patchset.
> 
> I haven't had time to look in detail but the kernel robot is complaining
> about patch 5...

These are warnings about the pinctrl-npcm7xx driver that became (more
easily) visible under CONFIG_COMPILE_TEST through my patch.

> 
> > I was originally just going to rebase the patchset on top of v5.17-rc1,
> > but while testing, I found that the IRQ handling code violated locking
> > rules, specifically that it used spin locks (which can sleep on RT kernels)
> > in IRQ contexts. So I made a few changes to fix that, mainly switching
> > to raw spin locks.
> 
> Which patches do you expect to be applied to the pin control tree?

These two:

[PATCH v5 4/9] dt-bindings: pinctrl: Add Nuvoton WPCM450
[PATCH v5 5/9] pinctrl: nuvoton: Add driver for WPCM450

and the rest can go through Joel Stanley's BMC tree, I think.


Thanks,
Jonathan

On Tue, 1 Feb 2022 at 13:05, Jonathan Neuschäfer <j.neuschaefer@gmx.net> wrote:
>
> On Sun, Jan 30, 2022 at 02:50:25AM +0100, Linus Walleij wrote:
> > On Sat, Jan 29, 2022 at 12:57 PM Jonathan Neuschäfer
> > <j.neuschaefer@gmx.net> wrote:
> >
> > > This is version 5 of the WPCM450 pinctrl/GPIO driver patchset.

> > Which patches do you expect to be applied to the pin control tree?
>
> These two:
>
> [PATCH v5 4/9] dt-bindings: pinctrl: Add Nuvoton WPCM450
> [PATCH v5 5/9] pinctrl: nuvoton: Add driver for WPCM450
>
> and the rest can go through Joel Stanley's BMC tree, I think.

Seems reasonable. I assume you're sending a v6 to fix some of the warnings?

Cheers,

Joel

On Wed, Feb 02, 2022 at 02:10:44PM +0200, Andy Shevchenko wrote:
> On Wed, Feb 2, 2022 at 2:01 PM Jonathan Neuschäfer
> <j.neuschaefer@gmx.net> wrote:
> > On Tue, Feb 01, 2022 at 11:42:11PM +0000, Joel Stanley wrote:
> > > On Tue, 1 Feb 2022 at 13:05, Jonathan Neuschäfer <j.neuschaefer@gmx.net> wrote:
> 
> ...
> 
> > > I assume you're sending a v6 to fix some of the warnings?
> >
> > No, the warnings are fairly independent of this patchset, it's just that
> > the adjacent pinctrl-npcm7xx driver started to be built by the bot, due
> > to my Kconfig change. I'll fix them in a separate patchset.
> 
> I guess you need to fix that first.
> 
> Because now and then all CIs will complain to your patch and confuse people.

Hm, right.

I'll send the pinctrl-npcm7xx fixes, and then a version 6 of this
patchset if necessary.


Jonathan