From patchwork Fri Dec 2 03:13:22 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Doug Brown X-Patchwork-Id: 630974 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 8FDA0C4321E for ; Fri, 2 Dec 2022 03:13:54 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231245AbiLBDNx (ORCPT ); Thu, 1 Dec 2022 22:13:53 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:55448 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231281AbiLBDNw (ORCPT ); Thu, 1 Dec 2022 22:13:52 -0500 Received: from mail-pf1-x433.google.com (mail-pf1-x433.google.com [IPv6:2607:f8b0:4864:20::433]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id DEEC6AA8C9 for ; Thu, 1 Dec 2022 19:13:50 -0800 (PST) Received: by mail-pf1-x433.google.com with SMTP id l127so3085036pfl.2 for ; Thu, 01 Dec 2022 19:13:50 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=schmorgal.com; s=google; h=content-transfer-encoding:mime-version:message-id:date:subject:cc :to:from:from:to:cc:subject:date:message-id:reply-to; bh=/KCyW/nZsCSOBqrMJLS3BfqoCX4HTe2xd1fQxSnYf4c=; b=Mgl3zQz64SSTsWS5jS3ZAVpbPf4ufwqiaqntCB5pAiMQXUrS9nQWsnbIEndDrjN5Ic Ue7BehdwCUNS02VQpUbrYG5E2zKMgVddhWykQtijzZ6RfV/T9SioCLPes/q0Kk4Eg6xy L/TWFrycIj/XCYHmlKkGS4BACNlygdvmCSBSc= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:message-id:date:subject:cc :to:from:x-gm-message-state:from:to:cc:subject:date:message-id :reply-to; bh=/KCyW/nZsCSOBqrMJLS3BfqoCX4HTe2xd1fQxSnYf4c=; b=74zl2FLZtQMpSejc7HG2m0T15TUU3vH3Kf2CtDhVZQ+kwiqG/22twv6EEp4vqDxKRB e0qg+++Mq24HK97TEnztI3oRymshQOAOrLOsDVN8uFLc5bZoVwQd7lMqzwNVLboV9RCB ZacxbfASXKslVzoFf1fgDK+WwCtkM8HLHtI3d7wAxDzkdyxf07hhYFAv/IoEVLLouRaU IRfgah68fcLZn0PMMH+GPod+xzMRAM72sudT36VJ6S4vXQWU2q3ako8YxY4dmcNRgFia DXjvD7GkxGdXaQRMBFtNNVsUdjeV3KyVByDGdFFjeWlAIqgRpjzl7ejxPls5Xl2Gb8fH qu6g== X-Gm-Message-State: ANoB5pk8WduBVtZiggBlzVAFUSf5DoOsaFfLZRZ6NRzP8/ZZsJGxzfvB /6FJZ+sDRhKQbT3bXZr/cMNA2g== X-Google-Smtp-Source: AA0mqf4bsC0ceRf9eG10Yhj6Qr71xtd1D/giJttzYDpCc1/ktkNuFv9ydePp+pSyzGPXrnj7W5/EyA== X-Received: by 2002:a63:db0a:0:b0:459:35b1:1396 with SMTP id e10-20020a63db0a000000b0045935b11396mr46503851pgg.593.1669950830237; Thu, 01 Dec 2022 19:13:50 -0800 (PST) Received: from doug-ryzen-5700G.. ([192.183.212.197]) by smtp.gmail.com with ESMTPSA id jx24-20020a17090b46d800b00213202d77d9sm3708410pjb.43.2022.12.01.19.13.49 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 01 Dec 2022 19:13:49 -0800 (PST) From: Doug Brown To: Ulf Hansson , Adrian Hunter Cc: Rob Herring , Krzysztof Kozlowski , linux-mmc@vger.kernel.org, devicetree@vger.kernel.org, Doug Brown Subject: [PATCH v2 0/8] mmc: sdhci-pxav2: Add support for PXA168 Date: Thu, 1 Dec 2022 19:13:22 -0800 Message-Id: <20221202031330.94130-1-doug@schmorgal.com> X-Mailer: git-send-email 2.34.1 MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org This is a revival of an earlier patch series from 2013 to add support for the PXA168 SDHC controller, with an additional SDIO IRQ errata fix. It also cleans up the clock naming to be consistent with the existing DT schema shared with the pxav3 driver (in a backwards-compatible way). Here is the original patch series this is based on: https://lore.kernel.org/linux-mmc/1363544206-3671-1-git-send-email-tanmay.upadhyay@einfochips.com/ Note that I left out the platform_specific_completion and clock gating changes from the original patches. They both seemed controversial, and don't seem necessary based on my testing. I've been running this code on a PXA168 for months without any issues. Changes in v2: - Fix mistakes in devicetree binding - Use cleaner code for pxav1_readw suggested by Adrian - Switch to request_done() and irq() for SDIO workaround CMD0 handling Doug Brown (8): mmc: sdhci-pxav2: add initial support for PXA168 V1 controller mmc: sdhci-pxav2: enable CONFIG_MMC_SDHCI_IO_ACCESSORS mmc: sdhci-pxav2: add register workaround for PXA168 silicon bug mmc: sdhci-pxav2: change clock name to match DT bindings mmc: sdhci-pxav2: add optional core clock mmc: sdhci-pxav2: add SDIO card IRQ workaround for PXA168 V1 controller mmc: sdhci-pxav2: add optional pinctrl for SDIO IRQ workaround dt-bindings: mmc: sdhci-pxa: add pxav1 .../devicetree/bindings/mmc/sdhci-pxa.yaml | 19 ++- drivers/mmc/host/Kconfig | 1 + drivers/mmc/host/sdhci-pxav2.c | 150 +++++++++++++++++- 3 files changed, 163 insertions(+), 7 deletions(-)