| Message ID | 20230221083323.302471-1-xingyu.wu@starfivetech.com |
|---|---|
| Headers | show |
| Series | Add new partial clock and reset drivers for StarFive JH7110 | expand |
On Tue, 21 Feb 2023 at 09:37, Xingyu Wu <xingyu.wu@starfivetech.com> wrote: > Add bindings for the System-Top-Group clock and reset generator (STGCRG) > on the JH7110 RISC-V SoC by StarFive Ltd. > > Signed-off-by: Xingyu Wu <xingyu.wu@starfivetech.com> > --- > .../clock/starfive,jh7110-stgcrg.yaml | 82 +++++++++++++++++++ > MAINTAINERS | 1 + > .../dt-bindings/clock/starfive,jh7110-crg.h | 34 ++++++++ > .../dt-bindings/reset/starfive,jh7110-crg.h | 28 +++++++ > 4 files changed, 145 insertions(+) > create mode 100644 Documentation/devicetree/bindings/clock/starfive,jh7110-stgcrg.yaml > > diff --git a/Documentation/devicetree/bindings/clock/starfive,jh7110-stgcrg.yaml b/Documentation/devicetree/bindings/clock/starfive,jh7110-stgcrg.yaml > new file mode 100644 > index 000000000000..b64ccd84200a > --- /dev/null > +++ b/Documentation/devicetree/bindings/clock/starfive,jh7110-stgcrg.yaml > @@ -0,0 +1,82 @@ > +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause > +%YAML 1.2 > +--- > +$id: http://devicetree.org/schemas/clock/starfive,jh7110-stgcrg.yaml# > +$schema: http://devicetree.org/meta-schemas/core.yaml# > + > +title: StarFive JH7110 System-Top-Group Clock and Reset Generator > + > +maintainers: > + - Xingyu Wu <xingyu.wu@starfivetech.com> > + > +properties: > + compatible: > + const: starfive,jh7110-stgcrg > + > + reg: > + maxItems: 1 > + > + clocks: > + items: > + - description: Main Oscillator (24 MHz) > + - description: HIFI4 core > + - description: STG AXI/AHB > + - description: USB (125 MHz) > + - description: CPU Bus > + - description: HIFI4 Axi > + - description: NOC STG Bus > + - description: APB Bus > + > + clock-names: > + items: > + - const: osc > + - const: hifi4_core > + - const: stg_axiahb > + - const: usb_125m > + - const: cpu_bus > + - const: hifi4_axi > + - const: nocstg_bus > + - const: apb_bus > + > + '#clock-cells': > + const: 1 > + description: > + See <dt-bindings/clock/starfive,jh7110-crg.h> for valid indices. > + > + '#reset-cells': > + const: 1 > + description: > + See <dt-bindings/reset/starfive,jh7110-crg.h> for valid indices. > + > +required: > + - compatible > + - reg > + - clocks > + - clock-names > + - '#clock-cells' > + - '#reset-cells' > + > +additionalProperties: false > + > +examples: > + - | > + #include <dt-bindings/clock/starfive,jh7110-crg.h> > + > + stgcrg: clock-controller@10230000 { > + compatible = "starfive,jh7110-stgcrg"; > + reg = <0x10230000 0x10000>; > + clocks = <&osc>, > + <&syscrg JH7110_SYSCLK_HIFI4_CORE>, > + <&syscrg JH7110_SYSCLK_STG_AXIAHB>, > + <&syscrg JH7110_SYSCLK_USB_125M>, > + <&syscrg JH7110_SYSCLK_CPU_BUS>, > + <&syscrg JH7110_SYSCLK_HIFI4_AXI>, > + <&syscrg JH7110_SYSCLK_NOCSTG_BUS>, > + <&syscrg JH7110_SYSCLK_APB_BUS>; > + clock-names = "osc", "hifi4_core", > + "stg_axiahb", "usb_125m", > + "cpu_bus", "hifi4_axi", > + "nocstg_bus", "apb_bus"; > + #clock-cells = <1>; > + #reset-cells = <1>; > + }; > diff --git a/MAINTAINERS b/MAINTAINERS > index 93eb504c3b21..2e70c9f21989 100644 > --- a/MAINTAINERS > +++ b/MAINTAINERS > @@ -19914,6 +19914,7 @@ F: arch/riscv/boot/dts/starfive/ > STARFIVE JH71X0 CLOCK DRIVERS > M: Emil Renner Berthing <kernel@esmil.dk> > M: Hal Feng <hal.feng@starfivetech.com> > +M: Xingyu Wu <xingyu.wu@starfivetech.com> > S: Maintained > F: Documentation/devicetree/bindings/clock/starfive,jh71*.yaml > F: drivers/clk/starfive/clk-starfive-jh71* > diff --git a/include/dt-bindings/clock/starfive,jh7110-crg.h b/include/dt-bindings/clock/starfive,jh7110-crg.h > index 5e4f21ca0642..5ac8a4d90a7a 100644 > --- a/include/dt-bindings/clock/starfive,jh7110-crg.h > +++ b/include/dt-bindings/clock/starfive,jh7110-crg.h > @@ -1,6 +1,7 @@ > /* SPDX-License-Identifier: GPL-2.0 OR MIT */ > /* > * Copyright 2022 Emil Renner Berthing <kernel@esmil.dk> > + * Copyright 2022 StarFive Technology Co., Ltd. > */ > > #ifndef __DT_BINDINGS_CLOCK_STARFIVE_JH7110_CRG_H__ > @@ -222,4 +223,37 @@ > > #define JH7110_AONCLK_END 14 Hi Xingyu, The clock and reset names below have been shortened from the very long names in the documentation. I see you've come to the same shortened names as I used in the first STGCRG driver I pushed, which is great, but I find it highly unlikely to have happened without looking at / copying my code like you did for the SYSCRG and AONCRG drivers Hal has posted. Unfortunately the commit message above doesn't reflect that, so please add a Co-developed-by: Emil Renner Berthing <kernel@esmil.dk> Signed-off-by: Emil Renner Berthing <kernel@esmil.dk> I do have some updated suggestions for short names below though: > +/* STGCRG clocks */ > +#define JH7110_STGCLK_HIFI4_CLK_CORE 0 > +#define JH7110_STGCLK_USB0_APB 1 > +#define JH7110_STGCLK_USB0_UTMI_APB 2 unli > +#define JH7110_STGCLK_USB0_AXI 3 > +#define JH7110_STGCLK_USB0_LPM 4 > +#define JH7110_STGCLK_USB0_STB 5 > +#define JH7110_STGCLK_USB0_APP_125 6 > +#define JH7110_STGCLK_USB0_REFCLK 7 > +#define JH7110_STGCLK_PCIE0_AXI_MST0 8 > +#define JH7110_STGCLK_PCIE0_APB 9 > +#define JH7110_STGCLK_PCIE0_TL 10 > +#define JH7110_STGCLK_PCIE1_AXI_MST0 11 > +#define JH7110_STGCLK_PCIE1_APB 12 > +#define JH7110_STGCLK_PCIE1_TL 13 > +#define JH7110_STGCLK_PCIE01_SLV_DEC_MAINCLK 14 Does PCIE01 here mean that the clock is used by both pcie0 and pcie1? If so then maybe just call it JH7110_PCIE_SLV_MAIN > +#define JH7110_STGCLK_SEC_HCLK 15 For other clocks I think "hclk" means ahb clock, so maybe JH7110_STGCLK_SEC_AHB > +#define JH7110_STGCLK_SEC_MISCAHB 16 I find something like JH7110_STGCLK_SEC_MISC_AHB a little easier to read. > +#define JH7110_STGCLK_GRP0_MAIN 17 > +#define JH7110_STGCLK_GRP0_BUS 18 > +#define JH7110_STGCLK_GRP0_STG 19 > +#define JH7110_STGCLK_GRP1_MAIN 20 > +#define JH7110_STGCLK_GRP1_BUS 21 > +#define JH7110_STGCLK_GRP1_STG 22 > +#define JH7110_STGCLK_GRP1_HIFI 23 > +#define JH7110_STGCLK_E2_RTC 24 > +#define JH7110_STGCLK_E2_CORE 25 > +#define JH7110_STGCLK_E2_DBG 26 > +#define JH7110_STGCLK_DMA1P_AXI 27 > +#define JH7110_STGCLK_DMA1P_AHB 28 > + > +#define JH7110_STGCLK_END 29 > + > #endif /* __DT_BINDINGS_CLOCK_STARFIVE_JH7110_CRG_H__ */ > diff --git a/include/dt-bindings/reset/starfive,jh7110-crg.h b/include/dt-bindings/reset/starfive,jh7110-crg.h > index d78e38690ceb..4a865ded78b8 100644 > --- a/include/dt-bindings/reset/starfive,jh7110-crg.h > +++ b/include/dt-bindings/reset/starfive,jh7110-crg.h > @@ -1,6 +1,7 @@ > /* SPDX-License-Identifier: GPL-2.0 OR MIT */ > /* > * Copyright (C) 2022 Emil Renner Berthing <kernel@esmil.dk> > + * Copyright (C) 2022 StarFive Technology Co., Ltd. > */ > > #ifndef __DT_BINDINGS_RESET_STARFIVE_JH7110_CRG_H__ > @@ -151,4 +152,31 @@ > > #define JH7110_AONRST_END 8 > > +/* STGCRG resets */ > +#define JH7110_STGRST_SYSCON 0 > +#define JH7110_STGRST_HIFI4_CORE 1 > +#define JH7110_STGRST_HIFI4_AXI 2 > +#define JH7110_STGRST_SEC_TOP_HRESETN 3 JH7110_STGRST_SEC_AHB to match the clock above. > +#define JH7110_STGRST_E24_CORE 4 > +#define JH7110_STGRST_DMA1P_AXI 5 > +#define JH7110_STGRST_DMA1P_AHB 6 > +#define JH7110_STGRST_USB0_AXI 7 > +#define JH7110_STGRST_USB0_APB 8 > +#define JH7110_STGRST_USB0_UTMI_APB 9 > +#define JH7110_STGRST_USB0_PWRUP 10 > +#define JH7110_STGRST_PCIE0_AXI_MST0 11 > +#define JH7110_STGRST_PCIE0_AXI_SLV0 12 > +#define JH7110_STGRST_PCIE0_AXI_SLV 13 > +#define JH7110_STGRST_PCIE0_BRG 14 > +#define JH7110_STGRST_PCIE0_CORE 15 > +#define JH7110_STGRST_PCIE0_APB 16 > +#define JH7110_STGRST_PCIE1_AXI_MST0 17 > +#define JH7110_STGRST_PCIE1_AXI_SLV0 18 > +#define JH7110_STGRST_PCIE1_AXI_SLV 19 > +#define JH7110_STGRST_PCIE1_BRG 20 > +#define JH7110_STGRST_PCIE1_CORE 21 > +#define JH7110_STGRST_PCIE1_APB 22 > + > +#define JH7110_STGRST_END 23 > + > #endif /* __DT_BINDINGS_RESET_STARFIVE_JH7110_CRG_H__ */ > -- > 2.25.1 > > > _______________________________________________ > linux-riscv mailing list > linux-riscv@lists.infradead.org > http://lists.infradead.org/mailman/listinfo/linux-riscv
This patch serises are to add new partial clock drivers and reset supports about System-Top-Group(STG), Image-Signal-Process(ISP) and Video-Output(VOUT) for the StarFive JH7110 RISC-V SoC. Patches 1 to 3 are about the System-Top-Group clock and reset generator(STGCRG) part. The first patch adds docunmentation to describe STG bindings, and the second patch adds support about STG resets. The last patch adds clock driver to support STG clocks for JH7110. Patches 4 to 6 are about the Image-Signal-Process clock and reset gennerator(ISPCRG) part. The first patch adds docunmentation to describe ISP bindings, and the second patch adds support about ISP resets. The last patch adds clock driver to support ISP clocks for JH7110. Patches 7 to 9 are about the Video-Output clock and reset generator(VOUTCRG) part. The first patch adds docunmentation to describe VOUT bindings, and the second patch adds support about VOUT resets. The last patch adds clock driver to support VOUT clocks for JH7110. Patch 10 adds external clocks which ISP and VOUT clock driver need. Patch 11 adds device node about STGCRG, ISPCRG and VOUTCRG to JH7110 dts. Patches 2, 3, 5, 6, 8 and 9 are dependent on the patchset [1] which is about JH71x0 clock and reset driver. Patches 6 and 9 also are dependent on the patchset [2] which is about JH7110 PMU driver(Accpeted). Patchdes 10 and 11 are dependent on the patchset [1] and [3] which is about JH7110 device tree and PMU node. This patchset should be applied after the patchset [1], [2], [3]: [1] https://lore.kernel.org/all/20230221024645.127922-1-hal.feng@starfivetech.com/ [2] https://lore.kernel.org/all/20230119094447.21939-3-walker.chen@starfivetech.com/ [3] https://lore.kernel.org/all/20230116074259.22874-4-walker.chen@starfivetech.com/ Changes since v1: - Modified the binding and dropped the indentation. - Removed the useless header files in the drivers. - Used an array lookup instead of a pile of conditions about parent clocks' name. - Added clocks operation on driver remove. v1: https://lore.kernel.org/all/20230120024445.244345-1-xingyu.wu@starfivetech.com/ Xingyu Wu (11): dt-bindings: clock: Add StarFive JH7110 System-Top-Group clock and reset generator reset: starfive: jh7110: Add StarFive System-Top-Group reset support clk: starfive: Add StarFive JH7110 System-Top-Group clock driver dt-bindings: clock: Add StarFive JH7110 Image-Signal-Process clock and reset generator reset: starfive: jh7110: Add StarFive Image-Signal-Process reset support clk: starfive: Add StarFive JH7110 Image-Signal-Process clock driver dt-bindings: clock: Add StarFive JH7110 Video-Output clock and reset generator reset: starfive: jh7110: Add StarFive Video-Output reset support clk: starfive: Add StarFive JH7110 Video-Output clock driver riscv: dts: starfive: jh7110: Add DVP and HDMI TX pixel external clocks riscv: dts: starfive: jh7110: Add STGCRG/ISPCRG/VOUTCRG nodes .../clock/starfive,jh7110-ispcrg.yaml | 97 +++++++ .../clock/starfive,jh7110-stgcrg.yaml | 82 ++++++ .../clock/starfive,jh7110-voutcrg.yaml | 96 +++++++ MAINTAINERS | 1 + .../jh7110-starfive-visionfive-2.dtsi | 8 + arch/riscv/boot/dts/starfive/jh7110.dtsi | 71 +++++ drivers/clk/starfive/Kconfig | 33 +++ drivers/clk/starfive/Makefile | 3 + .../clk/starfive/clk-starfive-jh7110-isp.c | 254 +++++++++++++++++ .../clk/starfive/clk-starfive-jh7110-stg.c | 176 ++++++++++++ .../clk/starfive/clk-starfive-jh7110-vout.c | 261 ++++++++++++++++++ .../reset/starfive/reset-starfive-jh7110.c | 30 ++ .../dt-bindings/clock/starfive,jh7110-crg.h | 74 +++++ .../dt-bindings/reset/starfive,jh7110-crg.h | 60 ++++ 14 files changed, 1246 insertions(+) create mode 100644 Documentation/devicetree/bindings/clock/starfive,jh7110-ispcrg.yaml create mode 100644 Documentation/devicetree/bindings/clock/starfive,jh7110-stgcrg.yaml create mode 100644 Documentation/devicetree/bindings/clock/starfive,jh7110-voutcrg.yaml create mode 100644 drivers/clk/starfive/clk-starfive-jh7110-isp.c create mode 100644 drivers/clk/starfive/clk-starfive-jh7110-stg.c create mode 100644 drivers/clk/starfive/clk-starfive-jh7110-vout.c base-commit: c9c3395d5e3dcc6daee66c6908354d47bf98cb0c prerequisite-patch-id: 4dc515731ce237184553c1606ffb3afaeb51c3d8 prerequisite-patch-id: ac150a8c622e858e088df8121093d448df49c245 prerequisite-patch-id: a4255724d4698f1238663443024de56de38d717b prerequisite-patch-id: a798370d170dc2bcc79ed86f741c21c1e6d87c78 prerequisite-patch-id: 203d2500cadc112bd20fefc56eabf1470d3d2d2d prerequisite-patch-id: 315303931e4b6499de7127a88113763f86e97e16 prerequisite-patch-id: 40cb8212ddb024c20593f73d8b87d9894877e172 prerequisite-patch-id: a1673a9e9f19d6fab5a51abb721e54e36636f067 prerequisite-patch-id: 94860423c7acc9025249d4bb36652a585bd0a797 prerequisite-patch-id: b5084253283929d9a6d0e66c350400c7c85d034d prerequisite-patch-id: a428ed7a2aa45abab86923dc467e1e6b08427e85 prerequisite-patch-id: d4f80829fca7ce370a6fad766593cdcb502fa245 prerequisite-patch-id: e3490e19e089fe284334db300ee189b619a61628 prerequisite-patch-id: 34298e3882261bc2d72955b1570cc9612ab7d662 prerequisite-patch-id: 377c5c282a0776feee9acd10b565adbd5275a67e prerequisite-patch-id: 3ccee718de0750adbf8d0b77d553a2778a344f64 prerequisite-patch-id: 4710f2ac22dca0bdd9ff5d744d2c37cab3c74515 prerequisite-patch-id: 65f2aed865d88e6fa468d2923527b523d4313857 prerequisite-patch-id: 258ea5f9b8bf41b6981345dcc81795f25865d38f prerequisite-patch-id: 8b6f2c9660c0ac0ee4e73e4c21aca8e6b75e81b9 prerequisite-patch-id: e3b986b9c60b2b93b7812ec174c9e1b4cfb14c97 prerequisite-patch-id: a2b3a9cff8a683422eb0ccf3a0850091401812d4 prerequisite-patch-id: dbb0c0151b8bdf093e6ce79fd2fe3f60791a6e0b prerequisite-patch-id: ea9a6d0313dd3936c8de0239dc2072c3360a2f6b prerequisite-patch-id: d57e95d31686772abc4c4d5aa1cadc344dc293cd prerequisite-patch-id: 29aab7148bf56a20acddcb8a11f290705fcc97f6 prerequisite-patch-id: eeecb5367bea99627210b661986ca5b49e2a9d63 prerequisite-patch-id: c02658f677990683d4c4957e06c19ed3a3a0cfab prerequisite-patch-id: 2ddada18ab6ea5cd1da14212aaf59632f5203d40