[00/19] Qcom PCIe cleanups and improvements

Message ID	20230306153222.157667-1-manivannan.sadhasivam@linaro.org
Headers	show Return-Path: <devicetree-owner@vger.kernel.org> From: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> To: andersson@kernel.org, lpieralisi@kernel.org, kw@linux.com, krzysztof.kozlowski+dt@linaro.org, robh@kernel.org Cc: konrad.dybcio@linaro.org, linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org, quic_srichara@quicinc.com, Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Subject: [PATCH 00/19] Qcom PCIe cleanups and improvements Date: Mon, 6 Mar 2023 21:02:03 +0530 Message-Id: <20230306153222.157667-1-manivannan.sadhasivam@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Precedence: bulk
Series	Qcom PCIe cleanups and improvements \| expand [00/19] Qcom PCIe cleanups and improvements [01/19] PCI: qcom: Remove PCIE20_ prefix from register definitions [04/19] PCI: qcom: Add missing macros for register fields [05/19] PCI: qcom: Use lower case for hex [07/19] PCI: qcom: Use bulk clock APIs for handling clocks for IP rev 1.0.0 [10/19] PCI: qcom: Use bulk reset APIs for handling resets for IP rev 2.3.3 [12/19] PCI: qcom: Use macros for defining total no. of clocks & supplies [14/19] PCI: qcom-ep: Rename "mmio" region to "mhi" [18/19] arm64: dts: qcom: sc8280xp: Add "mhi" region to the PCIe nodes [19/19] PCI: qcom: Expose link transition counts via debugfs

Message ID

20230306153222.157667-1-manivannan.sadhasivam@linaro.org

Headers

From: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
To: andersson@kernel.org, lpieralisi@kernel.org, kw@linux.com,
        krzysztof.kozlowski+dt@linaro.org, robh@kernel.org
Cc: konrad.dybcio@linaro.org, linux-arm-msm@vger.kernel.org,
        devicetree@vger.kernel.org, linux-pci@vger.kernel.org,
        linux-kernel@vger.kernel.org, quic_srichara@quicinc.com,
        Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Subject: [PATCH 00/19] Qcom PCIe cleanups and improvements
Date: Mon,  6 Mar 2023 21:02:03 +0530
Message-Id: <20230306153222.157667-1-manivannan.sadhasivam@linaro.org>
MIME-Version: 1.0
Content-Transfer-Encoding: 8bit
Precedence: bulk

Series

Qcom PCIe cleanups and improvements | expand

Message

Manivannan Sadhasivam March 6, 2023, 3:32 p.m. UTC

Hi,

This series brings in several code cleanups and improvements to the
Qualcomm PCIe controller drivers (RC and EP). The cleanup part mostly
cleans up the bitfield definitions and transitions to bulk APIs for clocks,
and resets. The improvement part renames the "mmio" region to "mhi" as per
Qualcomm's internal documentation EP driver and also adds the debugfs entry
to track link transition count in RC driver.

Testing
-------

I have tested this series on SDM845, SM8250 and SC8280XP based platforms.
However, I'm counting on Qualcomm folks CCed to do testing on older IPQ/APQ
platforms.

Merging Strategy
----------------

Binding and driver patches through PCI tree and DTS patches through Qcom
tree.

NOTE: For the sake of maintaining dependency, I've clubbed both cleanup and
improvement patches in the same series. If any of the maintainers prefer to
have them splitted, please let me know.

Thanks,
Mani


Manivannan Sadhasivam (19):
  PCI: qcom: Remove PCIE20_ prefix from register definitions
  PCI: qcom: Sort and group registers and bitfield definitions
  PCI: qcom: Use bitfield definitions for register fields
  PCI: qcom: Add missing macros for register fields
  PCI: qcom: Use lower case for hex
  PCI: qcom: Use bulk reset APIs for handling resets for IP rev 2.1.0
  PCI: qcom: Use bulk clock APIs for handling clocks for IP rev 1.0.0
  PCI: qcom: Use bulk clock APIs for handling clocks for IP rev 2.3.2
  PCI: qcom: Use bulk clock APIs for handling clocks for IP rev 2.3.3
  PCI: qcom: Use bulk reset APIs for handling resets for IP rev 2.3.3
  PCI: qcom: Use bulk reset APIs for handling resets for IP rev 2.4.0
  PCI: qcom: Use macros for defining total no. of clocks & supplies
  dt-bindings: PCI: qcom-ep: Rename "mmio" region to "mhi"
  PCI: qcom-ep: Rename "mmio" region to "mhi"
  dt-bindings: PCI: qcom: Add "mhi" register region to supported SoCs
  arm64: dts: qcom: sdm845: Add "mhi" region to the PCIe nodes
  arm64: dts: qcom: sm8250: Add "mhi" region to the PCIe nodes
  arm64: dts: qcom: sc8280xp: Add "mhi" region to the PCIe nodes
  PCI: qcom: Expose link transition counts via debugfs

 .../devicetree/bindings/pci/qcom,pcie-ep.yaml |    6 +-
 .../devicetree/bindings/pci/qcom,pcie.yaml    |   12 +-
 arch/arm64/boot/dts/qcom/sc8280xp.dtsi        |   15 +-
 arch/arm64/boot/dts/qcom/sdm845.dtsi          |    6 +-
 arch/arm64/boot/dts/qcom/sm8250.dtsi          |    9 +-
 drivers/pci/controller/dwc/pcie-qcom-ep.c     |   38 +-
 drivers/pci/controller/dwc/pcie-qcom.c        | 1009 ++++++-----------
 7 files changed, 414 insertions(+), 681 deletions(-)

Comments

Krzysztof Kozlowski March 7, 2023, 8:20 a.m. UTC | #1

On 06/03/2023 16:32, Manivannan Sadhasivam wrote:
> The "mhi" region contains the debug registers that could be used to monitor
> the PCIe link transitions.
> 
> Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
> ---
>  arch/arm64/boot/dts/qcom/sdm845.dtsi | 6 ++++--
>  1 file changed, 4 insertions(+), 2 deletions(-)
> 
> diff --git a/arch/arm64/boot/dts/qcom/sdm845.dtsi b/arch/arm64/boot/dts/qcom/sdm845.dtsi
> index 479859bd8ab3..0104e77dd8d5 100644
> --- a/arch/arm64/boot/dts/qcom/sdm845.dtsi
> +++ b/arch/arm64/boot/dts/qcom/sdm845.dtsi
> @@ -2280,10 +2280,11 @@ opp-4 {
>  		pcie0: pci@1c00000 {
>  			compatible = "qcom,pcie-sdm845";
>  			reg = <0 0x01c00000 0 0x2000>,
> +			      <0 0x01c07000 0 0x1000>,
>  			      <0 0x60000000 0 0xf1d>,
>  			      <0 0x60000f20 0 0xa8>,
>  			      <0 0x60100000 0 0x100000>;
> -			reg-names = "parf", "dbi", "elbi", "config";
> +			reg-names = "parf", "mhi", "dbi", "elbi", "config";

Indexes are fixed, thus this breaks other users of DTS.

Best regards,
Krzysztof