From patchwork Mon Jan 15 12:57:14 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Devarsh Thakkar X-Patchwork-Id: 763463 Received: from fllv0015.ext.ti.com (fllv0015.ext.ti.com [198.47.19.141]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 7F69717553; Mon, 15 Jan 2024 12:57:41 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=ti.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=ti.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b="xCGMBLjs" Received: from lelv0265.itg.ti.com ([10.180.67.224]) by fllv0015.ext.ti.com (8.15.2/8.15.2) with ESMTP id 40FCvHEa112237; Mon, 15 Jan 2024 06:57:17 -0600 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1705323437; bh=6iByVdVvYTCVZkLYoWSBd1ifMXk011NYhGbUvfcH5hM=; h=From:To:CC:Subject:Date; b=xCGMBLjs9zHNbrIUnG4ZN/d+VPZarbUZD5f8tWzRbjulXGTERhLl8kuWLOh5Yi+RZ gJPBGuZvA39VI6kSnAUeEnN5b0Nn2Pa3HhcYgOGbVaAfr4xknyxEV9gOWfTgYhETtc LxxuScoMKWNc+kYVqjW8bi54SEpLl7M87Vw4JLMk= Received: from DFLE111.ent.ti.com (dfle111.ent.ti.com [10.64.6.32]) by lelv0265.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 40FCvHph019828 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Mon, 15 Jan 2024 06:57:17 -0600 Received: from DFLE103.ent.ti.com (10.64.6.24) by DFLE111.ent.ti.com (10.64.6.32) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23; Mon, 15 Jan 2024 06:57:17 -0600 Received: from lelvsmtp6.itg.ti.com (10.180.75.249) by DFLE103.ent.ti.com (10.64.6.24) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23 via Frontend Transport; Mon, 15 Jan 2024 06:57:17 -0600 Received: from localhost (ti.dhcp.ti.com [172.24.227.95] (may be forged)) by lelvsmtp6.itg.ti.com (8.15.2/8.15.2) with ESMTP id 40FCvG9W128446; Mon, 15 Jan 2024 06:57:16 -0600 From: Devarsh Thakkar To: , , , , , , , , , , , , CC: , , , , , , Subject: [PATCH 0/2] Add common1 register space for TI Keystone displays Date: Mon, 15 Jan 2024 18:27:14 +0530 Message-ID: <20240115125716.560363-1-devarsht@ti.com> X-Mailer: git-send-email 2.34.1 Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Add common1 register space for SoC's supporting TI Keystone displays present in AM65x and AM62x SoCs. This is required to support use-cases where Linux may want to use common1 region instead of common region with the latter being controlled by another processing core. The enumeration of common1 region in device-tree bindings seem to be a miss as ideally bindings should enumerate all supported register spaces as done in Documentation/devicetree/bindings/display/ti/ti,j721e-dss.yaml which also uses TI Keystone display subsystem albeit with some more features. Devarsh Thakkar (2): dt-bindings: display: ti,am65x-dss: Add support for common1 region arm64: dts: ti: Add common1 register space for AM62x and AM65x SoCs .../devicetree/bindings/display/ti/ti,am65x-dss.yaml | 7 +++++-- arch/arm64/boot/dts/ti/k3-am62-main.dtsi | 5 +++-- arch/arm64/boot/dts/ti/k3-am65-main.dtsi | 5 +++-- 3 files changed, 11 insertions(+), 6 deletions(-)