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[209.132.180.67]) by mx.google.com with ESMTP id ri5si4209715pdb.115.2015.03.04.00.49.59; Wed, 04 Mar 2015 00:50:00 -0800 (PST) Received-SPF: none (google.com: linux-kernel-owner@vger.kernel.org does not designate permitted sender hosts) client-ip=209.132.180.67; Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S933468AbbCDIty (ORCPT + 28 others); Wed, 4 Mar 2015 03:49:54 -0500 Received: from mail-pa0-f54.google.com ([209.85.220.54]:36469 "EHLO mail-pa0-f54.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1760607AbbCDItv (ORCPT ); Wed, 4 Mar 2015 03:49:51 -0500 Received: by padfa1 with SMTP id fa1so25589534pad.3 for ; Wed, 04 Mar 2015 00:49:50 -0800 (PST) X-Received: by 10.66.167.206 with SMTP id zq14mr5145560pab.62.1425458990395; Wed, 04 Mar 2015 00:49:50 -0800 (PST) Received: from localhost.localdomain ([124.219.30.17]) by mx.google.com with ESMTPSA id n4sm3326384pdl.12.2015.03.04.00.49.40 (version=TLSv1.2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Wed, 04 Mar 2015 00:49:49 -0800 (PST) From: "pi-cheng.chen" To: Viresh Kumar , Matthias Brugger , Rob Herring , "Rafael J. Wysocki" , Thomas Petazzoni Cc: Pawel Moll , Mark Rutland , Ian Campbell , Kumar Gala , Catalin Marinas , Will Deacon , "pi-cheng.chen" , "Joe.C" , Eddie Huang , Howard Chen , Ashwin Chaugule , Mike Turquette , fan.chen@mediatek.com, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org, linaro-kernel@lists.linaro.org, linux-mediatek@lists.infradead.org Subject: [PATCH v2 2/4] cpufreq: dt-bindings: add bindings for mtk-cpufreq driver Date: Wed, 4 Mar 2015 16:49:14 +0800 Message-Id: <1425458956-20665-3-git-send-email-pi-cheng.chen@linaro.org> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1425458956-20665-1-git-send-email-pi-cheng.chen@linaro.org> References: <1425458956-20665-1-git-send-email-pi-cheng.chen@linaro.org> Sender: linux-kernel-owner@vger.kernel.org Precedence: list List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-Removed-Original-Auth: Dkim didn't pass. X-Original-Sender: pi-cheng.chen@linaro.org X-Original-Authentication-Results: mx.google.com; spf=pass (google.com: domain of patch+caf_=patchwork-forward=linaro.org@linaro.org designates 209.85.215.43 as permitted sender) smtp.mail=patch+caf_=patchwork-forward=linaro.org@linaro.org Mailing-list: list patchwork-forward@linaro.org; contact patchwork-forward+owners@linaro.org X-Google-Group-Id: 836684582541 List-Post: , List-Help: , List-Archive: List-Unsubscribe: , Add dt-binding for mtk-cpufreq driver so that the driver could get SoC specific information (intermediate_clk for now) from device tree. Signed-off-by: pi-cheng.chen --- .../devicetree/bindings/cpufreq/cpufreq-mtk.txt | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) create mode 100644 Documentation/devicetree/bindings/cpufreq/cpufreq-mtk.txt diff --git a/Documentation/devicetree/bindings/cpufreq/cpufreq-mtk.txt b/Documentation/devicetree/bindings/cpufreq/cpufreq-mtk.txt new file mode 100644 index 0000000..53bf108 --- /dev/null +++ b/Documentation/devicetree/bindings/cpufreq/cpufreq-mtk.txt @@ -0,0 +1,17 @@ + +Mediatek cpufreq driver +------------------- + +Mediatek SoC cpufreq driver for CPU frequency scaling. + +Required properties: +- compatible: "mediatek,mtk-cpufreq" +- intermediate_clk: The intermediate clock source which CPUs will switch to +during CPU frequency transition. + +Examples: +-------- + mtk-cpufreq { + compatible = "mediatek,mtk-cpufreq"; + intermediate_clk = <&apmixedsys APMIXED_MAINPLL>; + };