From patchwork Thu Apr 7 10:25:30 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Roger Quadros X-Patchwork-Id: 65274 Delivered-To: patch@linaro.org Received: by 10.112.199.169 with SMTP id jl9csp378733lbc; Thu, 7 Apr 2016 03:26:09 -0700 (PDT) X-Received: by 10.98.15.142 with SMTP id 14mr3766564pfp.6.1460024757605; Thu, 07 Apr 2016 03:25:57 -0700 (PDT) Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id qy6si10887469pab.106.2016.04.07.03.25.57; Thu, 07 Apr 2016 03:25:57 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1755861AbcDGKZ4 (ORCPT + 7 others); Thu, 7 Apr 2016 06:25:56 -0400 Received: from arroyo.ext.ti.com ([192.94.94.40]:51292 "EHLO arroyo.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1755831AbcDGKZz (ORCPT ); Thu, 7 Apr 2016 06:25:55 -0400 Received: from dlelxv90.itg.ti.com ([172.17.2.17]) by arroyo.ext.ti.com (8.13.7/8.13.7) with ESMTP id u37APotj004028; Thu, 7 Apr 2016 05:25:50 -0500 Received: from DFLE72.ent.ti.com (dfle72.ent.ti.com [128.247.5.109]) by dlelxv90.itg.ti.com (8.14.3/8.13.8) with ESMTP id u37APoEE011877; Thu, 7 Apr 2016 05:25:50 -0500 Received: from dlep33.itg.ti.com (157.170.170.75) by DFLE72.ent.ti.com (128.247.5.109) with Microsoft SMTP Server id 14.3.224.2; Thu, 7 Apr 2016 05:25:50 -0500 Received: from lta0400828d.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by dlep33.itg.ti.com (8.14.3/8.13.8) with ESMTP id u37APfFY032760; Thu, 7 Apr 2016 05:25:48 -0500 From: Roger Quadros To: CC: , , , , Roger Quadros Subject: [PATCH 03/13] ARM: dts: omap5: Enable gpio and interrupt controller for GPMC Date: Thu, 7 Apr 2016 13:25:30 +0300 Message-ID: <1460024740-19716-4-git-send-email-rogerq@ti.com> X-Mailer: git-send-email 2.5.0 In-Reply-To: <1460024740-19716-1-git-send-email-rogerq@ti.com> References: <1460024740-19716-1-git-send-email-rogerq@ti.com> MIME-Version: 1.0 Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org GPMC driver provides interrupts and gpio for the GPMC_WAIT pins. Mark it as gpio and interrupt capable. Signed-off-by: Roger Quadros --- arch/arm/boot/dts/omap5.dtsi | 4 ++++ 1 file changed, 4 insertions(+) -- 2.5.0 -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html diff --git a/arch/arm/boot/dts/omap5.dtsi b/arch/arm/boot/dts/omap5.dtsi index 38805eb..aecdc69 100644 --- a/arch/arm/boot/dts/omap5.dtsi +++ b/arch/arm/boot/dts/omap5.dtsi @@ -398,6 +398,10 @@ ti,hwmods = "gpmc"; clocks = <&l3_iclk_div>; clock-names = "fck"; + interrupt-controller; + #interrupt-cells = <2>; + gpio-controller; + #gpio-cells = <2>; }; i2c1: i2c@48070000 {