From patchwork Wed Sep 14 05:12:06 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kishon Vijay Abraham I X-Patchwork-Id: 76132 Delivered-To: patch@linaro.org Received: by 10.140.106.72 with SMTP id d66csp1693139qgf; Tue, 13 Sep 2016 22:14:18 -0700 (PDT) X-Received: by 10.98.14.20 with SMTP id w20mr1142424pfi.9.1473830058281; Tue, 13 Sep 2016 22:14:18 -0700 (PDT) Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id h2si2703202pah.243.2016.09.13.22.14.18; Tue, 13 Sep 2016 22:14:18 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1759196AbcINFOQ (ORCPT + 7 others); Wed, 14 Sep 2016 01:14:16 -0400 Received: from comal.ext.ti.com ([198.47.26.152]:57366 "EHLO comal.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1759482AbcINFON (ORCPT ); Wed, 14 Sep 2016 01:14:13 -0400 Received: from dlelxv90.itg.ti.com ([172.17.2.17]) by comal.ext.ti.com (8.13.7/8.13.7) with ESMTP id u8E5DJ7u007618; Wed, 14 Sep 2016 00:13:19 -0500 Received: from DFLE72.ent.ti.com (dfle72.ent.ti.com [128.247.5.109]) by dlelxv90.itg.ti.com (8.14.3/8.13.8) with ESMTP id u8E5DIwK032117; Wed, 14 Sep 2016 00:13:18 -0500 Received: from dflp33.itg.ti.com (10.64.6.16) by DFLE72.ent.ti.com (128.247.5.109) with Microsoft SMTP Server id 14.3.294.0; Wed, 14 Sep 2016 00:13:17 -0500 Received: from a0393678ub.india.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by dflp33.itg.ti.com (8.14.3/8.13.8) with ESMTP id u8E5CHvQ003576; Wed, 14 Sep 2016 00:13:12 -0500 From: Kishon Vijay Abraham I To: Bjorn Helgaas , Arnd Bergmann , Jingoo Han , , , , , Pratyush Anand CC: , , , , , , Joao Pinto , Rob Herring , , Subject: [RFC PATCH 10/11] ARM: dts: DRA7: Modify pcie1 dt node for EP mode Date: Wed, 14 Sep 2016 10:42:06 +0530 Message-ID: <1473829927-20466-11-git-send-email-kishon@ti.com> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: <1473829927-20466-1-git-send-email-kishon@ti.com> References: <1473829927-20466-1-git-send-email-kishon@ti.com> MIME-Version: 1.0 Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Modify pcie1 dt node in order for the controller to operate in endpoint mode. This is used only for testing EP mode. Signed-off-by: Kishon Vijay Abraham I --- arch/arm/boot/dts/dra7.dtsi | 43 +++++++++++-------------------------------- 1 file changed, 11 insertions(+), 32 deletions(-) -- 1.7.9.5 -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html diff --git a/arch/arm/boot/dts/dra7.dtsi b/arch/arm/boot/dts/dra7.dtsi index d9bfb94..73f63d1 100644 --- a/arch/arm/boot/dts/dra7.dtsi +++ b/arch/arm/boot/dts/dra7.dtsi @@ -283,38 +283,17 @@ }; }; - axi@0 { - compatible = "simple-bus"; - #size-cells = <1>; - #address-cells = <1>; - ranges = <0x51000000 0x51000000 0x3000 - 0x0 0x20000000 0x10000000>; - pcie1: pcie@51000000 { - compatible = "ti,dra7-pcie"; - reg = <0x51000000 0x2000>, <0x51002000 0x14c>, <0x1000 0x2000>; - reg-names = "rc_dbics", "ti_conf", "config"; - interrupts = <0 232 0x4>, <0 233 0x4>; - #address-cells = <3>; - #size-cells = <2>; - device_type = "pci"; - ranges = <0x81000000 0 0 0x03000 0 0x00010000 - 0x82000000 0 0x20013000 0x13000 0 0xffed000>; - #interrupt-cells = <1>; - num-lanes = <1>; - ti,hwmods = "pcie1"; - phys = <&pcie1_phy>; - phy-names = "pcie-phy0"; - interrupt-map-mask = <0 0 0 7>; - interrupt-map = <0 0 0 1 &pcie1_intc 1>, - <0 0 0 2 &pcie1_intc 2>, - <0 0 0 3 &pcie1_intc 3>, - <0 0 0 4 &pcie1_intc 4>; - pcie1_intc: interrupt-controller { - interrupt-controller; - #address-cells = <0>; - #interrupt-cells = <1>; - }; - }; + pcie1: pcie@51000000 { + compatible = "ti,dra7-pcie-ep"; + reg = <0x51000000 0x28>, <0x51002000 0x14c>, <0x51001000 0x28>; + reg-names = "ep_dbics", "ti_conf", "ep_dbics2"; + interrupts = <0 232 0x4>; + num-lanes = <1>; + num-ib-windows = <4>; + num-ob-windows = <16>; + ti,hwmods = "pcie1"; + phys = <&pcie1_phy>; + phy-names = "pcie-phy0"; }; axi@1 {