From patchwork Thu Oct 20 01:15:26 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Masahiro Yamada X-Patchwork-Id: 78370 Delivered-To: patch@linaro.org Received: by 10.140.97.247 with SMTP id m110csp533683qge; Wed, 19 Oct 2016 18:14:02 -0700 (PDT) X-Received: by 10.98.10.153 with SMTP id 25mr16208099pfk.3.1476926042605; Wed, 19 Oct 2016 18:14:02 -0700 (PDT) Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id y6si21340375pff.4.2016.10.19.18.14.02; Wed, 19 Oct 2016 18:14:02 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=neutral (body hash did not verify) header.i=@nifty.com; spf=pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1756440AbcJTBN7 (ORCPT + 7 others); Wed, 19 Oct 2016 21:13:59 -0400 Received: from conuserg-09.nifty.com ([210.131.2.76]:28333 "EHLO conuserg-09.nifty.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1754175AbcJTBN6 (ORCPT ); Wed, 19 Oct 2016 21:13:58 -0400 Received: from beagle.diag.org (p14092-ipngnfx01kyoto.kyoto.ocn.ne.jp [153.142.97.92]) (authenticated) by conuserg-09.nifty.com with ESMTP id u9K1D0sf008597; Thu, 20 Oct 2016 10:13:01 +0900 DKIM-Filter: OpenDKIM Filter v2.10.3 conuserg-09.nifty.com u9K1D0sf008597 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nifty.com; s=dec2015msa; t=1476925982; bh=aenWBcgN1Qg3BuwDqpLCkf3tvLCaWYuAE3mETGw9Lkg=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=0aQ3z3jSdTkmaGmU/tcGs+reW340utXgiZoJB2ZSZf7Clg4ChtnKPSEkjqDRkp7Tr ffDDL9ToCm9TfP7TIMIG4ibPeO6Qx6XpPqyo345Z7EPw1Igyp/kVApb8jx/es7zCcQ BYI3Jf3P1DYmk7dg7RQo26OoeQDr9iMaeOBI/Faml7OoZQPJPuZwUgiSUiiJNERAA5 hZ6gzLzMoRXsNcaBl1NGXzrT2xAPzjQv6OhTLC/BYdQnIRu66qgoQRc2LtmGLx1P0v wH1uOGhdek5LU11ixb8vVWhM5CgRbWTXsdJxn8e7YMwCbAQcepfksdCrzeRQdvF1uF lxnJ+iefjE1UA== X-Nifty-SrcIP: [153.142.97.92] From: Masahiro Yamada To: linux-arm-kernel@lists.infradead.org Cc: Viresh Kumar , Masahiro Yamada , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Rob Herring , Will Deacon , Mark Rutland , Catalin Marinas Subject: [PATCH v2 2/2] arm64: dts: uniphier: add CPU clocks and OPP tables for LD20 SoC Date: Thu, 20 Oct 2016 10:15:26 +0900 Message-Id: <1476926126-6079-2-git-send-email-yamada.masahiro@socionext.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1476926126-6079-1-git-send-email-yamada.masahiro@socionext.com> References: <1476926126-6079-1-git-send-email-yamada.masahiro@socionext.com> Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Add a CPU clock to every CPU node and CPU OPP tables to use the generic cpufreq driver. All the CPUs in each cluster share the same OPP table. Note: clock-latency-ns (300ns) was calculated based on the CPU-gear switch sequencer spec; it takes 12 clock cycles on the sequencer running at 50 MHz, plus a bit additional latency. Signed-off-by: Masahiro Yamada --- Changes in v2: - Match the node name to the opp-hz property. arch/arm64/boot/dts/socionext/uniphier-ld20.dtsi | 84 ++++++++++++++++++++++++ 1 file changed, 84 insertions(+) -- 1.9.1 -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html diff --git a/arch/arm64/boot/dts/socionext/uniphier-ld20.dtsi b/arch/arm64/boot/dts/socionext/uniphier-ld20.dtsi index 6f48e82..7404678 100644 --- a/arch/arm64/boot/dts/socionext/uniphier-ld20.dtsi +++ b/arch/arm64/boot/dts/socionext/uniphier-ld20.dtsi @@ -79,28 +79,36 @@ device_type = "cpu"; compatible = "arm,cortex-a72", "arm,armv8"; reg = <0 0x000>; + clocks = <&sys_clk 32>; enable-method = "psci"; + operating-points-v2 = <&cluster0_opp>; }; cpu1: cpu@1 { device_type = "cpu"; compatible = "arm,cortex-a72", "arm,armv8"; reg = <0 0x001>; + clocks = <&sys_clk 32>; enable-method = "psci"; + operating-points-v2 = <&cluster0_opp>; }; cpu2: cpu@100 { device_type = "cpu"; compatible = "arm,cortex-a53", "arm,armv8"; reg = <0 0x100>; + clocks = <&sys_clk 33>; enable-method = "psci"; + operating-points-v2 = <&cluster1_opp>; }; cpu3: cpu@101 { device_type = "cpu"; compatible = "arm,cortex-a53", "arm,armv8"; reg = <0 0x101>; + clocks = <&sys_clk 33>; enable-method = "psci"; + operating-points-v2 = <&cluster1_opp>; }; }; @@ -109,6 +117,82 @@ method = "smc"; }; + cluster0_opp: opp_table0 { + compatible = "operating-points-v2"; + opp-shared; + + opp@250000000 { + opp-hz = /bits/ 64 <250000000>; + clock-latency-ns = <300>; + }; + opp@275000000 { + opp-hz = /bits/ 64 <275000000>; + clock-latency-ns = <300>; + }; + opp@500000000 { + opp-hz = /bits/ 64 <500000000>; + clock-latency-ns = <300>; + }; + opp@550000000 { + opp-hz = /bits/ 64 <550000000>; + clock-latency-ns = <300>; + }; + opp@666667000 { + opp-hz = /bits/ 64 <666667000>; + clock-latency-ns = <300>; + }; + opp@733334000 { + opp-hz = /bits/ 64 <733334000>; + clock-latency-ns = <300>; + }; + opp@1000000000 { + opp-hz = /bits/ 64 <1000000000>; + clock-latency-ns = <300>; + }; + opp@1100000000 { + opp-hz = /bits/ 64 <1100000000>; + clock-latency-ns = <300>; + }; + }; + + cluster1_opp: opp_table1 { + compatible = "operating-points-v2"; + opp-shared; + + opp@250000000 { + opp-hz = /bits/ 64 <250000000>; + clock-latency-ns = <300>; + }; + opp@275000000 { + opp-hz = /bits/ 64 <275000000>; + clock-latency-ns = <300>; + }; + opp@500000000 { + opp-hz = /bits/ 64 <500000000>; + clock-latency-ns = <300>; + }; + opp@550000000 { + opp-hz = /bits/ 64 <550000000>; + clock-latency-ns = <300>; + }; + opp@666666666 { + opp-hz = /bits/ 64 <666667000>; + clock-latency-ns = <300>; + }; + opp@733333333 { + opp-hz = /bits/ 64 <733334000>; + clock-latency-ns = <300>; + }; + opp@1000000000 { + opp-hz = /bits/ 64 <1000000000>; + clock-latency-ns = <300>; + }; + opp@1100000000 { + opp-hz = /bits/ 64 <1100000000>; + clock-latency-ns = <300>; + }; + }; + clocks { refclk: ref { compatible = "fixed-clock";