From patchwork Tue Nov 15 12:16:02 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ding Tianhong X-Patchwork-Id: 82324 Delivered-To: patch@linaro.org Received: by 10.140.97.165 with SMTP id m34csp1496892qge; Tue, 15 Nov 2016 04:20:05 -0800 (PST) X-Received: by 10.98.137.21 with SMTP id v21mr46717329pfd.48.1479212405863; Tue, 15 Nov 2016 04:20:05 -0800 (PST) Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id r197si26265489pfr.213.2016.11.15.04.20.05; Tue, 15 Nov 2016 04:20:05 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S932335AbcKOMUC (ORCPT + 7 others); Tue, 15 Nov 2016 07:20:02 -0500 Received: from szxga02-in.huawei.com ([119.145.14.65]:27812 "EHLO szxga02-in.huawei.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S933682AbcKOMUA (ORCPT ); Tue, 15 Nov 2016 07:20:00 -0500 Received: from 172.24.1.137 (EHLO szxeml431-hub.china.huawei.com) ([172.24.1.137]) by szxrg02-dlp.huawei.com (MOS 4.3.7-GA FastPath queued) with ESMTP id DQR69129; Tue, 15 Nov 2016 20:18:02 +0800 (CST) Received: from localhost (10.177.23.32) by szxeml431-hub.china.huawei.com (10.82.67.208) with Microsoft SMTP Server id 14.3.235.1; Tue, 15 Nov 2016 20:16:19 +0800 From: Ding Tianhong To: , , , , , , , , , , CC: Ding Tianhong Subject: [PATCH v4 1/6] arm64: arch_timer: Add device tree binding for hisilicon-161601 erratum Date: Tue, 15 Nov 2016 20:16:02 +0800 Message-ID: <1479212167-5812-1-git-send-email-dingtianhong@huawei.com> X-Mailer: git-send-email 1.8.5.2.msysgit.0 MIME-Version: 1.0 X-Originating-IP: [10.177.23.32] X-CFilter-Loop: Reflected Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org This erratum describes a bug in logic outside the core, so MIDR can't be used to identify its presence, and reading an SoC-specific revision register from common arch timer code would be awkward. So, describe it in the device tree. v2: Use the new erratum name and update the description. Signed-off-by: Ding Tianhong Acked-by: Rob Herring --- Documentation/devicetree/bindings/arm/arch_timer.txt | 8 ++++++++ 1 file changed, 8 insertions(+) -- 1.9.0 -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html diff --git a/Documentation/devicetree/bindings/arm/arch_timer.txt b/Documentation/devicetree/bindings/arm/arch_timer.txt index ef5fbe9..c27b2c4 100644 --- a/Documentation/devicetree/bindings/arm/arch_timer.txt +++ b/Documentation/devicetree/bindings/arm/arch_timer.txt @@ -31,6 +31,14 @@ to deliver its interrupts via SPIs. This also affects writes to the tval register, due to the implicit counter read. +- hisilicon,erratum-161601 : A boolean property. Indicates the presence of + erratum 161601, which says that reading the counter is unreliable unless + reading twice on the register and the value of the second read is larger + than the first by less than 32. If the verification is unsuccessful, then + discard the value of this read and repeat this procedure until the verification + is successful. This also affects writes to the tval register, due to the + implicit counter read. + ** Optional properties: - arm,cpu-registers-not-fw-configured : Firmware does not initialize