From patchwork Thu Dec 1 12:02:41 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Baoyou Xie X-Patchwork-Id: 86027 Delivered-To: patch@linaro.org Received: by 10.140.20.101 with SMTP id 92csp657256qgi; Thu, 1 Dec 2016 04:03:21 -0800 (PST) X-Received: by 10.84.206.37 with SMTP id f34mr83928492ple.127.1480593801273; Thu, 01 Dec 2016 04:03:21 -0800 (PST) Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id h68si68978130pfe.37.2016.12.01.04.03.21; Thu, 01 Dec 2016 04:03:21 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org; spf=pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=fail (p=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1754322AbcLAMDS (ORCPT + 7 others); Thu, 1 Dec 2016 07:03:18 -0500 Received: from mail-pg0-f51.google.com ([74.125.83.51]:34509 "EHLO mail-pg0-f51.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1756723AbcLAMDS (ORCPT ); Thu, 1 Dec 2016 07:03:18 -0500 Received: by mail-pg0-f51.google.com with SMTP id x23so94608263pgx.1 for ; Thu, 01 Dec 2016 04:03:17 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id; bh=zLTf54Y8CgiNs9JOcLfliK1r+r+wrY6n0KxNuVqdD24=; b=EgJ8G7t5DTB3+x07v01v7oiD3XR35zQxS7N4Obnqy4Da1nSlXdYByhlkMDQ/976iob G5iVM4R9ZNg8sWsjXcpEbh3xek+kh34msCgY6yIQVg1yOP9ZE4oSuQFd9/2JCe+m0Wql j9em3KKg/pTbU1UgJ64jsKqmrVNpuD72JWu5E= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id; bh=zLTf54Y8CgiNs9JOcLfliK1r+r+wrY6n0KxNuVqdD24=; b=hsftxSmY1K+8gLTg0GHPbg9aZvBRIg9M72bYP+jxcd8Na+0lw6/VTtbbPCFzYhG7Qh DSzr/NwFF1urc7dQCB40N92hpE1NNIdJL8AJzGRk0dIgEFDi2pfk0bXnMq6IeQprVTVs VygHQ1v7MmSjJjM8iqQQM9NMxwa6V/wBnrhuv1mvSRtp/Fpehz8lHzRegYHt78O+uQbk mkrqoaom7WDxCrXj63S+PRxw5pYUgRShCEp2mRr38B8ahiGIQQR8KWlk3Kp9RmjccTCO X+oO/Vn02dqysurIYk2HbnIc/kNHPWM2yt4fbmF3RmjaN59PNv3h1VPLSCyXTLVAWldd wr4g== X-Gm-Message-State: AKaTC01b2tl+8G+dfa93jfHDo5qhD72cjbwRwAmWFOfTg0NSWjNmvGOPKjPeMzWNvLex6PTC X-Received: by 10.84.138.165 with SMTP id 34mr83740932plp.20.1480593797363; Thu, 01 Dec 2016 04:03:17 -0800 (PST) Received: from localhost.localdomain ([104.237.91.218]) by smtp.gmail.com with ESMTPSA id c128sm110347461pfc.39.2016.12.01.04.03.07 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Thu, 01 Dec 2016 04:03:16 -0800 (PST) From: Baoyou Xie To: robh+dt@kernel.org, mark.rutland@arm.com, catalin.marinas@arm.com, will.deacon@arm.com, jun.nie@linaro.org, shawnguo@kernel.org Cc: devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, baoyou.xie@linaro.org, xie.baoyou@zte.com.cn, chen.chaokai@zte.com.cn, wang.qiang01@zte.com.cn Subject: [PATCH 1/3] arm64: dts: zx: support cpu-freq for zx296718 Date: Thu, 1 Dec 2016 20:02:41 +0800 Message-Id: <1480593761-27139-1-git-send-email-baoyou.xie@linaro.org> X-Mailer: git-send-email 2.7.4 Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org This patch adds the CPU clock phandle in CPU's node and uses operating-points-v2 to register operating points. So it can be used by cpufreq-dt driver. Signed-off-by: Baoyou Xie --- arch/arm64/boot/dts/zte/zx296718.dtsi | 37 +++++++++++++++++++++++++++++++++++ 1 file changed, 37 insertions(+) -- 2.7.4 -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html diff --git a/arch/arm64/boot/dts/zte/zx296718.dtsi b/arch/arm64/boot/dts/zte/zx296718.dtsi index 7a1aed7..16f7d5e 100644 --- a/arch/arm64/boot/dts/zte/zx296718.dtsi +++ b/arch/arm64/boot/dts/zte/zx296718.dtsi @@ -44,6 +44,7 @@ #include #include #include +#include / { compatible = "zte,zx296718"; @@ -81,6 +82,8 @@ compatible = "arm,cortex-a53","arm,armv8"; reg = <0x0 0x0>; enable-method = "psci"; + clocks = <&topcrm A53_GATE>; + operating-points-v2 = <&cluster0_opp>; }; cpu1: cpu@1 { @@ -88,6 +91,7 @@ compatible = "arm,cortex-a53","arm,armv8"; reg = <0x0 0x1>; enable-method = "psci"; + operating-points-v2 = <&cluster0_opp>; }; cpu2: cpu@2 { @@ -95,6 +99,7 @@ compatible = "arm,cortex-a53","arm,armv8"; reg = <0x0 0x2>; enable-method = "psci"; + operating-points-v2 = <&cluster0_opp>; }; cpu3: cpu@3 { @@ -102,6 +107,38 @@ compatible = "arm,cortex-a53","arm,armv8"; reg = <0x0 0x3>; enable-method = "psci"; + operating-points-v2 = <&cluster0_opp>; + }; + }; + + cluster0_opp: opp_table0 { + compatible = "operating-points-v2"; + opp-shared; + + opp@500000000 { + opp-hz = /bits/ 64 <500000000>; + opp-microvolt = <857000>; + clock-latency-ns = <500000>; + }; + opp@648000000 { + opp-hz = /bits/ 64 <648000000>; + opp-microvolt = <857000>; + clock-latency-ns = <500000>; + }; + opp@800000000 { + opp-hz = /bits/ 64 <800000000>; + opp-microvolt = <882000>; + clock-latency-ns = <500000>; + }; + opp@1000000000 { + opp-hz = /bits/ 64 <1000000000>; + opp-microvolt = <892000>; + clock-latency-ns = <500000>; + }; + opp@1188000000 { + opp-hz = /bits/ 64 <1188000000>; + opp-microvolt = <1009000>; + clock-latency-ns = <500000>; }; };