From patchwork Fri Dec 9 02:11:44 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Zhangfei Gao X-Patchwork-Id: 87362 Delivered-To: patch@linaro.org Received: by 10.140.20.101 with SMTP id 92csp84514qgi; Thu, 8 Dec 2016 18:12:34 -0800 (PST) X-Received: by 10.99.100.132 with SMTP id y126mr135798667pgb.177.1481249554131; Thu, 08 Dec 2016 18:12:34 -0800 (PST) Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id s77si31221667pfa.20.2016.12.08.18.12.33; Thu, 08 Dec 2016 18:12:34 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org; spf=pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=fail (p=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S932985AbcLICMc (ORCPT + 7 others); Thu, 8 Dec 2016 21:12:32 -0500 Received: from mail-pg0-f48.google.com ([74.125.83.48]:36790 "EHLO mail-pg0-f48.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S932822AbcLICMc (ORCPT ); Thu, 8 Dec 2016 21:12:32 -0500 Received: by mail-pg0-f48.google.com with SMTP id f188so2017333pgc.3 for ; Thu, 08 Dec 2016 18:12:31 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=ie9UYl9UlszL9SlvmzQ+X85oRlIQx8VoTGaRc3rS3DA=; b=QSrjRZftMzLEI+X2zZN6EfEPliIr+3olr15IPusBfhB9XaWUtUCZlTiBCEFMwlkVSp ylnzRdfx1nPeV+FTndHpAXT7hoDzhWMSymY+wZDfzsNeXYz7uh1m7QiQBlM/Ch0V5Mee yQ5KSG5EnFPZhDaQPGqGBy9R25jiuH2PafXxw= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=ie9UYl9UlszL9SlvmzQ+X85oRlIQx8VoTGaRc3rS3DA=; b=QqSH5Yl2HzzSUgZZ6NNEAhoA0bRALIa/I8TIBVRJJrai8InawyQuqWXwgcCl28IidK majCVbninwVfomw5hpIS1/2JC29kVK9JROwcm/aIoH+4UYsdDXjpHrRXcGyWbUIZLNDy wc3Pxaj2uljfWVcI38qWrMM2ABOhQj3S8qYJGl1znqTbblZlnxz0idZwGjQo6DB9EKSU 0GDIm0k1QLboiuo91ig0nKSI9tafmkVLFcq57phZeYO4mWdtg9O1nIBFTYOtUurTaIpv MMGdkb9Hs83XsZ69rSxzaZvhJhVOYjs6qftDxVMVONE/czeAe+jsQ85bgEdwsBtb00ag 93UQ== X-Gm-Message-State: AKaTC031RfWecI33vL+OY5xGjflJqWtAruYmzMphbwHC2RMX/9L+hi73WdQeARto+nIkRcuj X-Received: by 10.99.50.67 with SMTP id y64mr138252897pgy.146.1481249551373; Thu, 08 Dec 2016 18:12:31 -0800 (PST) Received: from localhost.localdomain ([45.56.152.14]) by smtp.gmail.com with ESMTPSA id u3sm22913257pfk.3.2016.12.08.18.12.17 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Thu, 08 Dec 2016 18:12:30 -0800 (PST) From: Zhangfei Gao To: Rob Herring , Philipp Zabel , Arnd Bergmann Cc: linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, Zhangfei Gao Subject: [PATCH] dt-bindings: Document the hi3660 reset bindings Date: Fri, 9 Dec 2016 10:11:44 +0800 Message-Id: <1481249504-7942-1-git-send-email-zhangfei.gao@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1480989092-31847-2-git-send-email-zhangfei.gao@linaro.org> References: <1480989092-31847-2-git-send-email-zhangfei.gao@linaro.org> Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Add DT bindings documentation for hi3660 SoC reset controller. Signed-off-by: Zhangfei Gao --- .../bindings/reset/hisilicon,hi3660-reset.txt | 43 ++++++++++++++++++++++ 1 file changed, 43 insertions(+) create mode 100644 Documentation/devicetree/bindings/reset/hisilicon,hi3660-reset.txt -- 2.7.4 -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Acked-by: Rob Herring diff --git a/Documentation/devicetree/bindings/reset/hisilicon,hi3660-reset.txt b/Documentation/devicetree/bindings/reset/hisilicon,hi3660-reset.txt new file mode 100644 index 0000000..2bf3344 --- /dev/null +++ b/Documentation/devicetree/bindings/reset/hisilicon,hi3660-reset.txt @@ -0,0 +1,43 @@ +Hisilicon System Reset Controller +====================================== + +Please also refer to reset.txt in this directory for common reset +controller binding usage. + +The reset controller registers are part of the system-ctl block on +hi3660 SoC. + +Required properties: +- compatible: should be + "hisilicon,hi3660-reset" +- hisi,rst-syscon: phandle of the reset's syscon. +- #reset-cells : Specifies the number of cells needed to encode a + reset source. The type shall be a and the value shall be 2. + + Cell #1 : offset of the reset assert control + register from the syscon register base + offset + 4: deassert control register + offset + 8: status control register + Cell #2 : bit position of the reset in the reset control register + +Example: + iomcu: iomcu@ffd7e000 { + compatible = "hisilicon,hi3660-iomcu", "syscon"; + reg = <0x0 0xffd7e000 0x0 0x1000>; + }; + + iomcu_rst: iomcu_rst_controller { + compatible = "hisilicon,hi3660-reset"; + hisi,rst-syscon = <&iomcu>; + #reset-cells = <2>; + }; + +Specifying reset lines connected to IP modules +============================================== +example: + + i2c0: i2c@..... { + ... + resets = <&iomcu_rst 0x20 3>; /* offset: 0x20; bit: 3 */ + ... + };