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[209.132.180.67]) by mx.google.com with ESMTP id 1si686473plw.75.2016.12.14.21.58.50; Wed, 14 Dec 2016 21:58:50 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org; spf=pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=fail (p=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1755135AbcLOF6i (ORCPT + 7 others); Thu, 15 Dec 2016 00:58:38 -0500 Received: from mail-pf0-f176.google.com ([209.85.192.176]:34652 "EHLO mail-pf0-f176.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1755123AbcLOF6g (ORCPT ); Thu, 15 Dec 2016 00:58:36 -0500 Received: by mail-pf0-f176.google.com with SMTP id c4so7402971pfb.1 for ; Wed, 14 Dec 2016 21:58:36 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=W9ky3t8BHlGRcoOH94PpLXp02/vN2jN0y3RHZJZJeZ0=; b=cMpHUy/TphqTzK5MaZHCf0JkRpf9bhrldet6vkLHR39Kx4p/wlw07GD55FDf93xbjZ +J7QQ5uU7AIlWcBh/2w30X9dN9KqXs+39Lsy1WaQ8ubahsNVal2vFJgxAkO0J7Il16uv U/QpDcnecUECUon5nlY+YybolQ5Ax5ZWMX2jQ= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=W9ky3t8BHlGRcoOH94PpLXp02/vN2jN0y3RHZJZJeZ0=; b=HxoC1gC6m0m1YihgDoKd0PY5Dt1cgJNNegLm1SgX0apB2g4iv38exhxlOiVKwYPuBY Og7M3HGeqVVI7trPRKF5NMo4CJ6yvd2ca/9wjag5/RfD0hodLFgmBSe5CAkNyx6PgXcB wdPgCN4ow4TeF6qJppGw6GhvQFS5MygpnyaSXPul/5Am6tU/I1QLxB7G9LqvSdhJfHM2 AgxPg6nWLH0HvXETSgxTj3L4dW+ZWGjil77D358YAiaFwJl3GBc+1STCWZKelqVY3MVD QB5AK1NOcsQEkTxtr86t4779xWiu/8ta/k8h6lSwRLtilpMDE9mTI7+CfUMIPfoQafFV ChDA== X-Gm-Message-State: AKaTC00mITCQkQ+kPN93i1uiBRwNLYPJXN8jVGBquk/46NWEOZfqFG/T2cLKckEdGvAnhpON X-Received: by 10.98.59.154 with SMTP id w26mr637913pfj.112.1481781515520; Wed, 14 Dec 2016 21:58:35 -0800 (PST) Received: from localhost.localdomain ([45.56.152.27]) by smtp.gmail.com with ESMTPSA id y200sm964038pfb.16.2016.12.14.21.58.29 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Wed, 14 Dec 2016 21:58:35 -0800 (PST) From: Zhangfei Gao To: Stephen Boyd , Rob Herring , Arnd Bergmann , haojian.zhuang@linaro.org, guodong Xu Cc: linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, Zhangfei Gao Subject: [PATCH 1/2] dt-bindings: Document the hi3660 clock bindings Date: Thu, 15 Dec 2016 13:58:12 +0800 Message-Id: <1481781493-6188-2-git-send-email-zhangfei.gao@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1481781493-6188-1-git-send-email-zhangfei.gao@linaro.org> References: <1481781493-6188-1-git-send-email-zhangfei.gao@linaro.org> Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Add DT bindings documentation for hi3660 SoC clock. Signed-off-by: Zhangfei Gao --- .../devicetree/bindings/clock/hi3660-clock.txt | 42 ++++++++++++++++++++++ 1 file changed, 42 insertions(+) create mode 100644 Documentation/devicetree/bindings/clock/hi3660-clock.txt -- 2.7.4 -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html diff --git a/Documentation/devicetree/bindings/clock/hi3660-clock.txt b/Documentation/devicetree/bindings/clock/hi3660-clock.txt new file mode 100644 index 0000000..7296fd7 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/hi3660-clock.txt @@ -0,0 +1,42 @@ +* Hisilicon Hi3660 Clock Controller + +The Hi3660 clock controller generates and supplies clock to various +controllers within the Hi3660 SoC. + +Required Properties: + +- compatible: the compatible should be one of the following strings to + indicate the clock controller functionality. + + - "hisilicon,hi3660-crgctrl" + - "hisilicon,hi3660-pctrl" + - "hisilicon,hi3660-pmuctrl" + - "hisilicon,hi3660-sctrl" + - "hisilicon,hi3660-iomcu" + +- reg: physical base address of the controller and length of memory mapped + region. + +- #clock-cells: should be 1. + +Each clock is assigned an identifier and client nodes use this identifier +to specify the clock which they consume. + +All these identifier could be found in . + +Examples: + crg_ctrl: crg_ctrl@fff35000 { + compatible = "hisilicon,hi3660-crgctrl", "syscon"; + reg = <0x0 0xfff35000 0x0 0x1000>; + #clock-cells = <1>; + }; + + uart0: uart@fdf02000 { + compatible = "arm,pl011", "arm,primecell"; + reg = <0x0 0xfdf02000 0x0 0x1000>; + interrupts = ; + clocks = <&crg_ctrl HI3660_CLK_MUX_UART0>, + <&crg_ctrl HI3660_PCLK>; + clock-names = "uartclk", "apb_pclk"; + status = "disabled"; + };