From patchwork Thu Mar 30 06:46:00 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Masahiro Yamada X-Patchwork-Id: 96248 Delivered-To: patch@linaro.org Received: by 10.140.89.233 with SMTP id v96csp103833qgd; Wed, 29 Mar 2017 23:55:04 -0700 (PDT) X-Received: by 10.99.123.75 with SMTP id k11mr4374908pgn.150.1490856904011; Wed, 29 Mar 2017 23:55:04 -0700 (PDT) Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id t9si1262655pfa.157.2017.03.29.23.55.03; Wed, 29 Mar 2017 23:55:04 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=neutral (body hash did not verify) header.i=@nifty.com; spf=pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S932084AbdC3Gy6 (ORCPT + 7 others); Thu, 30 Mar 2017 02:54:58 -0400 Received: from conuserg-07.nifty.com ([210.131.2.74]:40106 "EHLO conuserg-07.nifty.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S932929AbdC3GtJ (ORCPT ); Thu, 30 Mar 2017 02:49:09 -0400 Received: from pug.e01.socionext.com (p14092-ipngnfx01kyoto.kyoto.ocn.ne.jp [153.142.97.92]) (authenticated) by conuserg-07.nifty.com with ESMTP id v2U6kUcc015463; Thu, 30 Mar 2017 15:46:49 +0900 DKIM-Filter: OpenDKIM Filter v2.10.3 conuserg-07.nifty.com v2U6kUcc015463 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nifty.com; s=dec2015msa; t=1490856411; bh=AblKcnGlp0cQX+Na6ynoVgFNtxmwnwy6u57YL8O+q+A=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=r/xsT5lMdnDQbzhYopQSoN7Mwz4llsvKvmx3qYkW3TwKXQBepJnmbvKvVdfjFUiKe jWqOB4wVa008Xw9b5zZOyzMK5OXIdx9/cyCcByK+h9r6HE7zw6d4GoLRUURavUtFOM 5irPugdxLaG4cJJfYb+/6jW/3O8IYCjlIM5RXa03xykhpn5Ecmf5zYXXvbRn44QPWT ZyAhz7mI312QX2EFqS2QyCsWo+3i49Hzj8i+a0VU203SJc1pOcEf/3wvdf/oHhStWP 2OMNwNzt0KKGFpvw1+0lW/VQJdFnzq5iPoYdCmu8sLo+uVpn6HVvj46XJVBmNDSm43 bLU7BO28rYk5g== X-Nifty-SrcIP: [153.142.97.92] From: Masahiro Yamada To: linux-mtd@lists.infradead.org Cc: Enrico Jorns , Artem Bityutskiy , Dinh Nguyen , Boris Brezillon , Marek Vasut , Graham Moore , David Woodhouse , Masami Hiramatsu , Chuanxiao Dong , Jassi Brar , Masahiro Yamada , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Brian Norris , Richard Weinberger , Cyrille Pitchen , Rob Herring , Mark Rutland Subject: [PATCH v3 14/37] mtd: nand: denali: support "nand-ecc-strength" DT property Date: Thu, 30 Mar 2017 15:46:00 +0900 Message-Id: <1490856383-31560-15-git-send-email-yamada.masahiro@socionext.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1490856383-31560-1-git-send-email-yamada.masahiro@socionext.com> References: <1490856383-31560-1-git-send-email-yamada.masahiro@socionext.com> Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Historically, this driver tried to choose as big ECC strength as possible, but it would be reasonable to allow DT to set a particular ECC strength with "nand-ecc-strength" property. This is useful when a particular ECC setting is hard-coded by firmware (or hard- wired by boot ROM). If no ECC strength is specified in DT, "nand-ecc-maximize" is implied since this was the original behavior. Signed-off-by: Masahiro Yamada Acked-by: Rob Herring --- Changes in v3: None Changes in v2: - Add available values in the binding document Documentation/devicetree/bindings/mtd/denali-nand.txt | 6 ++++++ drivers/mtd/nand/denali.c | 18 ++++++++++++++++-- drivers/mtd/nand/denali_pci.c | 1 + 3 files changed, 23 insertions(+), 2 deletions(-) -- 2.7.4 -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html diff --git a/Documentation/devicetree/bindings/mtd/denali-nand.txt b/Documentation/devicetree/bindings/mtd/denali-nand.txt index 25313c7..647618e 100644 --- a/Documentation/devicetree/bindings/mtd/denali-nand.txt +++ b/Documentation/devicetree/bindings/mtd/denali-nand.txt @@ -11,6 +11,12 @@ Optional properties: - nand-ecc-step-size: must be 512 or 1024. If not specified, default to: 512 for "altr,socfpga-denali-nand" see nand.txt for details. + - nand-ecc-strength: see nand.txt for details. Available values are: + 8, 15 for "altr,socfpga-denali-nand" + - nand-ecc-maximize: see nand.txt for details + +Note: +Either nand-ecc-strength or nand-ecc-maximize should be specified. The device tree may optionally contain sub-nodes describing partitions of the address space. See partition.txt for more detail. diff --git a/drivers/mtd/nand/denali.c b/drivers/mtd/nand/denali.c index ce87b95..2f796e3 100644 --- a/drivers/mtd/nand/denali.c +++ b/drivers/mtd/nand/denali.c @@ -1641,9 +1641,23 @@ int denali_init(struct denali_nand_info *denali) goto failed_req_irq; } - ret = denali_set_max_ecc_strength(denali); - if (ret) + if (!chip->ecc.strength && !(chip->ecc.options & NAND_ECC_MAXIMIZE)) { + dev_info(denali->dev, + "No ECC strength strategy is specified. Maximizing ECC strength\n"); + chip->ecc.options |= NAND_ECC_MAXIMIZE; + } + + if (chip->ecc.options & NAND_ECC_MAXIMIZE) { + ret = denali_set_max_ecc_strength(denali); + if (ret) + goto failed_req_irq; + } else if (!(denali->ecc_strength_avail & BIT(chip->ecc.strength))) { + dev_err(denali->dev, + "ECC strength %d is not supported on this controller.\n", + chip->ecc.strength); + ret = -EINVAL; goto failed_req_irq; + } chip->ecc.bytes = denali_calc_ecc_bytes(chip->ecc.size, chip->ecc.strength); diff --git a/drivers/mtd/nand/denali_pci.c b/drivers/mtd/nand/denali_pci.c index a1ee9f8..a39682a5 100644 --- a/drivers/mtd/nand/denali_pci.c +++ b/drivers/mtd/nand/denali_pci.c @@ -87,6 +87,7 @@ static int denali_pci_probe(struct pci_dev *dev, const struct pci_device_id *id) denali->ecc_strength_avail = BIT(15) | BIT(8); denali->caps |= DENALI_CAP_ECC_SIZE_512; + denali->nand.ecc.options |= NAND_ECC_MAXIMIZE; ret = denali_init(denali); if (ret)