From patchwork Tue Mar 27 06:57:12 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kunihiko Hayashi X-Patchwork-Id: 132466 Delivered-To: patch@linaro.org Received: by 10.46.84.29 with SMTP id i29csp4714613ljb; Mon, 26 Mar 2018 23:57:23 -0700 (PDT) X-Google-Smtp-Source: AG47ELsy6dnSgK8cXVNdNIQRzHWgjA3xr+Hq1FSeGvSa97MrffMGN/C0jBmkzvH/mzzJDfYYXrkD X-Received: by 10.98.174.23 with SMTP id q23mr32454860pff.103.1522133843014; Mon, 26 Mar 2018 23:57:23 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1522133843; cv=none; d=google.com; s=arc-20160816; b=FexjGCTao1HgJqPbFv46vyUY2jIV84FUh/226oztEy76Q26JsTv5uhNHzOalISKKjt 67pNeG9GBRCdDeXKuPvpVu2bTOZBPTKcz58t8/RTLf0uJDWcEodmj/zb9+ziPtNDS2cc GSN9eN6i3LS6SvE4f5BVJWL6397JFTg4IK62yuqO8y04MHy26SHI708c+jZikPPLVj69 8DXPWWKqcVQCkOhacIGP4+U7GTgYWyUzBjGU9e2s7rVFJmhxJEc4PHZFm1ulXfn4ZiEA XWoLwFJAVx/FQ9hjTegJecV40lVOQQwFQePGJMNw46rqskqBAIX0Y0QUfvNZcbAVtYCd RAkw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:message-id:date:subject:cc:to:from :arc-authentication-results; bh=nfqFyO7CDjV21suncTwkHkZiCeYacxRAUfQaOs95ERA=; b=e8hj1aYuGGgdPhvRborOQDA3JzP7S4yLtge7d5Pb8PAZyw/nPx5slPWpZKD+/5+zwy hbygiLRgJB6aVUmb0B0fFmNMWr+v50MNGyyI0BfIa2cUNwHMwwxPkRzFPTxvFzrWDm9O 7v19oOR5AD3nBn018QB5tCw7hVnjQlIgB5xzvp6Wp7qtWVKnJ1tCWrffDgkkRvlg8occ W52vwTDzuWBYgvOen0pFywIEeeb4FJo6VCmquk2UsnOaCZW5on2N1WEF1YO0CRoDux++ ni47XWC8Y5F9hl/VMfl65LYdoN76gAuKJqE92NLnfR2otnc8CM3di6gZeRTlKAOuvvn/ /aRw== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id b5-v6si642875pli.442.2018.03.26.23.57.22; Mon, 26 Mar 2018 23:57:23 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1750978AbeC0G5V (ORCPT + 6 others); Tue, 27 Mar 2018 02:57:21 -0400 Received: from mx.socionext.com ([202.248.49.38]:54749 "EHLO mx.socionext.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1750937AbeC0G5U (ORCPT ); Tue, 27 Mar 2018 02:57:20 -0400 Received: from unknown (HELO kinkan-ex.css.socionext.com) ([172.31.9.52]) by mx.socionext.com with ESMTP; 27 Mar 2018 15:57:18 +0900 Received: from mail.mfilter.local (m-filter-1 [10.213.24.61]) by kinkan-ex.css.socionext.com (Postfix) with ESMTP id E679C180CA5; Tue, 27 Mar 2018 15:57:18 +0900 (JST) Received: from 172.31.9.51 (172.31.9.51) by m-FILTER with ESMTP; Tue, 27 Mar 2018 15:57:18 +0900 Received: from plum.e01.socionext.com (unknown [10.213.132.32]) by kinkan.css.socionext.com (Postfix) with ESMTP id 47EF81A159F; Tue, 27 Mar 2018 15:57:18 +0900 (JST) From: Kunihiko Hayashi To: Tejun Heo , Hans de Goede , Rob Herring , Mark Rutland Cc: linux-ide@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Kunihiko Hayashi Subject: [PATCH v2] ata: ahci-platform: add reset control support Date: Tue, 27 Mar 2018 15:57:12 +0900 Message-Id: <1522133832-7760-1-git-send-email-hayashi.kunihiko@socionext.com> X-Mailer: git-send-email 2.7.4 Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Add support to get and control a list of resets for the device as optional and shared. These resets must be kept de-asserted until the device is enabled. This is specified as shared because some SoCs like UniPhier series have common reset controls with all ahci controller instances. Signed-off-by: Kunihiko Hayashi Reviewed-by: Hans de Goede Reviewed-by: Rob Herring --- Changes since v1: - add 'Reviewed-by:' lines .../devicetree/bindings/ata/ahci-platform.txt | 1 + drivers/ata/ahci.h | 1 + drivers/ata/libahci_platform.c | 24 +++++++++++++++++++--- 3 files changed, 23 insertions(+), 3 deletions(-) -- 2.7.4 -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html diff --git a/Documentation/devicetree/bindings/ata/ahci-platform.txt b/Documentation/devicetree/bindings/ata/ahci-platform.txt index c760ecb..f4006d3 100644 --- a/Documentation/devicetree/bindings/ata/ahci-platform.txt +++ b/Documentation/devicetree/bindings/ata/ahci-platform.txt @@ -30,6 +30,7 @@ compatible: Optional properties: - dma-coherent : Present if dma operations are coherent - clocks : a list of phandle + clock specifier pairs +- resets : a list of phandle + reset specifier pairs - target-supply : regulator for SATA target power - phys : reference to the SATA PHY node - phy-names : must be "sata-phy" diff --git a/drivers/ata/ahci.h b/drivers/ata/ahci.h index a9d996e..4356ef1 100644 --- a/drivers/ata/ahci.h +++ b/drivers/ata/ahci.h @@ -350,6 +350,7 @@ struct ahci_host_priv { u32 em_msg_type; /* EM message type */ bool got_runtime_pm; /* Did we do pm_runtime_get? */ struct clk *clks[AHCI_MAX_CLKS]; /* Optional */ + struct reset_control *rsts; /* Optional */ struct regulator **target_pwrs; /* Optional */ /* * If platform uses PHYs. There is a 1:1 relation between the port number and diff --git a/drivers/ata/libahci_platform.c b/drivers/ata/libahci_platform.c index 30cc8f1..46a7624 100644 --- a/drivers/ata/libahci_platform.c +++ b/drivers/ata/libahci_platform.c @@ -25,6 +25,7 @@ #include #include #include +#include #include "ahci.h" static void ahci_host_stop(struct ata_host *host); @@ -195,7 +196,8 @@ EXPORT_SYMBOL_GPL(ahci_platform_disable_regulators); * following order: * 1) Regulator * 2) Clocks (through ahci_platform_enable_clks) - * 3) Phys + * 3) Resets + * 4) Phys * * If resource enabling fails at any point the previous enabled resources * are disabled in reverse order. @@ -215,12 +217,19 @@ int ahci_platform_enable_resources(struct ahci_host_priv *hpriv) if (rc) goto disable_regulator; - rc = ahci_platform_enable_phys(hpriv); + rc = reset_control_deassert(hpriv->rsts); if (rc) goto disable_clks; + rc = ahci_platform_enable_phys(hpriv); + if (rc) + goto disable_resets; + return 0; +disable_resets: + reset_control_assert(hpriv->rsts); + disable_clks: ahci_platform_disable_clks(hpriv); @@ -239,12 +248,15 @@ EXPORT_SYMBOL_GPL(ahci_platform_enable_resources); * following order: * 1) Phys * 2) Clocks (through ahci_platform_disable_clks) - * 3) Regulator + * 3) Resets + * 4) Regulator */ void ahci_platform_disable_resources(struct ahci_host_priv *hpriv) { ahci_platform_disable_phys(hpriv); + reset_control_assert(hpriv->rsts); + ahci_platform_disable_clks(hpriv); ahci_platform_disable_regulators(hpriv); @@ -393,6 +405,12 @@ struct ahci_host_priv *ahci_platform_get_resources(struct platform_device *pdev) hpriv->clks[i] = clk; } + hpriv->rsts = devm_reset_control_array_get_optional_shared(dev); + if (IS_ERR(hpriv->rsts)) { + rc = PTR_ERR(hpriv->rsts); + goto err_out; + } + hpriv->nports = child_nodes = of_get_child_count(dev->of_node); /*