From patchwork Wed Nov 28 02:42:30 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Masahiro Yamada X-Patchwork-Id: 152173 Delivered-To: patch@linaro.org Received: by 2002:a2e:299d:0:0:0:0:0 with SMTP id p29-v6csp568027ljp; Tue, 27 Nov 2018 18:43:58 -0800 (PST) X-Google-Smtp-Source: AFSGD/XWavSK8BSAM7kulMe8R9HvVwa3geS23LA6tyXqxoptkZp4dCgfIsOO+VlTw4xnCZZoUyrW X-Received: by 2002:a17:902:22f:: with SMTP id 44mr33381895plc.137.1543373038420; Tue, 27 Nov 2018 18:43:58 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1543373038; cv=none; d=google.com; s=arc-20160816; b=EKnvnpn9ieZ/vvhCsaUXhny9LLoxz4I3PVvBpA9xbcnPdgUNUEpGYzm8FTrWKR2vXT CK5vJiZYApgMQDfFPs9HR1tEhKdYAugC5AxgJjJBTlgsvHbLQtFwOLP+l4uijNyNJrrB 6Eo0Vy24C9wOLpcboTc3s6YGshZzwO2MS6U1dycwz6gSXXwKrgxIGcujIhcfPsgjBm9N NR3qMZ9l3DWUZhw0+NVOsqw7M0rV8XNaV5IVHsqvuuXJoc9aU+1+6btbjQkzm3GqnsWo rbDMCJW2/f8HGJfHtRPpCzZC36rVBNhXhDYC+Vas/m+uMlmH1JRm3I4jaDSPq5/Pspvy JYUw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:message-id:date:subject:cc:to:from :dkim-signature:dkim-filter; bh=MLm54/hlBwHayBrPJEK83yP0Kov80dckgzbn1AG5asY=; b=aKoQ3NXHDcXex3CCZFNpsDDerJHoL7qVHG78DaSbvZoxC1Mc4NfRrgqQVhI8BJciMT 7QfCBSNtWAorTg2/MWz1KT6crkCSF6LmhfU6UtEw0G9j5ZRG53W0GuDcX1s7RARRyOVR sKMrMH7RFBkuJusIEg1Fdd5YoExv/a+2Gu5UM5VnsXvZ8laP3KC4aNtSJbRC1doPvPXh WmmbjYPMp0F/eL2dO7PGUO8JWCw1iGSrWm2BBs8F3ndCnE7bl12y+ask4jxsPfwZceo6 5pihx5Fo2eQWyEccNXJEca+we/P8DP8O8pxWIW3nOiME2TBdYh3l8Wn//hhYhCJjx/BJ IHrQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@nifty.com header.s=dec2015msa header.b=Pxf+1fBQ; spf=pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id o21si5124066pgj.415.2018.11.27.18.43.58; Tue, 27 Nov 2018 18:43:58 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@nifty.com header.s=dec2015msa header.b=Pxf+1fBQ; spf=pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726894AbeK1Nnz (ORCPT + 6 others); Wed, 28 Nov 2018 08:43:55 -0500 Received: from conuserg-11.nifty.com ([210.131.2.78]:26884 "EHLO conuserg-11.nifty.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726731AbeK1Nnz (ORCPT ); Wed, 28 Nov 2018 08:43:55 -0500 Received: from pug.e01.socionext.com (p14092-ipngnfx01kyoto.kyoto.ocn.ne.jp [153.142.97.92]) (authenticated) by conuserg-11.nifty.com with ESMTP id wAS2h2Nc017200; Wed, 28 Nov 2018 11:43:02 +0900 DKIM-Filter: OpenDKIM Filter v2.10.3 conuserg-11.nifty.com wAS2h2Nc017200 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nifty.com; s=dec2015msa; t=1543372982; bh=MLm54/hlBwHayBrPJEK83yP0Kov80dckgzbn1AG5asY=; h=From:To:Cc:Subject:Date:From; b=Pxf+1fBQje6J+ykRwUr++jGxsVllVZUd1n+K/JC/sBt260pBkHqQ7rkLGx0oqon3Y BNujwZ6Y8bxaFybaXPqpG9Kn55n7LN+OGyxkihbnKrAfqtcKJ4laUromGi2EChn4Ou 4DEjXwPUKmuOeaekoNKYIZ76DNor2DhWktUySWrIW75ZRxzSx4SjIPA0W4AjCS5gew Q6hijxdq8sIdtjbIk8nt7bh1P8rHvEwVg95n766s9ZdsM7AVvP0/v22fLkYKZr5+7u 1Pc414swK66bBPIUE0Y9iZoDOY7VmV7mZOYlsDVD63epto9pEVU+6uVQzn5130V+Yn LgrJl94w6c93g== X-Nifty-SrcIP: [153.142.97.92] From: Masahiro Yamada To: linux-arm-kernel@lists.infradead.org Cc: Masahiro Yamada , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Rob Herring , Mark Rutland Subject: [PATCH] ARM: dts: uniphier: add MIO DMAC nodes Date: Wed, 28 Nov 2018 11:42:30 +0900 Message-Id: <1543372950-16122-1-git-send-email-yamada.masahiro@socionext.com> X-Mailer: git-send-email 2.7.4 Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Add MIO-DMAC (Media IO DMA Controller) nodes, and use them as the DMA engine of SD/eMMC controllers. Signed-off-by: Masahiro Yamada --- arch/arm/boot/dts/uniphier-ld4.dtsi | 14 ++++++++++++++ arch/arm/boot/dts/uniphier-pro4.dtsi | 16 ++++++++++++++++ arch/arm/boot/dts/uniphier-sld8.dtsi | 14 ++++++++++++++ 3 files changed, 44 insertions(+) -- 2.7.4 diff --git a/arch/arm/boot/dts/uniphier-ld4.dtsi b/arch/arm/boot/dts/uniphier-ld4.dtsi index b73d594..c2706ce 100644 --- a/arch/arm/boot/dts/uniphier-ld4.dtsi +++ b/arch/arm/boot/dts/uniphier-ld4.dtsi @@ -235,6 +235,16 @@ }; }; + dmac: dma-controller@5a000000 { + compatible = "socionext,uniphier-mio-dmac"; + reg = <0x5a000000 0x1000>; + interrupts = <0 68 4>, <0 68 4>, <0 69 4>, <0 70 4>, + <0 71 4>, <0 72 4>, <0 73 4>; + clocks = <&mio_clk 7>; + resets = <&mio_rst 7>; + #dma-cells = <1>; + }; + sd: sdhc@5a400000 { compatible = "socionext,uniphier-sd-v2.91"; status = "disabled"; @@ -246,6 +256,8 @@ clocks = <&mio_clk 0>; reset-names = "host", "bridge"; resets = <&mio_rst 0>, <&mio_rst 3>; + dma-names = "rx-tx"; + dmas = <&dmac 4>; bus-width = <4>; cap-sd-highspeed; sd-uhs-sdr12; @@ -263,6 +275,8 @@ clocks = <&mio_clk 1>; reset-names = "host", "bridge", "hw"; resets = <&mio_rst 1>, <&mio_rst 4>, <&mio_rst 6>; + dma-names = "rx-tx"; + dmas = <&dmac 6>; bus-width = <8>; cap-mmc-highspeed; cap-mmc-hw-reset; diff --git a/arch/arm/boot/dts/uniphier-pro4.dtsi b/arch/arm/boot/dts/uniphier-pro4.dtsi index 0beb606..97d051e 100644 --- a/arch/arm/boot/dts/uniphier-pro4.dtsi +++ b/arch/arm/boot/dts/uniphier-pro4.dtsi @@ -269,6 +269,16 @@ }; }; + dmac: dma-controller@5a000000 { + compatible = "socionext,uniphier-mio-dmac"; + reg = <0x5a000000 0x1000>; + interrupts = <0 68 4>, <0 68 4>, <0 69 4>, <0 70 4>, + <0 71 4>, <0 72 4>, <0 73 4>, <0 74 4>; + clocks = <&mio_clk 7>; + resets = <&mio_rst 7>; + #dma-cells = <1>; + }; + sd: sdhc@5a400000 { compatible = "socionext,uniphier-sd-v2.91"; status = "disabled"; @@ -280,6 +290,8 @@ clocks = <&mio_clk 0>; reset-names = "host", "bridge"; resets = <&mio_rst 0>, <&mio_rst 3>; + dma-names = "rx-tx"; + dmas = <&dmac 4>; bus-width = <4>; cap-sd-highspeed; sd-uhs-sdr12; @@ -297,6 +309,8 @@ clocks = <&mio_clk 1>; reset-names = "host", "bridge", "hw"; resets = <&mio_rst 1>, <&mio_rst 4>, <&mio_rst 6>; + dma-names = "rx-tx"; + dmas = <&dmac 5>; bus-width = <8>; cap-mmc-highspeed; cap-mmc-hw-reset; @@ -313,6 +327,8 @@ clocks = <&mio_clk 2>; reset-names = "host", "bridge"; resets = <&mio_rst 2>, <&mio_rst 5>; + dma-names = "rx-tx"; + dmas = <&dmac 6>; bus-width = <4>; cap-sd-highspeed; }; diff --git a/arch/arm/boot/dts/uniphier-sld8.dtsi b/arch/arm/boot/dts/uniphier-sld8.dtsi index f7fcf6b..efce027 100644 --- a/arch/arm/boot/dts/uniphier-sld8.dtsi +++ b/arch/arm/boot/dts/uniphier-sld8.dtsi @@ -239,6 +239,16 @@ }; }; + dmac: dma-controller@5a000000 { + compatible = "socionext,uniphier-mio-dmac"; + reg = <0x5a000000 0x1000>; + interrupts = <0 68 4>, <0 68 4>, <0 69 4>, <0 70 4>, + <0 71 4>, <0 72 4>, <0 73 4>; + clocks = <&mio_clk 7>; + resets = <&mio_rst 7>; + #dma-cells = <1>; + }; + sd: sdhc@5a400000 { compatible = "socionext,uniphier-sd-v2.91"; status = "disabled"; @@ -250,6 +260,8 @@ clocks = <&mio_clk 0>; reset-names = "host", "bridge"; resets = <&mio_rst 0>, <&mio_rst 3>; + dma-names = "rx-tx"; + dmas = <&dmac 4>; bus-width = <4>; cap-sd-highspeed; sd-uhs-sdr12; @@ -267,6 +279,8 @@ clocks = <&mio_clk 1>; reset-names = "host", "bridge", "hw"; resets = <&mio_rst 1>, <&mio_rst 4>, <&mio_rst 6>; + dma-names = "rx-tx"; + dmas = <&dmac 6>; bus-width = <8>; cap-mmc-highspeed; cap-mmc-hw-reset;