From patchwork Wed Jan 8 01:52:05 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: =?utf-8?b?Q2h1bmZlbmcgWXVuICjkupHmmKXls7Ap?= X-Patchwork-Id: 206041 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-9.8 required=3.0 tests=DKIM_SIGNED,DKIM_VALID, DKIM_VALID_AU, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH, MAILING_LIST_MULTI, MIME_BASE64_TEXT, SIGNED_OFF_BY, SPF_HELO_NONE, UNPARSEABLE_RELAY, USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id B3EC7C33C99 for ; Wed, 8 Jan 2020 01:52:51 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 8524024676 for ; Wed, 8 Jan 2020 01:52:51 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (1024-bit key) header.d=mediatek.com header.i=@mediatek.com header.b="UN/z2HQe" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727095AbgAHBwr (ORCPT ); Tue, 7 Jan 2020 20:52:47 -0500 Received: from Mailgw01.mediatek.com ([1.203.163.78]:46630 "EHLO mailgw01.mediatek.com" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S1726992AbgAHBwj (ORCPT ); Tue, 7 Jan 2020 20:52:39 -0500 X-UUID: 6b8a1a7eab9c44619f53facb8bed77e5-20200108 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Transfer-Encoding:Content-Type:MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:CC:To:From; bh=Tn+ocDgoE7quv83eopc3270X61VLoovrwR+4z9klDjM=; b=UN/z2HQeaTRBMtzEN8N2YwZKlg2M08imkkVHjfba9dVlrUBTnaEdEcNhurpc/hwAKGZa6laqSTRPv8pQaB+Ge9SsZvmKQ16OO0lr5RrkR8r5fD8+SPpHfGM2aKFWDeTi/psFjkl+aY++3/spb3zBxr3ci81fS9x96IznyrxOR5M=; X-UUID: 6b8a1a7eab9c44619f53facb8bed77e5-20200108 Received: from mtkcas36.mediatek.inc [(172.27.4.253)] by mailgw01.mediatek.com (envelope-from ) (mailgw01.mediatek.com ESMTP with TLS) with ESMTP id 263404547; Wed, 08 Jan 2020 09:52:34 +0800 Received: from mtkcas09.mediatek.inc (172.21.101.178) by MTKMBS31N1.mediatek.inc (172.27.4.69) with Microsoft SMTP Server (TLS) id 15.0.1395.4; Wed, 8 Jan 2020 09:51:57 +0800 Received: from localhost.localdomain (10.17.3.153) by mtkcas09.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1395.4 via Frontend Transport; Wed, 8 Jan 2020 09:53:07 +0800 From: Chunfeng Yun To: Kishon Vijay Abraham I CC: Rob Herring , Mark Rutland , Matthias Brugger , , Chunfeng Yun , , , Subject: [RESEND PATCH v5 10/11] phy: phy-mtk-tphy: add a new reference clock Date: Wed, 8 Jan 2020 09:52:05 +0800 Message-ID: <1578448326-27455-10-git-send-email-chunfeng.yun@mediatek.com> X-Mailer: git-send-email 1.8.1.1.dirty In-Reply-To: <1578448326-27455-1-git-send-email-chunfeng.yun@mediatek.com> References: <1578448326-27455-1-git-send-email-chunfeng.yun@mediatek.com> MIME-Version: 1.0 X-TM-SNTS-SMTP: 394569979869DFA0C5D2DE7AD80DFBA25B01A84F9741918F098C6E7299E92AFF2000:8 X-MTK: N Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Usually the digital and analog phys use the same reference clock, but some platforms have two separate reference clocks for each of them, so add another optional clock to support them. In order to keep the clock names consistent with PHY IP's, change the da_ref for analog phy and ref clock for digital phy. Signed-off-by: Chunfeng Yun --- v3~v5: no changes v2: fix typo of analog --- drivers/phy/mediatek/phy-mtk-tphy.c | 19 ++++++++++++++++++- 1 file changed, 18 insertions(+), 1 deletion(-) -- 2.24.0 diff --git a/drivers/phy/mediatek/phy-mtk-tphy.c b/drivers/phy/mediatek/phy-mtk-tphy.c index c6424fd2a06d..cdbcc49f7115 100644 --- a/drivers/phy/mediatek/phy-mtk-tphy.c +++ b/drivers/phy/mediatek/phy-mtk-tphy.c @@ -298,7 +298,8 @@ struct mtk_phy_instance { struct u2phy_banks u2_banks; struct u3phy_banks u3_banks; }; - struct clk *ref_clk; /* reference clock of anolog phy */ + struct clk *ref_clk; /* reference clock of (digital) phy */ + struct clk *da_ref_clk; /* reference clock of analog phy */ u32 index; u8 type; int eye_src; @@ -925,6 +926,13 @@ static int mtk_phy_init(struct phy *phy) return ret; } + ret = clk_prepare_enable(instance->da_ref_clk); + if (ret) { + dev_err(tphy->dev, "failed to enable da_ref\n"); + clk_disable_unprepare(instance->ref_clk); + return ret; + } + switch (instance->type) { case PHY_TYPE_USB2: u2_phy_instance_init(tphy, instance); @@ -984,6 +992,7 @@ static int mtk_phy_exit(struct phy *phy) u2_phy_instance_exit(tphy, instance); clk_disable_unprepare(instance->ref_clk); + clk_disable_unprepare(instance->da_ref_clk); return 0; } @@ -1170,6 +1179,14 @@ static int mtk_tphy_probe(struct platform_device *pdev) retval = PTR_ERR(instance->ref_clk); goto put_child; } + + instance->da_ref_clk = + devm_clk_get_optional(&phy->dev, "da_ref"); + if (IS_ERR(instance->da_ref_clk)) { + dev_err(dev, "failed to get da_ref_clk(id-%d)\n", port); + retval = PTR_ERR(instance->da_ref_clk); + goto put_child; + } } provider = devm_of_phy_provider_register(dev, mtk_phy_xlate);