From patchwork Fri Mar 13 00:58:16 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kunihiko Hayashi X-Patchwork-Id: 203387 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-9.8 required=3.0 tests=HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH, MAILING_LIST_MULTI, SIGNED_OFF_BY, SPF_HELO_NONE, SPF_PASS, URIBL_BLOCKED, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 9E2F9C10DCE for ; Fri, 13 Mar 2020 00:58:45 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 729A1206E7 for ; Fri, 13 Mar 2020 00:58:45 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727053AbgCMA6p (ORCPT ); Thu, 12 Mar 2020 20:58:45 -0400 Received: from mx.socionext.com ([202.248.49.38]:4532 "EHLO mx.socionext.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727085AbgCMA6o (ORCPT ); Thu, 12 Mar 2020 20:58:44 -0400 Received: from unknown (HELO iyokan-ex.css.socionext.com) ([172.31.9.54]) by mx.socionext.com with ESMTP; 13 Mar 2020 09:58:43 +0900 Received: from mail.mfilter.local (m-filter-2 [10.213.24.62]) by iyokan-ex.css.socionext.com (Postfix) with ESMTP id 873CA603AB; Fri, 13 Mar 2020 09:58:43 +0900 (JST) Received: from 172.31.9.51 (172.31.9.51) by m-FILTER with ESMTP; Fri, 13 Mar 2020 09:58:43 +0900 Received: from plum.e01.socionext.com (unknown [10.213.132.32]) by kinkan.css.socionext.com (Postfix) with ESMTP id EB6E41A01BB; Fri, 13 Mar 2020 09:58:42 +0900 (JST) From: Kunihiko Hayashi To: Masahiro Yamada , Rob Herring Cc: devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Masami Hiramatsu , Jassi Brar , Kunihiko Hayashi Subject: [PATCH 10/10] arm64: dts: uniphier: Stabilize Ethernet RGMII mode of LD20 global and PXs3 ref board Date: Fri, 13 Mar 2020 09:58:16 +0900 Message-Id: <1584061096-23686-11-git-send-email-hayashi.kunihiko@socionext.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1584061096-23686-1-git-send-email-hayashi.kunihiko@socionext.com> References: <1584061096-23686-1-git-send-email-hayashi.kunihiko@socionext.com> Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org The RGMII PHY needs to change drive-strength properties of the Ethernet Tx pins to stabilize the PHY. The devicetree for LD20 global board specifies RMII PHY in the ethernet node as default, however, there is also another board that has RGMII PHY. The devicetree for the board doesn't exist, so the users should change the ethernet properties by outside way. Signed-off-by: Kunihiko Hayashi --- arch/arm64/boot/dts/socionext/uniphier-ld20-global.dts | 13 +++++++++++++ arch/arm64/boot/dts/socionext/uniphier-pxs3-ref.dts | 16 ++++++++++++++++ 2 files changed, 29 insertions(+) diff --git a/arch/arm64/boot/dts/socionext/uniphier-ld20-global.dts b/arch/arm64/boot/dts/socionext/uniphier-ld20-global.dts index 2c00008..89b133f 100644 --- a/arch/arm64/boot/dts/socionext/uniphier-ld20-global.dts +++ b/arch/arm64/boot/dts/socionext/uniphier-ld20-global.dts @@ -146,6 +146,19 @@ }; }; +&pinctrl_ether_rgmii { + tx { + pins = "RGMII_TXD0", "RGMII_TXD1", "RGMII_TXD2", + "RGMII_TXD3", "RGMII_TXCTL"; + drive-strength = <12>; + }; + + txclk { + pins = "RGMII_TXCLK"; + drive-strength = <9>; + }; +}; + &usb { status = "okay"; }; diff --git a/arch/arm64/boot/dts/socionext/uniphier-pxs3-ref.dts b/arch/arm64/boot/dts/socionext/uniphier-pxs3-ref.dts index fcab6d1..d74a6c6 100644 --- a/arch/arm64/boot/dts/socionext/uniphier-pxs3-ref.dts +++ b/arch/arm64/boot/dts/socionext/uniphier-pxs3-ref.dts @@ -132,3 +132,19 @@ reg = <0>; }; }; + +&pinctrl_ether_rgmii { + tx { + pins = "RGMII0_TXCLK", "RGMII0_TXD0", "RGMII0_TXD1", + "RGMII0_TXD2", "RGMII0_TXD3", "RGMII0_TXCTL"; + drive-strength = <9>; + }; +}; + +&pinctrl_ether1_rgmii { + tx { + pins = "RGMII1_TXCLK", "RGMII1_TXD0", "RGMII1_TXD1", + "RGMII1_TXD2", "RGMII1_TXD3", "RGMII1_TXCTL"; + drive-strength = <9>; + }; +};