From patchwork Thu Aug 13 16:04:06 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: vineetha.g.jaya.kumaran@intel.com X-Patchwork-Id: 253850 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-13.0 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH, MAILING_LIST_MULTI, SIGNED_OFF_BY, SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id F11EDC433E4 for ; Thu, 13 Aug 2020 16:06:32 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id CE8282078D for ; Thu, 13 Aug 2020 16:06:32 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726694AbgHMQGc (ORCPT ); Thu, 13 Aug 2020 12:06:32 -0400 Received: from mga12.intel.com ([192.55.52.136]:58407 "EHLO mga12.intel.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726131AbgHMQGb (ORCPT ); Thu, 13 Aug 2020 12:06:31 -0400 IronPort-SDR: BDSThFSJU/6IJdMf85KaGH4BvM6pLmud/YhRwfGxrw61Mdk9cR1QB2ebYL+AEdBzsRR31MAFc+ Te88E0ojgR0w== X-IronPort-AV: E=McAfee;i="6000,8403,9712"; a="133778947" X-IronPort-AV: E=Sophos;i="5.76,308,1592895600"; d="scan'208";a="133778947" X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from orsmga004.jf.intel.com ([10.7.209.38]) by fmsmga106.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 13 Aug 2020 09:06:30 -0700 IronPort-SDR: trsjl8VS3wBXiAnbGFjfz8TtplCrLWq48FhsSh4GC4iqHWVYT6cF6sPxOn9lTKjl0BZf6gjboZ 9aw8jE/ffUkQ== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.76,308,1592895600"; d="scan'208";a="439824515" Received: from vgjayaku-ilbpg7.png.intel.com ([10.88.227.96]) by orsmga004.jf.intel.com with ESMTP; 13 Aug 2020 09:06:28 -0700 From: vineetha.g.jaya.kumaran@intel.com To: thierry.reding@gmail.com, u.kleine-koenig@pengutronix.de, robh+dt@kernel.org Cc: linux-pwm@vger.kernel.org, devicetree@vger.kernel.org, wan.ahmad.zainie.wan.mohamad@intel.com, andriy.shevchenko@intel.com, lakshmi.bai.raja.subramanian@intel.com Subject: [PATCH v3 2/2] dt-bindings: pwm: keembay: Add bindings for Intel Keem Bay PWM Date: Fri, 14 Aug 2020 00:04:06 +0800 Message-Id: <1597334646-21087-3-git-send-email-vineetha.g.jaya.kumaran@intel.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1597334646-21087-1-git-send-email-vineetha.g.jaya.kumaran@intel.com> References: <1597334646-21087-1-git-send-email-vineetha.g.jaya.kumaran@intel.com> Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org From: "Vineetha G. Jaya Kumaran" Add PWM Device Tree bindings documentation for the Intel Keem Bay SoC. Reviewed-by: Rob Herring Signed-off-by: Vineetha G. Jaya Kumaran --- .../devicetree/bindings/pwm/intel,keembay-pwm.yaml | 47 ++++++++++++++++++++++ 1 file changed, 47 insertions(+) create mode 100644 Documentation/devicetree/bindings/pwm/intel,keembay-pwm.yaml diff --git a/Documentation/devicetree/bindings/pwm/intel,keembay-pwm.yaml b/Documentation/devicetree/bindings/pwm/intel,keembay-pwm.yaml new file mode 100644 index 00000000..a374334 --- /dev/null +++ b/Documentation/devicetree/bindings/pwm/intel,keembay-pwm.yaml @@ -0,0 +1,47 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +# Copyright (C) 2020 Intel Corporation +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pwm/intel,keembay-pwm.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Intel Keem Bay PWM Device Tree Bindings + +maintainers: + - Vineetha G. Jaya Kumaran + +allOf: + - $ref: pwm.yaml# + +properties: + compatible: + enum: + - intel,keembay-pwm + + reg: + maxItems: 1 + + clocks: + maxItems: 1 + + "#pwm-cells": + const: 2 + +required: + - compatible + - reg + - clocks + - '#pwm-cells' + +additionalProperties: false + +examples: + - | + #define KEEM_BAY_A53_GPIO + + pwm@203200a0 { + compatible = "intel,keembay-pwm"; + reg = <0x203200a0 0xe8>; + clocks = <&scmi_clk KEEM_BAY_A53_GPIO>; + #pwm-cells = <2>; + };