From patchwork Wed Sep 30 05:36:06 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kunihiko Hayashi X-Patchwork-Id: 313839 Delivered-To: patch@linaro.org Received: by 2002:a92:5ad1:0:0:0:0:0 with SMTP id b78csp4740374ilg; Tue, 29 Sep 2020 22:36:32 -0700 (PDT) X-Google-Smtp-Source: ABdhPJwX8Q/8QKw+UWOy24TOg9oh4S9CxZkDU9irjccmP5znyWxJXJs+XsMTDP0K1NbTIN+jUHV9 X-Received: by 2002:a17:906:7e0e:: with SMTP id e14mr1106103ejr.238.1601444192003; Tue, 29 Sep 2020 22:36:32 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1601444191; cv=none; d=google.com; s=arc-20160816; b=EL6L9jBXlfvdANmnAlA8v0nIep5iSaSYcn/gppYAgInZEBJEWTPDpDoQF01JWFmhUl zPC+Yxos5BDYdSmdesU6wkzx40nsB+ZOtJeLED0XBvsPKp6WNSd8d0za6DD1lxxvmTQG 2nqrpyUI7m7GdS0TA6uvcIG3yKUVTCfjGoejhaJ2H7PT+sLetHNjvN1GRS820+E0Cre9 ei3SecLzodf+w8MB/NYYKQxWBvSaM2i/ElNbZgCUejO2/GP06p4dYo/sInGTC4gz4SKo fXRBEB+DulhVyDBeGNLcd3j4F4B0iP2Vc6MxdnFYQ+yBsSFueWAB0qUUjJNeCRGeS1Qo zVFA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:references:in-reply-to:message-id:date:subject :cc:to:from; bh=9sTO2+6sshoR05fbn/I8S0NStuSfvzcogMkhhjaoGUk=; b=FV+RhE71go4LNcqbg57J+QFp7eo6EDUDuCsRH/hooRsKXzIGxwOxlaO5SdwbNoOMs/ MnL5nGdautYrCmvG0jsBLfVuzTE1O4Sde51e6e5DHhy/TGKLI6tWl21DzmDtSd82+QmN aAtRFBMyClcTBrZq92+5FS8iv79qz80QU2DetfG48XqS4cEoeREvtDcFt94448hOrqJd 4pd8zv1I3G/86WYWPHXd/1JuDjXsKD6rze6bq6CwplkF9saGjyh1hN2LqZukcHZpFdT0 gG03c4DTJow5QbxSSgRgvHAqgEmVL52Vb/sBXTAtd1Ff/+BHoeNCpgIZnSPgCt4pAjyG Mj6w== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [23.128.96.18]) by mx.google.com with ESMTP id dn12si344326ejc.536.2020.09.29.22.36.31; Tue, 29 Sep 2020 22:36:31 -0700 (PDT) Received-SPF: pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; spf=pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728157AbgI3FgY (ORCPT + 6 others); Wed, 30 Sep 2020 01:36:24 -0400 Received: from mx.socionext.com ([202.248.49.38]:57202 "EHLO mx.socionext.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1725440AbgI3FgV (ORCPT ); Wed, 30 Sep 2020 01:36:21 -0400 Received: from unknown (HELO kinkan-ex.css.socionext.com) ([172.31.9.52]) by mx.socionext.com with ESMTP; 30 Sep 2020 14:36:12 +0900 Received: from mail.mfilter.local (m-filter-1 [10.213.24.61]) by kinkan-ex.css.socionext.com (Postfix) with ESMTP id 58A90180BE3; Wed, 30 Sep 2020 14:36:12 +0900 (JST) Received: from 172.31.9.51 (172.31.9.51) by m-FILTER with ESMTP; Wed, 30 Sep 2020 14:36:12 +0900 Received: from plum.e01.socionext.com (unknown [10.213.132.32]) by kinkan.css.socionext.com (Postfix) with ESMTP id DE2F61A0509; Wed, 30 Sep 2020 14:36:11 +0900 (JST) From: Kunihiko Hayashi To: Rob Herring , Bjorn Helgaas , Lorenzo Pieralisi , Jingoo Han , Gustavo Pimentel , Murali Karicheri Cc: linux-pci@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Masami Hiramatsu , Jassi Brar , Kunihiko Hayashi Subject: [PATCH v3 3/4] PCI: dwc: Add common iATU register support Date: Wed, 30 Sep 2020 14:36:06 +0900 Message-Id: <1601444167-11316-4-git-send-email-hayashi.kunihiko@socionext.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1601444167-11316-1-git-send-email-hayashi.kunihiko@socionext.com> References: <1601444167-11316-1-git-send-email-hayashi.kunihiko@socionext.com> Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org This gets iATU register area from reg property that has reg-names "atu". In Synopsys DWC version 4.80 or later, since iATU register area is separated from core register area, this area is necessary to get from DT independently. Cc: Murali Karicheri Cc: Jingoo Han Cc: Gustavo Pimentel Suggested-by: Rob Herring Signed-off-by: Kunihiko Hayashi --- drivers/pci/controller/dwc/pcie-designware.c | 5 +++++ 1 file changed, 5 insertions(+) -- 2.7.4 Reviewed-by: Rob Herring diff --git a/drivers/pci/controller/dwc/pcie-designware.c b/drivers/pci/controller/dwc/pcie-designware.c index 3fe859f..b6b39af 100644 --- a/drivers/pci/controller/dwc/pcie-designware.c +++ b/drivers/pci/controller/dwc/pcie-designware.c @@ -10,6 +10,7 @@ #include #include +#include #include #include "../../pci.h" @@ -548,11 +549,15 @@ void dw_pcie_setup(struct dw_pcie *pci) u32 val; struct device *dev = pci->dev; struct device_node *np = dev->of_node; + struct platform_device *pdev = to_platform_device(dev); if (pci->version >= 0x480A || (!pci->version && dw_pcie_iatu_unroll_enabled(pci))) { pci->iatu_unroll_enabled = true; if (!pci->atu_base) + pci->atu_base = + devm_platform_ioremap_resource_byname(pdev, "atu"); + if (IS_ERR(pci->atu_base)) pci->atu_base = pci->dbi_base + DEFAULT_DBI_ATU_OFFSET; } dev_dbg(pci->dev, "iATU unroll: %s\n", pci->iatu_unroll_enabled ?